The problem will only get worse as circuit densities are increased ... dozens of other major corporate accounts⦠..... for Modern Microcircuitsâ, IEEE IRPS, April 2002, pp. ..... Unlike hard mechanism a single failure criterion cannot be applied to.
A Tutorial on Single Event Effects in Advanced Commercial Silicon Technology Robert Baumann Component Reliability Group Silicon Technology Development Texas Instruments, Dallas, Texas
Robert Baumann
Slide 1
Tutorial Outline • Definitions & Acronyms • Radiation Environments • Radiation Effects on Silicon Devices • Testing for Radiation Sensitivity • Technology Scaling vs. Sensitivity • Mitigation • Summary Note: focus of this tutorial is on radiation-induced soft errors in components and devices. Robert Baumann
Slide 2
Definitions and Acronyms
Robert Baumann
Slide 3
Basic Definitions Hard Error An error induced by faulty device operation. DATA is lost AND data can no longer be stored at that location.
Soft Error A random error induced by an event which corrupts the DATA stored in a device. The device itself is not damaged.
Robert Baumann
Slide 4
Motivation Soft errors induce the highest failure rate of all other reliability mechanisms combined. Soft errors impact customer perception of reliability. Undetected errors are viewed as the biggest threat since their impact on applications cannot be predicted. The problem will only get worse as circuit densities are increased and voltages are decreased.
Robert Baumann
Slide 5
Historical Example Sun Screen Daniel Lyons, Forbes Global, 11.13.00 mysterious glitch has been popping up since late last year...web companies, telecommunications companies, a Baby Bell in Atlanta, an Internet domain registry on the East Coast, high-end servers made by Sun Microsystems have, for no apparent reason, suddenly crashed...It has caused problems for America Online, Ebay and dozens of other major corporate accounts…The Sun has caused crashes at dozens of customer sites. An odd problem involving stray cosmic rays and memory chips in the flagship Enterprise server line…Sun found it had been shipping servers whose cache modules contained faulty SRAM (static random access memory) chips from a supplier it won't name.
Loss of customer Loss of = confidence revenue Robert Baumann
Slide 6
Nomenclature Single bit upset
SET
Single event transient
SBU Multiple bit upset
MBU
SEE Single event effects
Single event func. interupt
SEFI Single event latch-up
SELU
Single event gate rupture/Burnout
SEGR/SEB Robert Baumann
SEU Single event upset
Soft Error Soft error rate (SER)
Hard Error Slide 7
What’s a FIT anyway? 1 failure 1 FIT = 9 10 dev − hrs. People usually hear about FITs in the context of HARD errors with typically acceptable values being 1-100 FIT. SOFT error rates, typically in 10s of kFIT for advanced products can cause some surprise! BUT…
A fail rate of 100 kFIT is ~ 1 error/year Robert Baumann
Slide 8
Causes of Soft Errors • Electromagnetic Interference (EMI) • EMI can easily be avoided with standard procedures • Can be verified by adding shielding (Faraday cage) or eliminating source
• Circuit-level electrical noise • Care in layout reduces parasitic coupling capacitance • Errors from this issue will be repeatable for specific patterns/algorithms
• Board-Level electrical noise • Mitigated through the use of bypass capacitors and multilayer PCBs • Generally limited to specific components/paths
• Ionizing Radiation • Random in time and location • Dominant “noise” in well designed systems
Robert Baumann
Slide 9
Linear Energy Transfer LET = energy deposited per unit length • LET is a function of the particle’s mass and energy and the material through which the particle is traveling. • The higher the particle mass and energy = higher the LET. The denser the material the higher the LET. LET turns the particle’s kinetic energy into charge. • LET is also known as dE/dx or stopping power and is often reported in units of MeV/mg/cm2.
Robert Baumann
Slide 10
A few parting distinctions • Directly Ionizing – Charged particles directly create e-h pairs – Particles lose energy as they travel (3.6eV per e-h pair in Si) – Particles are “stopped” when their kinetic energy is 0
• Indirectly ionizing – Nuclear reaction => ionizing reaction products – Implies rate is dependent on a reaction cross-section – Elastic and Inelastic reactions
Robert Baumann
Slide 11
Radiation Environments
Robert Baumann
Slide 12
Weapons Environment Electromagnetic Pulse * Large X- and g-ray doses are delivered within 10 -100 nsec, * followed by delayed gamma-rays at 1-10 msec, * and large neutrons fluences (> 1010 n/cm2) at 0.1 to 10msec. Courtesy DOE homepage
Effects • Total Dose Effects • Dose Rate Effects Upsets, Transients, Latchup and Burnout
• Neutron Dose
Robert Baumann
Slide 13
Space Environment & Effects Primary Cosmic Rays: Galactic Particles (E >> 1 GeV) [Big Bang left overs? Super Nova remnants?] Solar Wind (usually E < 1 GeV)
Composition (E up to 1020 eV): 92% 6% 2%
Protons Alpha Particles (He) Gamma rays and heavier nuclei
Courtesy NASA homepage
Effects •
•
Single Event Effects •
SEU
•
SET
•
SELU
Total Dose Effects
Robert Baumann
Slide 14
Aurora – Proof of Radiation
Photo courtesy of NASA homepage Robert Baumann
Slide 15
Effect of Solar Activity After M.S. Shea, et al., IEEE Trans. Nucl. Sci., 39(6), p. 1758, Dec. 1992
Time (in hours)
Photo courtesy of NASA homepage
Higher solar activity ionizes the upper atmosphere REDUCING the number of protons that get deeper into the atmosphere to create neutrons (muons, etc.) Robert Baumann
Slide 16
The “Nitrogen Filter” Protons (>> 1 GeV)
3rd-7th generation isotropic Neutrons, electrons, muons, protons (< 1 GeV) Robert Baumann
Slide 17
Neutron + Si/O Reactions Reaction table from F. Wrobel et al., IEEE Trans. Nucl. Phys., 47(6), Dec. 2000
28Si
+α 28Al + p 27Al + d 24Mg + n + α 27Al + n + p 26Mg + 3He 21Ne + 2α 25Mg
High energy neutron
With SiO2 above Si SER was increased by 36% while with SiO2 above AND below Si (such as SOI) SER was 64% higher.
2.75 MeV 4.00 MeV 9.70 MeV 10.34 MeV 12.00 MeV 12.58 MeV 12.99 MeV
after F. Wrobel et al.,”Contribution of SiO2 in Neutron-Induced SEU in SRAMs,” IEEE Trans. Nucl. Sci., 50(6), p. 2058, Dec. 2003
Robert Baumann
Slide 18
n+28Si Reaction Product LET
dQ/dx (fC/um)
200 150 SRIM2003 was used to generate this plot
100
Si28 Al28 Mg24 Ne21
50
Mg25 Al27 Mg26
0 0
2 4 6 8 10 Ion Energy (MeV) Robert Baumann
Slide 19
400 .
Relative Neutron Flux (sea-level=1)
Altitude Dependence 350 300 250 200 Terrestrial Altitudes
150
Flight Altitudes
After Eugene Normand, “Single Event Effects in Avionics”, IEEE Trans. Nucl. Sci., 43(2), April 1996, pp. 463.
100 50 0 0
20k
40k 60k 80k Altitude (Feet)
Robert Baumann
Slide 20
Latitude Dependence Relative Neutron Flux
6.0
Adapted from Eugene Normand, “Single Event Effects in Avionics”, IEEE Trans. Nucl. Sci., 43(2), April 1996, pp. 463.
5.0 4.0 3.0 2.0 1.0 0.0 0
10 20 30 40 50 60 70 80 90 Latitude (degrees) Robert Baumann
Slide 21
238U
Uranium 238
1.2
1.2
1.0
1.0
0.8
0.8
Intensity
Intensity
and 232Th alpha spectra
0.6 0.4
0.6 0.4
0.2
0.2
0.0
0.0 3
3
4 5 6 7 8 9 Alpha Energy (MeV)
Thorium 232
Robert Baumann
4 5 6 7 8 9 Alpha Energy (MeV) Slide 22
What does an alpha do in Si? 20
From radioactive impurities
80
60
10
40
Range (um)
dQ/dx (fC/um)
(232Th, 238U, 210Po, etc.)
20
0
0 0
Alpha Particle ~ 4 - 9 MeV
5
10
Particle Energy (MeV)
Robert Baumann
Slide 23
Alpha Emission Catagories Standard
10 - 0.01 α /cm2-hr
Low Alpha
< 0.01
Ultra Low Alpha
< 0.002
Hyper Low Alpha
< 0.0005
Robert Baumann
Slide 24
Alpha from chip materials Sample Description
Detector
CDL95
MDA95
average
conf.
ECD Cu 10um
4950
0.00019
0.00054
0.00036
91.47%
C027 Barrier Layer
4950
0.00012
0.00033
0.00000
-
C027 Interlevel Dielectric
4950
0.00012
0.00035
0.00039
99.96%
C021 Interlevel dielectric
4950
0.00013
0.00036
0.00027
96.41%
C021 Alternate dielectric
4950
0.00012
0.00034
0.00011
-
diborane based W process
4950
0.00012
0.00034
0.00007
-
Bare silicon wafers (C027)
4950
0.00012
0.00034
0.00004
-
Full process 8LM Cu wafer
4950
0.00013
0.00037
0.00028
96.78%
Full process 8LM Cu wafer 2
4950
0.00013
0.00072
0.00018
62.74%
Units in α/cm2-hr Robert Baumann
Slide 25
Low Energy Neutrons & Boron • R. Fleischer, IEEE Trans. Nucl. Sci., 30(5), p. 4013, Oct. 1983 • R. Baumann, et al., IEEE IRPS, p. 299 1995 • R. Baumann and E. B. Smith, Elsevier Microelec. Rel., 41(2), p. 213, 2001
Low Energy Neutron
0.84 MeV 7Li Recoil α - particle 10B
Nucleus
1.47 MeV Robert Baumann
Prompt gamma photon Slide 26
σnth (barns) 100
10-1
10-2
10-3
Robert Baumann
Boron-11
Oxygen
Phosphorus
Silicon
Aluminum
Nitrogen
Copper
Arsenic
Titanium
Tungsten
BORON 10
Cross-sections of chip materials 104
103
102
101
Slide 27
The Energies that Matter 1.0
Probability
0.8 0.6
90% of all 10B fissions are induced by neutron energies below 15 eV!
0.4 0.2 0.0 0.001 0.01
0.1
1
10
100
Neutron Energy (eV) Robert Baumann
Slide 28
Alpha & Lithium dQ/dx (fC/um)
n + 10B Reaction Product LET 30 Lithium Recoils
20 Alpha Particles
10
0 0
1
2
Particle Energy (MeV) Robert Baumann
Slide 29
Radiation Source Summary Alpha Particles • Emitted from U,Th impurities in materials • Peak dQ/dx ~ 16 fC/um • limited range (< 40 um) • Dominant in processes not screened for alphas 10B
and Low Energy Neutrons
• σth 10B is huge & highly ionizing emissions • High 10B concentration in BPSG (4 - 7%) • Peak dQ/dx ~ 16 & 25 fC/um
High Energy Neutrons • Complex reactions • Typical dQ/dx > 100 fC/um! • Effect increases with altitude
• Effect localized
• Cannot easily be shielded
• Effect dominant in parts using BPSG
Robert Baumann
Slide 30
Radiation Effects on Devices
Robert Baumann
Slide 31
Junction Charge Collection Ion Track
+V
n+ diffusion
Vss p- epi
Potential Contour Deformation
Drift Collection
Diffusion Collection
Electron-Hole Pairs
Recombination p+ substrate Robert Baumann
Slide 32
Charge Track & Collection Charge Generation (t = 0 - 1 psec) • Ion travels through or near (2 um) junction(50 fsec 5 MeV Si recoil) • Radiation event ionizes device silicon along trajectory • Track radius is ~ 0.2 µm and charge density is ~ 1019-1021 /cm-3
Prompt/Funneling Collection (t = 10 - 500 psec) • Track expands radially by ambipolar diffusion (quasineutral) • Potential warped into “funnel” shape around the track • Holes & electrons are separated by electric field • Electrons are collected by the sensitive node (reverse biased n+) • Field distortion (funnel) relaxes rapidly to its original state
Diffusion Collection (t >> nsec) • Excess electrons/holes deeper within the substrate diffuse away. • Some diffusing electrons are captured by the sensitive node. Robert Baumann
Slide 33
What is an SEU (SBU and MBU) Single Bit Upset Transient induces change in the voltage of a storage node (injects a current) that is sufficient to defeat the circuit feedback holding the data state such that the data state is reversed.
Multiple Bit Upset Same mechanism as SBU except the radiation event has higher charge density and/or a larger range such that multiple bits are upset by the single event. Robert Baumann
Slide 34
SEU/MBU in DRAM Radiation event
Stored Charge
transfer gate (wordline)
SERBL(f)
transfer gate
“1” data state
Qcoll> Qcrit
“0” data state
storage cell Time bitline
Plate voltage
Qcrit = CnodeVnode
Robert Baumann
Slide 35
SRAM Cell in “storage” mode Vdd
BL
BL’ WL
WL’
“0”
“1”
Robert Baumann
Slide 36
Writing Data to an SRAM Cell Vdd
BL’=“0”
BL=“1” WL
WL’
“0”
“1”
Bitlines set to proper logic value Robert Baumann
Slide 37
Writing Data to an SRAM Cell Vdd
BL’=“0”
BL=“1” WL
WL’
0 1
1 0
Wordlines turned on Robert Baumann
Slide 38
SRAM Cell in “storage” mode Vdd
BL
BL’ WL
WL’
“1”
“0”
Robert Baumann
Slide 39
SRAM “SEU” Event Vdd
BL
BL’ WL
WL’
“1”
“0”
Radiation event passes near or through NMOS drain junction creating e-h pairs Robert Baumann
Slide 40
SRAM “SEU” Event Vdd BL
BL’
WL
WL’ eeee eeeeeee eeeeee eeeee
“0”
As electrons are collected the node is pulled down If PMOS cannot compensate before the switching time….
Robert Baumann
Slide 41
SRAM “SEU” Event Vdd BL
BL’
WL
WL’
1 0
0 1
SEU occurs! Qcrit ~ CnodeVnode + I restoreτ flip Robert Baumann
Slide 42
What is a SEFI? Event + critical register => System upset DRAM refresh controls, FLASH R/W controls, FPGAs
SEU in critical control data or code results in system failure
Robert Baumann
Slide 43
What is SET? Event + propagation + timing => SEU in register Transient
Transient propagation
Latch/FF
Output Effected?
Combinatorial Logic
Robert Baumann
Slide 44
Probability SET becomes SEU • Will it propagate? • Depends on LET – higher LET produces wider pulses with larger voltage disturbance • Propagation delay (tprop) limited • Pulses narrower than tprop will NOT propagate
• Will it be latched? • Depends on when the pulse arrives • Depends on the clock frequency • Depends on the pulse width
Robert Baumann
Slide 45
To catch an SET… Setup Time
Hold Time
Clock Non-Latching SET
Data
Earliest-Latching SET
Data Data
Window of Vulnerability
Latest-Latching SET
Non-Latching SET
Data After D.G. Mavis and P. H. Eaton, “Soft Error Rate Mitigation Techniques for Modern Microcircuits”, IEEE IRPS, April 2002, pp.. 216-225. Robert Baumann
Slide 46
Non-propagating SET This non-propagating SET is below the critical transient width to propagate freely for this technology, and would only result in SEU if a latch is within 2-3 gates of the struck inverter. After Dodd et al., 2004 IEEE NSREC Meeting (to be published in Dec. issue of IEEE Trans. Nucl. Sci.)
Robert Baumann
Slide 47
Freely Propagating Transients
P.E. Dodd, et al., “Production and Propagation of Single-Event Transients in High-Speed Digital Logic ICs,” IEEE NSREC, 2004 Slide 48 Robert Baumann
What is SELU? Event + parasitic bipolars => Latch-up condition
Diagram from from Gianluca Boselli, Texas Instruments Robert Baumann
Slide 49
SE Latch-up Primer • Loop gain of relevant pnpn must exceed unity (βpnpβnpn≥1) • A triggering stimulus must allow the loop to achieve the current level required to turn itself on. • Circuit must be able to supply the holding current and voltage required to sustain the loop. • SELU occurs in technologies that exhibit regular electrical latch-up.
Robert Baumann
Slide 50
Testing for Radiation Sensitivity
Robert Baumann
Slide 51
Typical Commercial Program Radiation Characterization
Device/Circuit Level
At speed testing Real application SRAM vs. Logic SET => SEU
SRAM Sensitivity Characterization Logic Sensitivity Characterization SET Characterization
Circuit/Chip Level
EVM Characterization Accurate Product SER
Accurate Product MTTF
n-induced Latch Up Characterization
Circuit/Chip Simulation
3D Device Simulation
Non-SRAM SER Algo. dependence SET => SEU
Qcrit Sim Upgrade
Customer Application Models
MTTFactual > MTTFSER Robert Baumann
Slide 52
Testing Philosophies Intense Monoenergetic Radiation Source
SEU/MBU/SELU rate under actual use conditions
Device cross-section
Convolutions & modeling Robert Baumann
Slide 53
Testing Philosophies Intense “White” Radiation Source
1 multiplication
SEU/MBU/SELU rate under actual use conditions
Robert Baumann
Slide 54
Testing Philosophies Cosmic background
Hundreds or thousands of units for hundreds or thousands of hours!!!
SEU/MBU/SELU rate under actual use conditions Robert Baumann
Slide 55
Test Variables • • • • • • • •
Voltage Iddq Temperature Data Pattern Cycle time/static/dynamic Beam incidence angle Geometry History (previous exposure or virgin)
Robert Baumann
Slide 56
Static ASER test flow setup DUT test param.
Error?
YES
NO store map
parametric test
NO
pass?
YES
write data
write data wait for T seconds read data error count
wait for T seconds
store data, calculations, bitmaps
Irradiate read data error count
Robert Baumann
display fail bitmap and error count Slide 57
Dynamic ASER test flow setup DUT test param.
Error?
YES
NO parametric test
store map error count, SER, calcs.
NO
pass? YES write data read data error count increment
n=N?
YES
write data Irradiate
read data error count increment YES n=N?
NO
NO Robert Baumann
store data, calculations, bitmaps
display fail bitmap and error count Slide 58
SELU test flow NO
increase in IDDQ? YES
Supports SELU event
write data write data w/o power reset
Irradiate read data error count increment
write errors? n=N?
∆Error too big?
NO
NO No SELU event
YES YES
Strong Evidence of SELU event
write data w power reset
write errors? Robert Baumann
Not SELU or sensitivity too low
NO YES
No SELU event
Slide 59
Los Alamos Neutron Beam Proton beam Neutron beams Tungsten spallation target
Fission Foil
DUT 30ºL 30ºR
15ºR
0º
Robert Baumann
15ºL
Slide 60
Los Alamos vs. “Reality” Neutrons/cm2-sec-MeV
1E-02 1E-03 1E-04 1E-05 WNR Beam / 1.38E08 Atmosphere
1E-06 1E-07 1
From atmospheric curve after JEDEC JESD89 and WNR curve from Steve Wender
10
100
1000
Neutron Energy (MeV) Robert Baumann
Slide 61
Neutron Beam Jig Neutron event detector (gas volume enclosed by uranium foil)
Neutron beam (3” diameter)
DUT cards
XYZ and rotation DUT Positioning stage
Custom DUT/laser holder
Robert Baumann
Slide 62
ASER Alpha Sources Americium 241 1.2
Source intensity = 10 µCi
1.0
1.0
0.8
0.8
Intensity
Intensity
1.2
Thorium 228/232(thick)
0.6
0.6
0.4
0.4
0.2
0.2
0.0
0.0 3.0
4.0
5.0 6.0 7.0 8.0 Alpha Energy (MeV)
Intensity A.F. =
9.0
Source intensity = 15 µCi
3.0
4.0
5.0 6.0 7.0 8.0 Alpha Energy (MeV)
0.1-100 µ Ci 0.1 - 0.001 α /cm 2 - hr
~ 10
9.0
8 -13
1 Curie = 1Ci = 3.7E10 disintegrations/sec. Robert Baumann
Slide 63
Wafer Level Alpha Testing mounting filter
alpha source (foil)
probe card
PROS: Directly ionizing Relatively “safe” sources No activation Directly quantifies alpha SER
probes
wafer
CONS: Requires simulation to account for large distance from wafer. Potential for contamination of
hot chuck
manufacturing tester. Robert Baumann
Slide 64
Package Alpha Testing ceramic package
alpha source (foil)
PROS: Directly ionizing Relatively “safe” sources No activation Directly quantifies alpha SER
CONS: Requires simulation to account for absorption in layers, source geometry, etc.
socket
Requires open faced-package (no FC) or backside approach
Robert Baumann
Slide 65
Accounting for Test Geometry
Robert Baumann
Slide 66
Ion/Laser Beam Testing Ceramic or etched plastic package
PROS: Laser or Ion beam
Directly ionizing Small spot size Highly localized Short pulse duration
CONS: Requires simulation to account for absorption, reaction cross-section, shadowing, etc.
socket
Accurate X-Y positioner (beam or DUT)
Requires open faced-package (no FC) or backside approach. Expensive fast switching laser and microscope optics for positioning
Robert Baumann
Slide 67
LET and Voltage Sensitivity 25
120
20
100 15
80
10
60 40
5
SER (a.u.)
dQ/dx (fC/um)
10
140
1
0.1 Alpha Particles Boron Fission Cosmic Neutrons
20
0
0 0
5
10
0.01 0.5
Particle Energy (MeV)
Robert Baumann
1.0
1.5
2.0
2.5
3.0
Voltage (V)
Slide 68
More Voltage Sensitivity
Robert Baumann
Slide 69
ASELU Test Results Vendor A: 1.5-V 0.16-µm 6T SRAMs Show Low SELU Rate (1-10 FIT/Mbit)
Vendor C: 3.3-V 0.25-µm 6T SRAMs SELU rate 1000 FIT/Mbit 1000
Latchup FIT Rate/Mbit
Latchup FIT Rate/Mbit
100
100 Vendor C 25oC 85oC 125oC
10
1 1.0
1.5
2.0
2.5
3.0
3.5
4.0
o
25 C o
125 C 10
1
0.1 1.0
Power Supply (V)
1.2
1.4
1.6
1.8
2.0
2.2
2.4
Power Supply (V)
* From Paul Dodd et al. IEEE 2003 IRPS, p. 51-55
HUGE SELU variation from vendor-to-vendor Robert Baumann
Slide 70
Non-SEU Fail-Rate (FIT/Mbit)
More SELU data 10
40C (24.1 Mbit SRAM) No fails seen at 0.9-1.3V. Limit of detection was 0.0044 FIT/Mbit
1 0.1 0.01
detection limit
0.001 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
Core Voltage (V) Robert Baumann
Slide 71
Field Test Verification Product: applications processor with 2Mbit embedded SRAM (C05): Ultra low alpha flip chip (~ 0.001 a/cm2-hr) Slow mode (10Mhz), 1.7V, 90 C: Algorithm: Memory test (every error detected): Sample Size: 600 identical chips: Test Time: 99 days or 600x99x24=> 1.42 Million device hours Altitude: 5300 feet (4.1x flux increase from sea-level): Errors observed = 4
Estimated Field SER was 2817 FIT or 1409 FIT/Mbit @ 5200ft Concrete shielding effect ~ 2.8x (8” of concrete @ attenuation of ~1.36x /10cm for n > 10 MeV) Net effect (altitude/shielding) ~ 4.1x/2.8x ~ 1.5x SER from alphas 113 FIT/Mbit (from SER Estimator) thus 1409 – 113 = 1296 FIT/Mbit for cosmic SER Extrapolating to sea-level and accounting for shielding 1296/1.5 = 864 FIT/Mbit @ sea-level So total SER at sea-level => 864 + 113 = 977 FIT/Mbit
Equivalent Sea-level Field SER ~ 977 FIT/Mbit ASER of TI C05 predicts 982 FIT/Mbit (@ 1.7V) Robert Baumann
Slide 72
Memory Utilization Effect Typical DSP
Typical CPU Scratch pad data
signal data
Critical program data
Robert Baumann
Slide 73
Data Sensitivity Effect MSB
LSB
Robert Baumann
Slide 74
Propagation Effect on SEU logic
L1 latch
latch L2
tprop Sensitive time Sensitive time
Safe time
tprop Safe time
Note: If a SEU in latch (L1) occurs too late in the cycle, due to propagation delay of the combinatorial logic path to the output latch, the data state error will be NOT be clocked into the output latch (L2). Clearly, as frequency is increased, the propagation time, which is fixed (for a give technology/design), becomes a larger percentage of the clock cycle, so SER decreases for increasing clock frequency Robert Baumann
from N. Seifert, et al., IEEE Trans. Nucl. Sci., 49(6), p. 3102, Dec. 2002. Slide 75
Logical Masking Error in masked logic does not get propagated to output and thus does not cause a system error.
Robert Baumann
Slide 76
Technology Scaling vs. Radiation Sensitivity
Robert Baumann
Slide 77
DRAM SER Scaling Trend 5.0 System SER
1
4.0 Vdd
0.1
3.0
bit SER
0.01
2.0
0.001 1
10
100
Voltage (V)
DRAM SER (a.u.)
10
1.0 1000
DRAM Generation (Mbits) Robert Baumann
Slide 78
SRAM Bit SER Trend Based on embedded high-performance SRAM
5
0.35µm
10
w BPSG
0.25µm
0.13µm
0.5µm
1
0.18µm 0.7µm
0.1 0.1
4
1
10
3
0.09 µm
Voltage (V)
SER (A.U.)
100
2
1 100
SRAM Integration Level (Mbits) Robert Baumann
Slide 79
6T SRAM SER – Physics Limited Soft Error FIT Rate/Mbit
10000
TI 6T Bulk CMOS (65nm – 250nm)
1000
100
10
Sandia 6T CMOS SOI (Non-radhard version)
4 vendors of 6T Bulk CMOS SRAM
FIT Rate in NYC 1 0.0
1.0
2.0
TI SRAM
3.0
4.0
5.0
6.0
Power Supply (V) * From Paul Dodd et al. IEEE 2003 IEDM, Robert Baumann
Slide 80
SRAM System SER Trend Based on embedded high-performance SRAM
5
1000
4
100 0.25µm
10 0.35µm
1
0.13µm
3
0.18µm
2
0.5µm 0.7µm
0.1 0.1
Voltage (V)
SER (A.U.)
0.09µm
1 1
10
100
SRAM Integration Level (Mbits) Robert Baumann
Slide 81
Logic SER Trend 10 0.25um
0.18um 0.13um 0.09um
0.06um
SER (A.U.)
1 SRAM bit SER (DC)
0.1
Flip-flop/Latch SER (DC)
Not derated for AC effects, logical masking.
Simulated FF/Latch SER
0.01 0.001
Presented as part of Hans Stork’s (TI CTO) plenary speech at, IEEE IRPS, 2004. Also appeared in EE Times article (early May 2004)
0.0001 SRAM bit SER (w ECC)
0.13um data based on logic test chip, and two DSP scan chains. 90nm data based only on logic test chip.
0.00001 1 10 100 SRAM Integration Level (Mbits) Robert Baumann
Slide 82
Critical Width for Propagation 500 Mhz
Technology fmax
1 Ghz 2.5 Ghz 5 Ghz
100 Ghz
Adapted from P.E. Dodd, et al., “Production and Propagation of SingleEvent Transients in High-Speed Digital Logic ICs,” IEEE NSREC, 2004 Robert Baumann
Slide 83
Observed MBU Rate Based on 3.48um2 cell results (0.18um)
100.00%
% of Total SER
MBU neutron data
10.00%
Exponential Fit
1.00%
MBU rate will increase with scaling since the number of bits subtended by an event will increase with increased bit density
Double hit Double hit
0.10%
triple hit
0.01% 0
1
2
3
4
5
6
7
Event Distance (um) Robert Baumann
Slide 84
Mitigating SEE
Robert Baumann
Slide 85
Shielding from Alphas B
C
15µm blocks all alphas
polyimide
B Collected Charge
A
A C
silicon substrate active device layer Robert Baumann
Polyimide Thickness Slide 86
Solder Bump Keep Away Zones Sensitive area
Keep away zone
Solder bumps
High SER
Low SER (area penalty) Robert Baumann
Slide 87
Solution to the 10B problem Metal 6 Metal 5 Metal 4 Metal 3 Metal 2 Metal 1 n+
n+
p Tank
p+
Replace the first few µm’s of BPSG from the process. Use 11B precursors for any Bbased diffusion/doping process. Use boron rich shielding materials in the product.
p+
n Tank
Silicon Substrate Robert Baumann
Slide 88
Stopping High Energy Neutrons
~ 1.5 meters of concrete is required to reduce neutron flux by 2x Robert Baumann
Slide 89
Improving SER by Process 2-3x improvement Cost of additional implant/thermal cycle
Cost of additional implant/thermal cycle increase parasitic C, BJT action
G D
G S
D
S
Deep tank/Buried implants
Multiple Well Technology
• Reduce prompt charge collection by
• Drain/well and source/well fields reduced thus charge collection is reduced.
reducing funnel. • Reduce collected charge by allowing more efficient substrate collection of diffusing carriers
• Charge collected by buried well and substrate can be removed. • Charge sharing by source/well depletion reduces charge collected by drain node.
Robert Baumann
Slide 90
Improving SER by Process - SOI General Advantages of SOI:
gate S
• Eliminates latch-up.
D
• Si volume reduction leads to large reduction in direct Qcoll compared to bulk. • No funneling can occur
body
oxide
• Parasitic BJT triggered by high VD or radiation
substrate
event. Source/body junction forward biased turning on BJT. SER sensitivity defined by bipolar gain, temperature, and bias. • Body contacts tie emitter and base can reduce or eliminate BJT effect.
Parasitic Bipolar
D
S
Partially Depleted (Si 1000-2000Å)
Fully Depleted (Si < 800Å) • Limits floating body and short-channel
body
effects. Less sensitive to distribution. No Parasitic BJT. Robert Baumann
dopant
Slide 91
SOI vs. Bulk Neutrons
Normalized neutron SER/Mb
100
Alpha Particles
Bulk ST 130nm Bulk MOT 130nm Bulk MOT 90nm SOI MOT 130nm SOI MOT 90nm
Bulk devices
Bulk ST 130nm Bulk MOT 130nm SOI MOT 130nm
Bulk 130nm
10
SOI devices
1
0.8
1.0
5x
5x
1.2
1.4
SOI 130nm
1.6
1.8
1.0
1.2
1.4
1,6
Supply voltage (V)
Supply Voltage (V)
From Philippe Roche, ST Micro Robert Baumann
Slide 92
Boosting Capacitance from P. Roche, et al., IEEE IRPS, p.671, April 2004
150x SEU reduction - ST Micro (EDRAM - 10% wafer cost adder) 10x SEU reduction - Samsung (increased parasitics) 9x SEU reduction – Cypress (small MIM cap.) 100x reduction (private comm.) – Hitachi (EDRAM-like) Robert Baumann
Slide 93
Mitigating SELU • Ensure good electrical LU performance. • Use adequate number of taps. • Lower voltage technologies reduce probability of LU especially below 1V. • The Beta of lateral and vertical bipolars seems to be getting lower (good). • Use of SOI eliminates SELU. • Use of back-side ion implantation can further reduce beta.
Robert Baumann
Slide 94
Floating Gate Technology Program/Read Gate
Floating gate
Immune to soft errors in storage mode. SER will be defined by external CMOS sensitivity and how often the FLASH memory is accessed. In rare cases high LET particles can damage tunnel oxide causing leakage degradation and in some cases breakdown the tunnel oxide. In the terrestrial environment this failure mode is exceedingly rare – really only a concern in high dose environments or long space missions.
FLASH cell Robert Baumann
Slide 95
FRAM Technology • • • •
Spontaneous polarization arises from displacement of Zr4+/Ti4+ ions to O2Polarization is reversible by an external electric field FRAM very robust against SEU in retention mode CMOS circuitry has SEU sensitivity
Zr4+ / Ti4+
Pb2+
O2-
J. Rodriguez et al., “Reliability properties of low voltage PZT ferroelectric capacitors and arrays,” IEEE IRPS, pp. 200 – 208, April 2004. Robert Baumann
Slide 96
Parity Bit Data State “0” Single error
00
Double error
Single error
01
11
Single error
Error
Error
10 Robert Baumann
Data State “1”
A single error CANNOT transform data state “0 into “1”, instead an error vector is created. But since either state can generate either error vector, the original data state can not be restored Slide 97
Error Detection and Correction Unique (correctable) error vectors Data State “0”
0000 Single error
Double error
1 0 0 0
1 1 1 0
0 1 0 0
1 1 0 1
0 0 1 0
1 0 1 1
0 0 0 1
0 1 1 1
Non-unique (but detectable) error vectors
0 1 0 1
Data State “1”
1111 Single error
Double error
0 1 0 1
Robert Baumann
Slide 98
Size of the Event vs. Scaling Technology 1
High energy neutron event 1 MBU => 4 single-bit errors all correctable
Technology 2
Same high energy neutron event 1 MBU => 5 errors with 3 correctable single-bit errors and a single uncorrectable double bit error
Robert Baumann
Slide 99
Latch/FF Hardening by Design Resistive hardened Cells Decoupling resistors are used to slow the regenerative feedback response of the cell so that pull-up/pull-down transistors have time to restore the node voltage before a flip occurs.
State Redundancy Hardened Cells HIT, DICE, etc. these designs use additional inverters/transistors to ensure that logic states are defined by more than a single pull-down/pull-up path. With these types of approaches, the number of transistors is doubled but standby power and switching speed are not impacted while SEU resistance is greatly increased since single events on a single node cannot upset the cell.
Robert Baumann
Slide 100
Resistive Hardening Vdd WL
WL
BL
L.R. Rockett, Nucl. Sci., 35(6), 1988 suggested using gated resistors that can shunt the resistance during write operations
WL
WL
BL BL
BL
P1
R1
P2
P1
P2
N1
R2
N2
N1
N2
Qcrit = CnodeVnode + I restoreτ flip R1 and R2 lengthen the cell response time τflip and thus Irestore has plenty of time to provide charge to restore struck nodes – the down side is that write time increases.
Poly 1
salicide Poly 2
Robert Baumann
Slide 101
State Redundancy Hardening
Standard latch
Hardened Latch (by Whittaker)
D. Bessot and R. Velazco, RADECS, pp. 564, Sept. 1993.
Hardened Latch (by Liu) Hardened Latch (by Rockett) Robert Baumann
Slide 102
SEU & SET Immune Latch IN
D Q
D Q
D Q
LAT
LAT
LAT
Clk A D Q
D Q
D Q
LAT
LAT
LAT
D Q
D Q
D Q
LAT
LAT
LAT
MAJ VOTER
OUT
Clk B
Clk C
Synchronous Voting
Clk D Temporal Sampling After D.G. Mavis and P. H. Eaton, “Soft Error Rate Mitigation Techniques for Modern Microcircuits”, IEEE IRPS, April 2002, pp.. 216-225. Slide 103 Robert Baumann
Processor redundancy schemes CPU 1
TMR CPU system
Lock-step CPU system CPU 1 Compare
CPU 2
CPU 2
Voter
CPU 3
Controller
Input/Output
Input/Output
Common clock, Cache shared or distributed Robert Baumann
Slide 104
Executive Summary •
SEEs are the dominant failure mode in advanced microelectronics.
•
3 radiation mechanisms are responsible in terrestrial applications.
•
Primary failure modes are SEU/MBU, SEFI, and depending on design SELU. SET will become a problem at high frequency.
•
Unlike hard mechanism a single failure criterion cannot be applied to SER since the impact is highly application dependent.
•
System impact of SEU on DRAMs is flat while for SRAMs it is increasing with increasing memory density. Flash/FRAM/etc. are nearly immune in retention mode but do have some sensitivity during access.
•
Best way to fix Memory SER is with parity/ECC and with appropriate column MUX to mitigate MBU.
•
In systems with protected memories the sequential and combinatorial logic elements limit the reliability of the system. Options for fixing logic is painful requiring spatial and/or temporal redundancy. Robert Baumann
Slide 105
Author Biography Robert Baumann received the B.A. (1984) with honors in physics from Bowdoin College and the Ph.D. (1990) in electrical engineering from Rice University, researching ferroelectric process development and integration for opto-electronic applications. He joined Texas Instruments in 1989 where he made significant contributions to the understanding of alpha and neutron effects including the discovery that activation of 10B in BPSG by low energy neutrons is a significant source of soft errors in advanced technologies. Most of the semiconductor industry has since followed suit, eliminating BPSG from advanced technologies. He is currently a Distinguished Member of the Technical Staff, focused on radiation effects in advanced SRAM and logic devices. Robert was one of the primary authors of the International JEDEC JESD-89 specification that has become the defacto industry standard for radiation effects testing of commercial electronics. Robert is co-chairing an SIA experts panel on radiation effects regarding the International Traffic in Arms Regulations (ITAR) and its potential for inadvertently capturing commercial technologies. Robert was recently elected to Fellow of the IEEE for “For contributions to the understanding of the reliability impact of terrestrial radiation mechanisms in commercial electronics.”
Robert Baumann
Slide 106
