Guest Editorial ICMTS'96 - Semiconductor ... - IEEE Xplore

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IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 10, NO. 2, MAY 1997

Guest Editorial ICMTS’96

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EST structures have been used to evaluate many aspects of semiconductor manufacturing, material properties, and device behavior since the first integrated circuit appeared. From this time a proliferation of measurement techniques, test structure designs, and data interpretation and analysis methods have evolved, with them becoming more important as the development of high-density and high performance VLSI continues. Many of these developments are now reported at the IEEE International Conference on Microelectronics Test Structures (ICMTS). This meeting focuses on test structures for material and process characterization, reliability and product failure analysis, wafer fabrication process control, device and circuit modeling, replicated features metrology, new sensors and devices as well as measurement methods and utilization strategies. This issue of the IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING (T-SM) contains a special section devoted to some recently reported progress in microelectronics test structures. The papers are based on presentations made at ICMTS, held in Trento, Italy, March 25–28, 1996. The Conference Chairman was Prof. Giovanni Soncini of the University of Trento and the Instituto per la Ricerca Scientifica e Tecnologica (IRST). Eighty-nine papers were submitted from 19 countries, and of these, 58 were selected for oral and poster presentation. This is the fourth special issue/section of this TRANSACTIONS that has been devoted to ICMTS, and this year eight papers have been selected for wider dissemination in the semiconductor manufacturing community. The papers in this issue cover a broad spectrum of test structure research including the development of new structures and

measurement procedures. Papers on test structure development include structures for measuring the Seebeck coefficient of polysilicon, overlay errors, and planarization. Methods are presented for evaluating the influence of die attachment on MOS transistor matching and the measurement of carrier-carrier scattering effect on hole and electron mobilities. Other papers detail a wafer-level method for monitoring plasma-charging, the fast detection of anomalous cells in flash memory, and the measurement of on-chip interlayer capacitances. The above provide a flavor of the types of papers presented at ICMTS, and for those with further interest in microelectronic test structures there are many more interesting papers in the conference proceedings. We would both like to thank all the authors for their efforts in preparing extended manuscripts of their conference presentations and their admirable job in responding to the criticism of the reviewers. We would also like to thank the reviewers for the time they have devoted in reviewing the submitted manuscripts and for their valuable comments. Last but not least, we would like to thank the editor, Dr. Gary Cheek, and his assistant, Angela Grasso, for their assistance and excellent guidance through the IEEE T-SM review procedure.

Publisher Item Identifier S 0894-6507(97)03325-3.

KJELL O. JEPPSON, Guest Editor Chalmers University of Technology G¨oteborg, Sweden ANTHONY J. WALTON, Guest Editor University of Edinburgh Edinburgh, U.K.

Kjell O. Jeppson (S’68–M’76–SM’83) received the Ph.D. degree in solid-state electronics from Chalmers University of Technology, G¨oteborg, Sweden, in 1977. He became a Senior Lecturer in the Department of Solid-State Electronics, Chalmers University of Technology, in 1978 and (Associate) Professor in the same department in 1996. He spent the academic year 1973–1974 with Rockwell International, Anaheim, CA, and the fall semester 1985 at the Southampton University Microelectronics Centre, Southampton, U.K. His main research interest is focused on MOS device modeling and parameter extraction and CMOS VLSI design. He has published several papers on NMOS nonvolatile memories, MOS transistor modeling and parameter extraction, CMOS gate delay, and hierarchical DRC of VLSI circuits. He has also authored a textbook (in Swedish) on semiconductor devices. Since 1993 he is also Vice Dean, responsible for the undergraduate School of Electrical Engineering for which he has initiated the E-96 project for implementation of a new undergraduate curriculum.

0894–6507/97$10.00  1997 IEEE

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 10, NO. 2, MAY 1997

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Anthony J. Walton (M’88) received the B.Sc. degree in electrical and electronic engineering from the University of Newcastle-upon-Tyne, Newcastle-upon-Tyne, U.K., in 1974. In 1976, he received the M.Sc. degree by research into thin lumped elements at microwave frequencies. From 1977 to 1979, he worked toward the Ph.D. degree as a Research Assistant at Manchester Polytechnic, U.K. After receiving the Ph.D. degree, he joined the Department of Electronic and Electrical Engineering, University of Technology, Loughborough, U.K., as a Research Fellow working on hybrid active filters. In 1981, he moved to the Edinburgh Microfabrication Facility in the Department of Electrical Engineering, University of Edinburgh. There he worked as a Research Assistant where he addressed process control and measurement problems associated with integrated circuit fabrication. He is currently a Reader in the Department of Electrical Engineering at the University of Edinburgh. He has been involved with the microelectronics industry in a number of areas which include silicon precessing, microelectronic test structures, design for manufacturing (DFM) and technology computer-aided design (TCAD). His present interests also include the optimization of semiconductor processes through the integration of the experimental design and TCAD simulation tools. He has published over 140 papers. Dr. Walton won the IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING best paper award in 1990.