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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 9, SEPTEMBER 2009
Guest Editorial Special Issue on Compact Interconnect Models for Gigascale Integration
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HIS SPECIAL Issue is devoted to research and development activities on emerging compact interconnection models for advanced circuit simulation using next-generation silicon technology and beyond. The continuous scaling of CMOS devices to the sub-90-nm regime has resulted in higher device density, faster circuit speed, and lower power dissipation. As VLSI technology shrinks below 90-nm geometries with Cu/low-k interconnections, parasitics due to interconnections are becoming a limiting factor in determining the circuit performance. Therefore, accurate modeling of interconnection parasitic resistance (R), capacitance (C), and inductance (L) is essential in determining various on-chip interconnect-related issues, such as delay, crosstalk, IR drop, and power dissipation. Accurate compact interconnection models are crucial for the design and optimization of advanced VLSI circuits for 65-nm CMOS technology and below. In addition, with the emergence of technologies such as carbon nanotubes (CNTs) and graphene nanoribbons (GNRs), compact interconnection models that are suitable for these technologies are crucial for advanced circuit design. Currently available interconnection models, which are based on field solvers, are inadequate for accurate and meaningful analysis of today’s chip with millions of devices. The demands for advanced interconnection models that can accurately simulate on-chip global interconnections and speedpower optimization for advanced interconnection technologies have led to enormous R&D efforts in the development of advanced and computationally efficient models. Therefore, the objective of this Special Issue is to bring together the diversity of R&D activities and advancement in compact interconnection models and their applications in circuit design, which are compatible with circuit simulation tools, for accurate full-chip analysis with back-end variations of advanced interconnection technologies of sub-90-nm nodes. This Special Issue includes a total of 10 rigorously reviewed papers with six invited and four regular papers. Unfortunately, due to the tight time frame, only these papers were accepted in time for the Special Issue. Other papers will appear later in regular issues of the IEEE TRANSACTIONS ON ELECTRON DEVICES. This Special Issue starts with four invited papers describing emerging interconnection technologies and models for nextgeneration semiconductor technologies. The first paper entitled “Compact Performance Models and Comparisons for Giga-Scale On-Chip Global Interconnect Technologies” is by Koo et al. The paper presents a comprehensive review of the
Digital Object Identifier 10.1109/TED.2009.2026838
interconnect models and performance of novel interconnect technologies and describes an accurate analytical model for the optimization of the “capacitively driven low-swing interconnect (CDLSI)” wire scheme. The second paper entitled “Carbon Nanomaterials for Next Generation Interconnects and Passives: Physics, Status, and Prospects” by Li et al. presents a comprehensive review of the current research status of the fabrication and modeling of CNTs and GNRs as the interconnections for future technology generations. The third paper entitled “Compact Physics-Based Circuit Models for Graphene Nanoribbon Interconnects” by Naeemi et al. presents physicsbased equivalent circuit models for armchair and zigzag GNRs, and benchmarks their conductances against those of CNTs and copper (Cu) wires. This paper highlights the requirement for patterning methods to produce relatively smooth edges for fabricating comparatively low resistance GNR interconnects than Cu wires. The fourth paper entitled “Inductance in OneDimensional Nanostructures” by Yamada et al. presents the origin and model for kinetic inductance in 1-D nanostructures with the estimation of nanowire inductance with multiple nodes and walls. The next two invited papers describe the importance of interconnect modeling in scaled semiconductor technologies. The first paper entitled “Interconnect Modeling: A Physical Design Perspective” by Kurokawa et al. presents the techniques of interconnect modeling and analysis in advanced system-on-chip design with a comprehensive review of design technologies related to interconnect effects, such as interconnect parasitic extraction, signal integrity analysis, and timing analysis. The second paper entitled “Performance Modeling of Low-K/Cu Interconnects for 32-nm Node and Beyond” by Tada et al. predicts the performances of low-k/Cu interconnections from the viewpoint of both RC delay and power consumption in scaling down to 15-nm node. The next four regular papers describe the modeling approaches for interconnect wires and vias, and the extraction of interconnect model parameters for advanced CMOS technologies. The first paper entitled “Field-Based Capacitance Modeling for Sub-65-nm On-Chip Interconnect” by Zhao et al. presents a new physical model for interconnection capacitance from in-depth analysis of the electric field distribution between multiple electrodes. The model can be used to analyze advanced CMOS interconnect structures such as copper diffusion layer and air gap in the dielectric. The second paper entitled “ClosedForm Expressions of 3-D Via Resistance, Inductance, and Capacitance” by Savidis et al. presents closed-form analytical equations for efficient modeling of the impedance, inductance,
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IEEE TRANSACTIONS ON ELECTRON DEVICES
and capacitance of 3-D vias with excellent agreement with fullwave electromagnetic solutions. The third paper entitled “The Impact of On-Chip Interconnections on CMOS RF Integrated Circuits” by El-Desouki et al. demonstrates the impact of interconnection metal layer resistivity and layout parasitic on the on-chip performance of RF circuits. In particular, the impact of accurate modeling of metal layer resistivity and layout parasitics is crucial in the design of an RF power amplifier and a low-noise amplifier and in obtaining agreement between experiments and simulations. A methodology for improving circuit layout by careful consideration of the interconnection parasitics is, also, discussed. The fourth paper entitled “A Nondestructive Method of Extracting the Width and Thickness of Interconnects for a 40-nm Technology” by Tang et al. presents a nondestructive approach for extracting the metal width, thickness, and resistance, and interlayer dielectric thickness from the measured resistance and capacitance data of the interconnection wires for an accurate and efficient interconnect modeling. The three editors would like to sincerely thank the reviewers who carefully and meticulously reviewed each manuscript and the revised versions in a very timely manner. We would also like to thank the authors for their cooperation in submitting
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revised manuscripts in a shorter-than-normal time frame and in documenting important research results on compact interconnect modeling, so that they are available to the wider research and user communities. We would also like to thank and greatly appreciate the supporting work by J. Marsh of the EDS publications office. Finally, we have enjoyed putting together this Special Issue. We hope that the readers will also enjoy it.
SAMAR K. SAHA, Guest Editor Silterra USA, Inc. San Jose, CA 95110 USA
[email protected] M. JAMAL DEEN, Guest Editor McMaster University Hamilton, ON L8S 4K1, Canada
[email protected] HIROO MASUDA, Guest Editor Renesas Technology Tokyo 187-8588, Japan
[email protected]
Samar K. Saha (SM’99) received the M.S. degree in engineering management from Stanford University, Stanford, CA, and the M.Sc. and Ph.D. degrees in solid-state physics from Gauhati University, Guwahati, India. He was an Assistant Professor with the Department of Electrical Engineering, Southern Illinois University, Carbondale, IL, and Auburn University, Auburn, AL. Since 1984, he has held various positions at the National Semiconductor Corporation, LSI Logic Corporation, Texas Instruments, Philips Semiconductors, Silicon Storage Technology, Synopsys, and DSM Solutions. He is currently the Director of Design Technology with Silterra USA, Inc., San Jose, CA, and an Adjunct Professor with the Department of Electrical Engineering, Santa Clara University, Santa Clara, CA. He has authored more than 70 research papers. He is the holder of six U.S. patents. He has offered numerous tutorials/short courses on compact modeling and technology computer-aided design (TCAD). His research interests include nanoscale device and process architecture, TCAD, compact modeling, and TCAD and R&D management. Dr. Saha is the Vice President of the Electron Devices Society (EDS) Publications, an elected member of the EDS Administrative Committee, the Editor-In-Chief of QuestEDS, and a Distinguished Lecturer of EDS. He has served as the Principal Guest Editor for the IEEE TRANSACTIONS ON ELECTRON DEVICES Special Issue on “Advanced Compact Models and 45-nm Modeling Challenges,” Region-5&6 Editor of the EDS Newsletter, EDS representative to the Editorial Steering Committee of the IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, Chair of the IEEE EDS Compact Modeling Technical Committee, Chair of the EDS SRC-NAW, Member of the EDS Publications Committee, EDS representative to the Council of Electronic Design Automation, and Chair of the IEEE EDS Santa Clara Valley Chapter. He is listed in the Who’s Who in America and Who’s Who in the World.
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M. Jamal Deen (F’02) was born in Georgetown, Guyana. He received the Ph.D. degree in electrical engineering and applied physics from Case Western Reserve University, Cleveland, OH, in 1985. His Ph.D. dissertation was on the design and modeling of a new CARS spectrometer for dynamic temperature measurements and combustion optimization in rocket and jet engines, and was sponsored by the National Aeronautics and Space Administration, Cleveland. He is currently a Professor of electrical and computer engineering with McMaster University, Hamilton, ON, Canada, and is the holder of the Senior Canada Research Chair in Information Technology. He was a Fulbright Scholar (under the Latin American scholarship program) from 1980 to 1982, an American Vacuum Society Scholar from 1983 to 1984, and a Natural Sciences and Engineering Research Council of Canada Senior Industrial Fellow in 1993. He is an Executive Editor for Fluctuations and Noise Letters and a Member of the Editorial Board of the Journal of Nanoscience and Nanotechnology, the Microelectronics Journal, and the International Journal of High Speed Electronics and Systems. He has published more than 400 peer-reviewed papers (about 80 are invited) and 14 invited book chapters. He is the holder of six awarded patents. His research interests are microelectronics/nanoelectronics, optoelectronics, nanotechnology, and their emerging applications. Dr. Deen has been elected Fellow of three national academies and four professional societies, including The Royal Society of Canada: The Academies of Arts, Humanities and Sciences of Canada; The Canadian Academy of Engineering (FCAE); The American Physical Society (FAPS); and The Electrochemical Society (FECS). He is an Honorary Member of the World Innovation Foundation (which is the foundation’s highest honor). He is currently an Editor for the IEEE TRANSACTIONS ON ELECTRON DEVICES. Hiroo Masuda (M’71) received the B.S. degree in applied physics and the Dr.Eng. degree in electric system from Tokyo Institute of Technology, Tokyo, Japan, in 1970 and 1979, respectively. In 1970, he joined the Central Research Laboratory, Hitachi, Ltd., Tokyo. He was initially engaged in research on a 3-µm metal–oxide–semiconductor (MOS) device and process and dynamic memory. From 1982 to 1999, he worked on semiconductor device simulation and modeling. From 2000 to 2005, he was with STARC, where he was engaged in research and development works on physical design issues for sub-100-nm very large scale integration (LSI). Since 2006, he has been with Renesas Technology, Tokyo, working on the variability design of complementary-MOS LSI. Dr. Masuda is a Member of the Institute of Electronics, Information and Communication Engineers of Japan.
