We observe that architectural changes such as transactional memory and technology and cir- cuits to enable magnetic storage over charge-based storage are.
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Guest Editorial Special Section on Optical Interconnects Rasit O. Topaloglu, Senior Member, IEEE
Increasing delay of interconnects over devices at advanced nodes indicates a need for drastic change for interconnect. Such drastic changes have traditionally been possible through material changes. However, an alternative change in design may be near. In particular, on-chip optical interconnections are on the verge of being introduced to be able to cope with system-scale performance roadmaps. Thereby, photon-based information transfer may take the place of charge-based transfer that has been utilized within and across semiconductor chips for decades. Such a change would trigger significant updates to the design flows and circuitry. Semiconductors are no stranger to photons. Information transfer already utilizes optical interconnections, albeit at long distances, such as rack to rack or data center to data center. In addition to long-range data communication and transfer, photonics is also utilized for data or energy conversion across optical and electrical circuit mediums. However, in such cases, the sending and receiving circuitry is not a general-purpose processor. Improvements in data storage and transfer are two major areas that a high-performance computing system needs in order to keep up with increasing switching speeds and computing node number. Innovation in each requires technology, circuit, and architectural improvements and breakthroughs. Data storage has already been fighting at several fronts for the next generation memory system. We observe that architectural changes such as transactional memory and technology and circuits to enable magnetic storage over charge-based storage are being considered and implemented. On the data transfer side, improvements have been sufficient to incorporate over 10 cores on a single chip. Architectural,
circuit, and technology innovation in this area has been confined to charge-based transfer ones including the shift from aluminum to copper interconnects, improvements in low-k materials, reliability engineering to reduce electromigration, and incorporation of novel clocking mechanisms such as resonant clocking. Inside a processor, system, memory, I/O, or networking buses could utilize optical interconnects in the future. Bandwidth needs to double for each of these components going forward per each computer system generation while reducing energy per bit toward 1 pJ and controlling per bit cost increase. On-chip optical interconnect prototypes have already been shown to be available using standard silicon-based semiconductor processing. Yet modeling, design, analysis, prediction, optimization, and CAD tool aspects require practical solutions. Further in need is system-level planning and optimization to decide on how close to bring the optical transfer to switching and storage elements in a high-performance computing system and how exactly to architect them. This issue of IEEE T RANSACTIONS ON C OMPUTER A IDED D ESIGN OF I NTEGRATED C IRCUITS AND S YSTEMS contains a section on optical interconnects. The corresponding papers cover topics in routing automation and architectural design and optimization. We hope this special section provides insights for these topics and triggers follow-up publications to speed up the transfer into the light-enabled data transfer period. R ASIT O. T OPALOGLU, Guest Editor IBM Hopewell Junction, NY, USA
Rasit O. Topaloglu (M’05–SM’13) received the B.S. degree in electrical and electronic engineering from Bogazici University, Istanbul, Turkey, and the M.S. and Ph.D. degrees in computer science and engineering from the University of California, San Diego, San Diego, CA, USA. He was with AMD, Sunnyvale, CA, USA, from 2005 to 2009, GlobalFoundries, Santa Clara, CA, USA, from 2009 to 2011, and IBM, Hopewell Junction, NY, USA, since 2011. He has received five issued and five pending patents and close to 50 international publications. Dr. Topaloglu was the recipient of the Best Paper Award at ISQED. He serves as a Technical Advisory Board Member at the Semiconductor Research Corporation for IBM. He has also served on the Technical Program Committees of DAC, DFM&Y, DATE, ICCAD, ISPD, ISQED, SLIP, and VLSI-SOC. He is the International Chapter Coordinator for IEEE C-EDA. He is currently serving as Chair of the ACM/IEEE SLIP, and Co-Chair of the DAC Workshop on Alternative Computing in the Nano-scale Era and the Variability Modeling and Characterization Workshop in 2014.
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