Hardware-Software Interfaces - Columbia University
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Hardware-Software Interfaces - Columbia University
Memory-Mapped I/O To a processor, everything is memory. Peripherals appear as magical memory locations. Status registers: when read, report state of peripheral Control registers: when written, change state of peripheral
Hardware-Software Interfaces – p. 1
Typical Peripheral: PC Parallel Port
Hardware-Software Interfaces – p. 1
Parallel Port Registers D7
D6
D5
D4
D3
Busy
Ack
Paper
Sel
Err Sel
D2
D1
D0
0x378 0x379
Init
Auto
Strobe
0x37A
1. Write Data 2. Assert Strobe 3. Wait for Busy to clear 4. Wait for Acknowledge
Hardware-Software Interfaces – p. 1
A Parallel Port Driver #define DATA 0x378 #define STATUS 0x379 #define CONTROL 0x37A #define #define #define #define #define #define
NBSY 0x80 NACK 0x40 OUT 0x20 SEL 0x10 NERR 0x08 STROBE 0x01
#define INVERT (NBSY | NACK | SEL | NERR) #define MASK (NBSY | NACK | OUT | SEL | NERR) #define NOT_READY(x) ((inb(x)ˆINVERT)&MASK)
void write_single_character(char c) { while (NOT_READY(STATUS)) ; outb(DATA, c); outb(CONTROL, control | STROBE); /* Assert STROBE */ Hardware-Software Interfaces – p. 1 outb(CONTROL, control ); /* Clear STROBE */ }
The Parallel Port Schematic Address decoding
Data latch
Data read
Bus driver Control latch
Control read
Hardware-Software Interfaces – p. 1
Interrupts and Polling Two ways to get data from a peripheral: Polling: “Are we there yet?” Interrupts: Ringing Telephone
Hardware-Software Interfaces – p. 1
Interrupts Basic idea: 1. Peripheral asserts a processor’s interrupt input 2. Processor temporarily transfers control to interrupt service routine 3. ISR gathers data from peripheral and acknowledges interrupt 4. ISR returns control to previously-executing program
Hardware-Software Interfaces – p. 1
Many Different Interrupts Peripheral
Processor
Int ?
Peripheral
Peripheral
What’s a processor to do?
Hardware-Software Interfaces – p. 1
Interrupt Polling Peripheral
Processor
Int
Peripheral
Peripheral
Processor receives interrupt ISR polls all potential interrupt sources
Hardware-Software Interfaces – p. 1
Intel 8259 PIC clk
Din[7:0] Dout[7:0] DataValid
Read Write CS A0 Reset
CAS
INTA
Int
Control Logic Data Bus Buffer
Read / Write Logic
Cascade
In Service Register (ISR)
Priority Resolver
Interrupt Request Register I( RR)
Interrupt Mask Register (IMR)
Prioritizes incoming requests & notifies processor ISR reads 8-bit interrupt vector number of winner IBM PC/AT: two 8259s; became standard
