Invited Paper
Heterogeneous 3D Integration of Multi-spectral Photonic Sensor with Highly Oriented Micro/Nano-pillars of Semiconductors Logeeswaran VJ, Jacob Goodwin, Aaron M. Katzenmeyer and M. Saif Islam1 Integrated Nanodevices and Nanosystems Lab, Department of Electrical and Computer Engineering, University of California, Davis, CA 95616-5294 ABSTRACT We developed a novel method for three-dimensional heterogeneous integration of devices based on any semiconductor material on a pliant surface with arbitrary surface profile. Arrays of optical detectors in the form of vertically oriented micro/nano-pillars with diverse bandgaps and physical properties are fabricated via synthetic bottom-up or transformative top-down approaches on a single crystal surface and then transferred to a different target surface using a polymer assisted shear-fracturing process. The original wafers are used repeatedly for generating more devices and are never consumed. Ohmic contacts with low contact resistance are formed for individual electrical addressing of each layer of sensors using metals and/or conducting polymer such as PAni and PEDOT:PSS. The method offers an opportunity for device fabrication with low fill factor contributing to lower dark current, reduced parasitic capacitance and higher efficiency of light absorption. Keywords: heterogeneous integration, micro/nano-pillars, multi-spectral imaging, 3D material integration, detector arrays, photon traps, polymer-semiconductor contacts
1. INTRODUCTION Recently semiconductor device community has considerably focused on heterogenous integration of multiple thin films and nanomaterials for device applications including integrated optoelectronics, on/off-chip communications, photovoltaics [1-4] and sensors with ultra-wide spectral responses for imaging and sensing [5-7]. Heteroepitaxy offers some high performance devices but introduces issues such as high substrate cost, lack of flexibility of substrate, interface defects, vacancies and traps caused by material mismatch. In addition, CMOS incompatibility due to extreme physical growth conditions such as high growth temperature, dissimilar device processing schemes (such as difference in doping and contact materials) contribute to our inability to develop mass manufacturable techniques to grow and integrate a variety of materials and devices on a host of surfaces. Ideally monolithically integrated multiple semiconductors with diverse bandgap, electrical and optical properties could offer the ultimate solution to the grand challenge of multifunctional material integrations for CMOS compatible electronics and photonics with superior performance and wide spectral range. Additionally, the capability of integrating a stack of multifunctional semiconductor material on any type of substrate and with arbitrary topology will offer an enormous cost-effective economic opportunity for applications such as multi-spectral imaging, sensing, energy conversion, and photovoltaics. In principle, the challenges in integrating multifunctional materials can be circumvented by fabricating high quality single crystal and vertically oriented one-dimensional (1-D) micro or nanoscale wires/pillars of virtually any material and then harvesting them, while preserving the array morphology to coat a target substrate/surface. Highly crystalline nanowires fabricated via ‘bottom-up’ fabrication method and micro/nano-pillars fabricated via transformative ‘topdown’ method with diverse bandgaps and physical properties can then be fabricated on appropriate mother substrates and transferred to form multilayered three-dimensional (3-D) stacks for multifunctional devices. This approach not only ensures the incorporation of numerous materials (with the best device characteristics) on a single substrate facilitating substrate-free device fabrications on any topology, but also allows the repeated use of a mother substrate for continual production of new devices. An added advantage is the elimination of the need for expensive individual substrate materials for devices and circuits. This capability will offer a universal platform for material integration and enable a 1
Email:
[email protected], Phone: (530) 754-6732, www.ece.ucdavis.edu/inano/ Micro- and Nanotechnology Sensors, Systems, and Applications, edited by Thomas George, M. Saif Islam, Achyut K. Dutta, Proc. of SPIE Vol. 7318, 731805 · © 2009 SPIE · CCC code: 0277-786X/09/$18 · doi: 10.1117/12.821791
Proc. of SPIE Vol. 7318 731805-1
large number of end users to take advantages of economics-of-scale for inexpensive manufacturing of electronics and photonics, and to leverage development costs to create the technology infrastructure to make such systems powerful, inexpensive, and deployable in large numbers. Here we report an experimental method to harvest and transfer vertically aligned single crystal semiconductor micro- and nanoscale pillars (MNP’s) from a template (mother) substrate to a receiving low cost carrier substrate while simultaneously preserving the integrity and fidelity of the transferred arrays. We developed a transfer technique based on a vertical embossing and lateral fracturing method employing a transfer polymer. We also demonstrated Ohmic contact formation for electrical addressing using a composite of metals and conducting polymer. The capability of this process is demonstrated by fabricating Si photoconducting devices with a low fill factor contributing to lower leakage current, reduced parasitic capacitance and higher efficiency of light absorption. In the subsequent sections, it is well-identifiable that our approach offers a more generic method in that the ordered array of the 3D micro/nanostructures are preserved in their vertical orientation (direct 3D-to-3D) after transfer while increasing the volume density of the final device. We are not restricted by any starting mother substrates or carrier substrates (such as SOI as was required by others) and involve ambient and/or low temperature processes (
