HIERARCHICAL MODELING OF SIGMA DELTA

HIERARCHICAL MODELING OF SIGMA DELTA MODULATORS FOR NOISE COUPLING ANALYSIS Bingxin Li, Li-Rong Zheng and Hannu Tenhunen Electronic System Design Laboratory, Royal Institute of Technology Electrum 229, Isafjordsgatan 22 164 40 Kista, Sweden lbingxin, lrzheng, [email protected]

ABSTRACT In this paper a hierarchical modeling strategy of sigma delta modulator for mixed signal coupling analysis is presented. In this hierarchical model only the key components which are important to noise or disturbance analysis are implemented on transistor level, the other parts are realized in behavioral model which is written in Analog HDL. The simulation speed can be improved by an order of magnitude. With this method, fast and reasonably accurate estimation for coupled noise in mixed-signal IC design can be achieved. A 5th order sigma delta modulator is used as a demonstration to show the intrinsic noise analysis and the substrate coupling noise analysis. I. INTRODUCTION The technological improvement in digital VLSI circuits has increased the need for low cost high performance A/D and D/A converters, where a considerable amount of analog circuitry is integrated with digital circuitry. Unfortunately, marrying sensitive analog circuitry and digital circuitry on a single chip has been a difficult task due to the noise coupling problems. The most important noise mechanisms which influence such circuit performance include (i) near field capacitive coupling between neighbor circuits through interconnects; (ii) coupling between widely separated circuits through the chip substrate and power rails; and (iii) other noise sources, such as thermal noise, produced intrinsically by transistors and other circuit elements. In many mixed-signal IC implementations the first two dominate. However, systematic techniques to compare different architectures, circuit topologies, or layout floorplans for noise coupling robustness are not available. Experimental progress has been made in dealing with mixed-signal noise coupling problems [e.g. 1-3]. However, there are circuit classes which are extremely difficult to simulate with standard SPICE [4] based techniques. Typical examples of such circuits are sigma-delta modulators,

mixers, and VCOs [5-6]. A hierarchical modeling approach [6] using Analog HDL is thereby proposed and adopted in this work. By definition AHDL is a programming language that is specifically designed to allow the description (or modeling) of hardware that performs a continuous value and continuous time function [7]. An essential property of AHDL is that the models written in AHDL can be mixed with normal SPICE model, thus providing so-called hierarchical modeling method. In this paper, we present a hierarchical modeling approach for noise coupling analysis of sigma-delta modulators using AHDL. With this approach, we find that the simulation time is greatly shortened while the simulation accuracy is still guaranteed. This modeling technique enables us to study complex circuit robustness to different noise sources. II. HIERARCHICAL MODELING OF Σ-∆ MODULATORS Σ-∆ modulator is the key component of oversampling A/D convertors. With noise shaping structure, the quantization noise is largely moved out from signal band [8]. Thus very high Signal-to-Noise ratio can be achieved (e.g. >100dB). As Σ−∆ modulator is a high-resolution circuit, it is important to analyze the influence of different kinds of noise sources. Using SPICE directly to do this kind of simulation is too time-consuming because the performance of Σ-∆ Modulator is evaluated by output signal power spectrum. To get reasonably accurate result, a large number of sample points have to be calculated (usually more than 10K). This can require days or even weeks of simulation time on the latest workstation. With AHDL, a simple behavioral model for the whole modulator can be created. Then according to the specific noise analysis, those components that are most sensitive can be implemented with transistor netlist including back annotated layout parasitics. The simulation time is significantly shortened while the simulation accuracy is still guaranteed because we have accurate models for the sensitive components. So dif-

N1

N2

N3

X H1

H2

H3 a3 a2 a1

Y

DAC Fig. 1.

3rd order Σ-∆ modulator model

ferent modulator topology and submodules can be compared in a short simulation time with respect to noise sensitivity. This is particularly useful in Σ−∆ noise shaper modeling, where due to strong feedback, non-linear comparator operation and noise shaping functionality, different noise sources are not directly additive and the overall effect at the baseband depends heavily on system topology and parameters. In a high order Σ−∆ modulator the first stage is of most importance to noise analysis. The reason is that the noises in the following stages (both intrinsic noise and coupling noise) are largely attenuated by the high DC and low frequency gain of the integrators. For example, in a 3rd order modulator whose structure is shown in Fig. 1, the transfer function for noise N1, N2 and N3 are: H1a1+H1H2a2+H1H2H3a3 Y = N1 1+H1a1+H1H2a2+H1H2H3a3 H2a2+H2H3a3 Y F(N2)= = N2 1+H1a1+H1H2a2+H1H2H3a3 H a Y F(N3)= = 1+H a +H H3 a3 +H H H a N3 1 1 1 2 2 1 2 3 3

Fig. 2.

Simulated SNDR (integrator DC gain=60dB)

Fig. 3.

Simulated SNDR (integrator DC gain=40dB)

F(N1)=

In signal band, H1, H2 and H3 have very high gains that are usually greater than 60dB. Assume that they have the same gain which is equal to G. With the same amplitude noise N1, N2 and N3, theoretically the influence of N1 will be G times larger than that of N2, and G2 times larger than that of N3. In practice this relationship is also affected by the modulator topology and device non-idealities, but it always has much bigger influence in the first stage than in the following stages. Simulations have been done to prove this. A 3rd order modulator was simulated with different amplitude noises added on each stage respectively. SNDR (signal to noise plus distortion ratio) was measured and plotted in Fig. 2 and Fig. 3. In Fig. 2 each stages has a DC gain of 60dB and the noise influence from the first stage is 40dB more than that from the second stages, and 55dB more than that from the third stage. In Fig. 3 each stage has a DC gain of 40dB and the noise influence from the first stage is 30dB more than that from the second stage, and

50dB more than that from the third stage. It is clear that with higher DC gain the noise influence in the following stages are smaller. Note that when the input noise power is very low the SNDR is limited by the quantization noise floor and remains almost unchanged. Based on the above analysis, in our hierarchical model the first stage is implemented in transistors netlist and the other parts are in behavioral model. To simulate a 3rd order Σ−∆ modulator with the same simulation resolution, the CPU time is about one tenth of that of a full transistor level simulation. This time reduction is even larger for higher order modulators because more stages are in behavioral model. For analysis purpose we have designed a 5th order single stage 1-bit Σ−∆ modulator as shown in Fig. 4. The loop coefficients are optimized for both performance and stability [8,9]. This noise shaper consists of multiple switched capacitor integrator stages, where the first stage

x(n)

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∆SNDR=3.7dB DAC

y(n)

Fig. 4.

5th order Σ-∆ modulator demonstration

VDD Bias 1

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Power spectrum of outputs with and without intrinsic noises

Fig. 6 compares the results with and without intrinsic noise sources. It should be mentioned that the SPICE numerical calculation error can be compatible with the high resolution of Σ−∆ modulator, therefor only the difference of SNRD is compared rather than their absolute values. In this example, the intrinsic noise power is roughly the same as quantization noise (in signal band), thus reducing the SNDR by about 3dB.

Bias 3

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Fig. 5.

Fig. 6.

IV. MIXED-SIGNAL COUPLING NOISE ANALYSIS

Folded-cascode Opamp in the integrator

is realized with fully differential OTA (Operational Transconductance Amplifier), as shown in Fig. 5. This kind of OTAs are good candidates for Σ−∆ modulator because of their large gain and slew rate [10]. III. INTRINSIC NOISE ANALYSIS Normal SPICE simulations do not consider the intrinsic noises (e.g. thermal noise and flick noise) inside the devices such as MOSFET and resistors. In many applications these noises are so small that it is safe to ignore them. However in high order Σ−∆ modulators these noises can be the limiting factor of overall resolution because the quantization noise in the signal band is already highly attenuated by the feedback loop. Some CAD tools (e.g. ELDO from Mentor Graphics) provide the function to add a noise source on each device and do simulation with these noise sources. Thus it is possible to simulate the hierarchical Σ−∆ modulator model with intrinsic noises and then compare it with the result where no noise is added. It is also possible to annotate back these noises to be an inputreferred macromodel, so fast simulation can be done later without the need to add a noise source on each device.

In a mixed signal design, noise coupled from digital side into analog side can be orders of magnitude worse than the thermal noise and flicker noise generated by analog circuits themselves unless carefully designed [3]. In addition, these noise sources or disturbances, do not have white spectral characteristics and can show strong temporal correlations. The path might be a direct capacitive or inductive coupling, or through the substrate. To reduce this noise (or the influence of the noise), many techniques can be used [3,11-12]. At circuit level, differential circuits can effectively reject most of the common mode noise. At layout level, one can arrange the power distribution or isolate the substrate of analog and digital parts in addition to using fully symmetrical floorplans. Till now there is still no comprehensive noise analysis tool available that can do efficient and accurate simulation of different kinds of coupling noises. Therefor it is practical to give simplified macromodels for both of the noise generation mechanism and the analog circuit itself to do fast evaluation at early stages of the circuit design process. One coupling noise analysis example with above hierarchical model is demonstrated here. In oversampling A/D converter, even if the substrate of digital part (decimation filter) and analog part (Σ−∆ modulator) are well isolated, the noise ejected by the clock line which goes through an-

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Fig. 7. Double-poly capacitor

+ M7 M8

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Sensitive devices in the first integrator clock NMOS OTA input-1

Substrate contact

NMOS OTA input-2

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P- epitaxial layer

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the highly doped bulk is modeled as a single node

Fig. 8.

Substrate coupling path macromodel

alog part (to clock the switch capacitor circuits) can still couple into analog circuit through the substrate. This is especially important when the clock frequency is high (e.g. about 100 meg Hz). With different layout floorplans of these clock lines the influences are also different. In this specific example the noise source is a clock line, and the selected sensitive devices are the integrator capacitors and input transistors of the amplifier as shown in Fig. 7. Fig. 8 shows the substrate coupling macromodels. The input transistors are sensitive because the noise coupled in these transistors will be amplified by the Opamp. The integrator capacitors are also sensitive because they have large areas and are connected to the Opamp outputs directly. The substrate has a heavily doped layer which is modeled as a common node. This heavily doped layer can be connected to the ground. This connection provides a low impedance path for the substrate coupling noise and will greatly reduce the noise impact on the analog circuit. For analysis

purpose this heavily doped layer is not connected to the ground in the following simulation. The parasitic capacitances and resistances connecting sensitive devices and noise source are extracted using Quasi-Static EM analysis method. Note that some resistance and capacitance are not shown in the figure for simplicity. When the clock switches, the voltage level shift will inject noise into the substrate. Through the coupling path generated by those parasitic resistance and capacitance, the noise will appear at the terminals of those sensitive nodes. How large this appeared coupling noise is depends on a lot of factors such as the clock switching voltage levels and edge slope, layout floorplan of noise source and sensitive devices, and the circuit connection of these sensitive devices. With different slope of the clock edge the injected noise will have different power spectrums, with shorter distance between noise source and sensitive nodes the coupled noise will be larger, and with different device connection the appeared

∆SNDR=11dB

ploration of the robustness of different sigma-delta modulator architecture and circuit topologies that requires extremely time-consuming simulations, even with less accurate models. This is especially important for wideband high resolution modulators [13]. The simulation time is normally within a few hours, which is 10~20 times faster than full transistor level simulation.

References

Fig. 9a.

Output power spectrum comparison (case 1)

∆SNDR=18dB

Fig. 9b.

Output power spectrum comparison (case 2)

coupling noise will also be different. These factors were changed to perform comparison simulations. The changed parameters include the clock edge slope, distance between transistor and the clock signal line, and the position of substrate contact. Fig. 9a and Fig. 9b show the results of two such comparison simulations. In case 1 the transistors are put 12um away from the signal line and the clock edge slope is 1ns. The SNDR is reduced by 11dB compared with the ideal case where no noise is added. In case 2 the transistors are closer to the noise source (2um) and the clock edge slope is set to 0.1ns. This reduces the SNDR by 18dB. Note that the capacitor coupled noises are not included in the above cases, which will lower the performance further. The simulations prove that the coupling noise can be the dominant noise source in Σ−∆ modulators unless carefully designed. V. CONCLUSIONS A hierarchical model of Σ−∆ modulator using Analog HDL and its application in noise analysis is presented. Macromodels for both intrinsic and coupling noises are also extracted. The approach facilitates the systematic ex-

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