High Aspect Ratio ThroughWafer Interconnect for ... - Semantic Scholar

High Aspect Ratio Through-Wafer Interconnect for Three Dimensional Integrated Circuits N.Ranganathan1, K. Prasad2, N.Balasubramanian1 , Zhou Qiaoer2 and Seah Chin Hwee1 1 Institute of Microelectronics, 11 Science Park Road, Singapore Science park II, Singapore 117685 2 Division of Microelectronics, School of Electrical & Electronic Engineering, Nanyang Technological University, Singapore 639798.

Abstract In this work, we examine deep silicon copper interconnect related failure mechanisms due to deep silicon via etching based on BOSCH process. Though it is the best candidate for performing deep and high aspect ratio silicon etching, its cyclical nature of doing series of etch and passivation process creates very rough sidewall thus impacting the electrical performance of through-wafer copper interconnection. In the present work we have designed a dedicated test vehicle to study and evaluate the deep silicon via etch induced defects such as sidewall scallops, conformality of dielectric isolation and copper diffusion barrier over the entire depth of the via. In addition, thermo-mechanical simulation has been done to identify the potential weak sites to help us to zoom into possible failures sites. Introduction Global interconnects are predicted to limit the performance of integrated circuits (ICs) in a few years time, even with damascene Cu/low-k technology [1]. Vertical or three dimensional circuit integration is one of the core approaches under investigation now that can significantly improve the interconnect performance [2]. Due to relentless device and interconnect width scaling. it is recognized that the on-chip and off-chip interconnections, rather than the transistor, are the limiting factors that affect the performance and economics of future electronic components, mainly due to sheer magnitude of the total interconnection lengths encountered in today’s ultra large scale integrated circuits (ULSI). This realization has led to increased research activities on three-dimensional (3-D) circuit integration architectures that rely on vertical interconnection by stacking chip to chip or wafer to wafer [3]. The development of 3-D integration technologies is mainly motivated by shorter chipto chip interconnection lengths, reduced parasitic wiring resistance and capacitance and hence higher signal speed and reduced power consumption, as compared to lateral chip placement and wiring approach. Further, due to small lead lengths offered by through-wafer interconnects, one can expect a dramatic decrease in power requirements, as well as a decrease in analog noise and cross-talk. The ability to form backside contact pads to ICs built on the front surface of the wafer opens new possibilities in circuit design. It allows system designer to partition complex systems into several wafers or chips and assemble them vertically by throughwafer interconnects. It also provides an effective option that can be used to interconnect devices vertically to form surface mountable devices [4]. In case of high frequency integrated circuits, vertical interconnects give the opportunity to bond an active device to a passive component layer, containing resistors, inductances, or power/ground planes. 0-7803-8906-9/05/$20.00 ©2005 IEEE

There exists a wide diversity of 3-D integration techniques in literature [5,6], but the most appealing and competitive schemes are those that can be implemented without disrupting the front-end processed device wafers. Typically, they involve aligning and stacking 2 or more functional wafers by lowtemperature wafer bonding technique. The devices in each substrate are interconnected by through-wafer interconnects. Here again there are several approaches to forming the via interconnections- one that involves copper to copper thermocompression bonding as shown in Fig-1 [7] while the other technique involves using low-k adhesives to bond wafers and then forming through-wafer via interconnection as shown in Fig-2 [8]. The concept can be extended to integrate several types of wafers vertically. Thinned silicon wafer Cu interconnect Device layers Device layers

Fig-1: Cu-Cu bonded wafer stack Glue layer for wafer bonding

Thinned silicon wafer

Cu interconnect Device layers Device layers

Fig-2: Adhesive bonded wafer stack Although different schemes vary significantly in their process flows, most wafer bonding schemes share some common requirements: (a) The bonding material ("glue") of choice, (b) a method for Si substrate thinning, (c) The waferto-wafer alignment scheme, and (d) the inter-layer electrical interconnection method. It is the objective of this paper to focus extensively on various aspects of deep silicon via etching process that is commonly used for forming the through-wafer vias for providing interconnections between

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both sides of wafers in a multi-wafer stack using wafer level packaging (WLP) or wafer bonding methods. While the 3-D integration approach has been demonstrated by many researchers, their reliability and manufacturability issues have not been extensively studied. The present work focuses on the impact of the etching process on the electrical performance of the through-wafer copper interconnections, especially due to the BOSCH process [9,10]. Experimental Details A. Test vehicle design A typical 3D interconnection structure is shown schematically in Figures 1 and 2. As it is our objective to study the effects of sidewall roughness created by the deep silicon via etch process on the electrical performance of the through-wafer copper interconnections, a test vehicle has been designed, as shown in Fig-3, to measure the current leakage between adjacent vias under various test conditions. The comb structure shown is formed by two metal masking steps: a trench metal mask and via metal mask. The detailed flow is given in Table-1. The via width was varied from 5 to 50 µm to study the effects of copper stress on the silicon dioxide dielectric and tantalum barrier. The test structure is built-up till it is ready for wafer thinning for face to face copper bonding to form a 3-D interconnected wafer stack. However, as it is our intent here to study the impact of silicon via etching process on the electrical performance, we have only fabricated the structure till the copper via-fill step. We also simulated thermal stress pattern on the actual through-wafer copper via and a partial copper via to ensure that there is no significant compromise in using the partial via instead of through-silicon via. In fact, the simulation studies have shown that our test structure is even more stringent. Dielectric layer

Via comb structures formed by damascene process Al Pad

Fig-3: Layout of test structure to evaluate the performance of through-wafer interconnection. Table-1: Process flow for test structure Step 1 2 3 4 5 6 7 8 9 10 11

Process description 3 µm plasma oxide deposition 1 µm damascene copper interconnection trench masking and etch process Deep silicon copper via masking and etch process 5 kǺ TEOS oxide liner deposition 250 Ǻ Tantalum/1.5 kǺ Cu seed sputtering Copper electroplating Copper alloying at 200C and CMP 1 kǺ Si3N4/3 kǺ SiO2 Passivation Pad window patterning and Aluminum deposition Aluminum Pad patterning Electrical measurements

B. Thermal stress modeling As product life cycles become shorter and product development costs increase, the need to develop products right the first time is critical. Modeling and simulation have become a critical step in developing new technologies. The initial step in developing a 3-D copper interconnection is to model the physical interaction between silicon, dielectric isolation, copper diffusion barrier and electro-deposited copper interconnect. Once the thermal stress model is created, simulations of the 3D structure are carried out to estimate the stress effects on the various films. Thermal stress characteristics of through-wafer damascene Cu lines passivated with tetraethyl orthosilicate (TEOS) oxide and protected by tantalum diffusion barrier were investigated by finite element analysis (FEA). Lines with different aspect ratios were studied, and the effect of line geometry was evaluated. The stress characteristics of Cu lines indicate that the insulation oxide and diffusion barrier play an important role in controlling the stress behavior in damascene structure. The effects of material properties, process conditions, and interconnect structure were carefully modeled and their implications in copper (Cu) interconnect performance are discussed. A potential failure mechanism in high density copper interconnect technology is via fatigue due to the coefficient of thermal expansion (CTE) mismatch between dielectric materials and the metallization in the via structure. This mismatch generates thermal stresses when the structure is subjected to cyclic temperature loads. FEA was conducted on a various geometries of copper via structure for a representative via (with surrounding dielectric) to determine the effect of accelerated temperature cycling and thermal shock. The results were then utilized to interpret the electrical failures in deep silicon copper vias. Following are the assumptions in FEA Model: – The 3D FEA models only one quarter of the package due to symmetry – 8 node solid element is employed. All materials are considered as linear elastic and isotropic except copper. An inelastic rate dependant multi linear isotropic Mises model is used for copper. – For a relative comparison purposes, boundary conditions, element type, smart mesh size, and evaluation index are fixed in view of the singularity effect. – Since the electroplating is conducted at room temperature, the stress in physical structure is assumed to be free at 25 °C. All the materials properties are listed in Table-2 to 4. – Loading: Thermal Cyclying (TC) test (- 40~125 °C). Fig-4(a) shows the stress pattern in silicon dioxide layer which is deposited on via surfaces and Fig-4(b) shows the stress pattern in the Tantalum barrier layer. Both the simulations have been done for through-wafer silicon via structure. Figures 5(a) and (b) similarly show the data for partial silicon via with electrodeposited copper. These 2 sets of simulation work have been done to show that the proposed test is functionally same in terms of stress pattern and hence can still be used for evaluating the performance of a copper via.

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electron microscope (TEM) image taken after copper electrodeposition in Fig-8. Thermal stress modeling data from our work indicates that the stress in the through-wafer copper interconnect structure is mainly concentrated at the ends of the via where the effect of BOSCH process can be felt most due to the sharp scallops. Hence, rest of this section focuses on the reduction of scallops through gradual ramping of critical etch parameter. The Multiplexed Inductive Coupled Plasma tool has the option to vary through software the various etch parameters to achieve better control on process. The parameters that affect the sidewall scallops the most are process pressure, power and etch and passivation cycle time. Figures 6 and 7 show the best etch profile achieved without dynamic parameter variation. Scanning electron microscope (SEM) image in Fig-8 shows the best results after process optimization through dynamic parameter ramping of pressure, power and etch/passivation cycle time. The ramping parameters are summarized in Table-5.

Table-2: Material properties @ 25 °C: Linear elastic Model CTE (-40~125°C )

Silicon 2.6 ppm/K

Young's Modulus

130.91 Gpa

70 Gpa

Poisson's Ratio

0.28

0.17

Silicon dioxide 0.94 ppm/K

Table-3 Plastic Model

Copper

CTE (-40~125°C)

16.12 ppm/K

Young’s modulus

127.4 Gpa

Poisson's ratio

0.36

Yield strength

262 Mpa

Hardening coefficient

315 Mpa

Hardening exponent

0.54

Table-4: Material properties of Tantalum CTE

6.5 ppm/K

Ultimate tensile strength

900 MPa

Modulus of Elasticity

186 GPa

Poisson’s Ratio

0.35

Table-5: Ramping parameters Critical etch parameters

Initial condition

% Ramp rate

Pressure (mTorr)

25

-0.1

Bias power (W)

20

0.1

Etch cycle time (s)

5

0.05

399 MPa

194.1 MPa

(a)

(b)

Fig-4: (a) Simulated stress pattern on SiO2 isolation layer: (b) Stress on Tantalum barrier layer due to thermal cycling on through-wafer copper interconnect structure. 233.7 MPa

413 MPa

(a)

(b)

Fig-5: (a) Simulated stress pattern on SiO2 isolation layer: (b) on Tantalum barrier layer due to thermal cycling on partial throughwafer copper interconnect test structure used in this study.

C. Parametric ramped Deep via etch process The deep silicon etch was carried out using the standard BOSCH process in Surface Technology Systems Multiplex inductively coupled plasma etch system. The main gas precursors are SF6 and O2 for etch and C4F8 for sidewall passivation process, which get repeated alternately till the required trench depth is achieved. As the SF6 /O2 etch chemistry results in isotropic etch, the final result always has scallops or waves as seen in the etch profile shown in Figures 6 to 8. Another feature of the BOSCH process is that the scallops decrease with depth as shown in the transmission

Fig-6: Scallops formed due to cyclical nature of BOSCH process is shown in SEM micrograhs. Edge roughness of ~0.2µm gradually decreases to about 0.01µm after reaching a depth of 4-5 µm

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Fig-9: Deep silicon trenches formed by smooth etch process after dynamic parametric ramping process. Sidewall roughness of ~0.01µm and 0.1µm mask undercut is seen.

Fig-7: TEM picture of 6 µm deep silicon via after copper electroplating showing the sharp edges of the scallops formed during the deep RIE process.

3µmOxide Mask

Fig-10: Deep silicon trenches formed by combination of BOSCH/smooth etch process after dynamic parametric ramping process. Sidewall roughness due to BOSCH process is eliminated in the top edge.

5.0µm

Table-6: Process split table for test vehicle ID

Fig-8: Deep silicon trenches formed by BOSCH process after dynamic parametric ramping process. Sidewall roughness of ~0.05 µm and 0.1 µm mask undercut is seen.

17 18

23

BOSCH with parameter ramp Smooth (non-BOSCH) Smooth (non-BOSCH) Smooth (non-BOSCH) BOSCH with parameter ramp

24 25

BOSCH with parameter ramp Smooth+BOSCH

19

Parameter ramping was also implemented on a nonBOSCH process by similarly ramping the pressure and power as shown in Table-5. The objective in this case was to reduce the mask undercut and sidewall roughness better than that of the BOSCH process. Only one-step process was used with C4F8 as passivation gas and SF6/O2 as the etch gas. As C4F8 is flowing continuously during the etch, the etch rate will be slower but sidewalls would be smoother as seen in Fig-9. A third process variation that was tried was with a combination of smooth sidewall profile for the first 5 µm and then switch to a normal BOSCH process. The results are shown in Fig-10. The main motivation for this process was to rectify the scallops in the initial 4-5 µm of the trench depth as shown in Figures 6 and 7. Once the basic process conditions have been optimized, the test vehicle as described in Fig-3 was fabricated using the process flow shown in Table-1. 9 wafers were run with different process conditions to identify and solve problems due to sidewall roughness and high stress in deep silicon copper interconnections for 3D integrated systems. The process split is summarized in Table-6.

Etch process BOSCH with parameter ramp BOSCH with parameter ramp

20 21 22

Cu-barrier

Via depth

250Ǻ Ta

100 µm

250Ǻ Ta 1000Ǻ Nitride+250Ǻ Ta 1000A Nitride+250Ǻ Ta

10 µm

250Ǻ Ta

10 µm

1000Ǻ Ta

10 µm

1000Ǻ Ta 1000Ǻ Nitride+1000Ǻ Ta 1000Ǻ Ta

10 µm

10 µm 10 µm

30 µm 30 µm

Electrical Characterization All the test structures were tested at room temperature in a standard probe station. The voltage was swept from 0 to 100V between the 2 pads of the comb structures. The substrate was kept floating during the measurement. The results are plotted in Figures 11 to 14 for test structures with vias of 5, 15, 25 and 35µm, respectively.

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3.00E-09

S-17

S-18

S-19

S-20

S-22

S-23

S-24

S-25

S-21

Leakage current (Amps)

2.50E-09

2.00E-09

1.50E-09

1.00E-09

5.00E-10

0.00E+00 0

10

20

30

40

50

60

70

80

90

100

Voltage (volts)

Fig-11: Leakage current between 5 µm vias at 250C S-17

S-18

S-19

S-20

S-22

S-23

S-24

S-25

S-21

1.60E-09 Leakage current in Amps

1.40E-09 1.20E-09 1.00E-09 8.00E-10 6.00E-10 4.00E-10 2.00E-10 0.00E+00 0

10

20

30

40

50

60

70

80

90

100

Voltage in volts

Leakage current in Amp

Fig-12: Leakage current between 15 µm vias at 250C. 1.00E-09

Slot-17

Slot-18

Slot-19

Slot-20

9.00E-10

Slot-22

Slot-23

Slot-24

Slot-25

Slot-21

8.00E-10 7.00E-10 6.00E-10 5.00E-10 4.00E-10 3.00E-10 2.00E-10 1.00E-10 0.00E+00 0

10

20

30

40

50

60

70

80

90

100

Voltage in volts

Fig-13: Leakage current between 25 µm vias at 250C. 2.00E-09 1.80E-09

Slot-17

Slot-18

Slot-19

Slot-20

Slot-22

Slot-23

Slot-24

Slot-25

Slot-21

Leakage current in Amp

1.60E-09 1.40E-09 1.20E-09 1.00E-09 8.00E-10 6.00E-10 4.00E-10 2.00E-10 0.00E+00 0

20

40

60

80

Voltage in volts

Fig-14: Leakage current between 35 µm vias at 250C.

100

Results and Discussion From the stress patterns shown in Figures 4 and 5, we can see that Tantalum barrier layer and the silicon dioxide layer experience much higher stress than copper interconnect at both ends of the via. The partial via structure which has been used as the test structure in this study experiences almost a similar or slightly higher stress than open ended via structures. It was further seen that the stress is mainly concentrated at the bottom and top end of the vias making it vulnerable for stress induced failures at the top and bottom corners. The second part of the study therefore involves achieving good via etch profile with minimum defects at the edges to avoid any stress induced copper diffusion through the silicon dioxide. It was also extremely important from the above simulation study to make sure that the silicon dioxide and tantalum film be conformal and defect free at the top and bottom ends of the interconnects for a good electrical performance. Figures 11 to 14 summarize the copper via to via leakage current for 5, 15, 25 and 35 µm vias, respectively, with different depth and process conditions and tested at room temperature. It can be seen from the split table that we have tried to study the effect of: (a) different etch depths (slots 17 and 18); (b) etch recipes with different sidewall roughness and (c) different barrier process. For the same process conditions, the performance of the copper via is expected to deteriorate as via depth increases due to poorer conformality of the dielectric layer and barrier films. This can be seen clearly in Figures 12 to 15 for slots 17 and 18 in which we had used the same barrier thickness of 250 Ǻ Tantalum. The leakage between the 100 µm deep copper vias (slot 17) is high compared to 10 µm deep copper vias (slot 18). When we added an additional diffusion barrier of 1000 Ǻ nitride before 250 Ǻ Ta, we notice an improvement in terms of leakage current reduction for all the vias except for 5µm vias, which has resulted in a breakdown at 20 V. This is due to copper peeling in the corner of the vias due to higher stress caused by the nitride/tantalum film. A comparison of the leakage trend of slot 18 (BOSCH process) and slot 21 (nonBOSCH process) shows that there is almost 100 times lower leakage current in slot 21 for the same 250 Ǻ Ta barrier thickness. This clearly confirms that sidewall scallops can cause significant non-uniformity in the barrier layer to cause an increase in the leakage current. In another process split, a thicker barrier layer of 1000 Ǻ Ta was deposited and run with both non-BOSCH process (slot 22) and BOSCH process (slot 23). The results still show that the BOSCH process has a higher leakage current but within an acceptable range of few tens of pA. This observation confirms that the sidewall scallops due to BOSCH process can still pose a problem as the aspect ratio is increased (see slot 17). We further notice that as the via size increases from 5 to 35µm, the difference between both the BOSCH and non-BOSCH process becomes almost insignificant due to better conformality of dielectric and barrier layer. In another process variation, an additional layer of 1000 Ǻ silicon nitride was deposited before 250 Ǻ Ta barrier (slots 19 and 20). Again there are 5-6 times larger leakage current in BOSCH processed wafer compared to non-BOSCH processed 347


wafer. But the leakage current for these 2 wafers with the additional 1000 Ǻ nitride is within the acceptable range 10-10 A. Slots 22 and 23 were likewise processed with thicker barrier of 1000 Ǻ tantalum to reduce the effect of roughness due to BOSCH process. The behavior was same as in slots 19 and 20. Having understood the impact of the sidewall scallops for 10 µm trenches and the resultant improvements by increasing the barrier thickness, we decided to apply the thicker barrier films on deeper silicon vias. Accordingly, slot 24 was fabricated with BOSCH process with 1000 Ǻ nitride and 250 Ǻ Ta barrier while slot 25 was fabricated with a combination of smooth and BOSCH process with 1000 Ǻ Ta barrier. The via depth was targeted at ~30µm. Copper peeled off for most of the 5 µm via. In case of larger vias, the copper delamination was not severe but still survived at some sites (see Fig-15). This was mainly due to high film stress causing it to peel during chemical mechanical polishing (CMP) process. Electrical tests on these wafers showed that the leakage current is higher in BOSCH processed wafers compared to smooth+BOSCH processed wafer. This result further confirms that the current leakage can be controlled by smoothening the top corner of the via instead of the entire via.

Fig-15: Copper peeling during CMP process in 5 and 15 µm structures.

practical solution by using a combination of smooth and BOSCH process to minimize the leakage issue. References: 1. J. D. Meindl et al, “Interconnect opportunities for gigascale integration”, IBM J. Res. & Dev. Vol.46, No. 2/3 March/May 2002, pp 245-263. 2. Rafael Reif” et al, “Fabrication Technologies for ThreeDimensional Integrated Circuits”, International Symposium on Quality Electronic Design (ISQED-2002), 18–20 March 2002 — San Jose, CA. 3. N.T.Nguyen et al, “Through wafer copper electroplating for three dimensional interconnects”, Journal of micromechanics and micro engineering, Vol 12 (2002), pp. 395-399 4. C.S.Premachandran and N.Ranganathan, “A Novel Electrically Conductive Wafer Through Hole Filled Vias Interconnect for 3D MEMS Packaging”, 2003 Electronic Components and Technology Conference, May 27 - 30, 2003, New Orleans, Louisiana, USA, pp 627-630. 5. Hyongsok T.Soh et al, “Ultra-Low resistance, throughwafer via (TWV) technology and its applications in three dimensional structures on silicon”, Japanese. J of Appl. Phys, Vol.38 (1999) pp 2393-2396. 6. Seong Joon Ok et al, “ Generic, Direct Chip-Attach MEMS Packaging Design with high density and aspect ratio through-wafer electrical interconnect”, 2003 Electronic Components and Technology Conference, May 27 - 30, 2003, New Orleans, Louisiana, USA, pp 232-237. 7. Kenji Takahashi et al, “Process Integration of 3D Chip Stack with Vertical Interconnection”, 2004 Electronic Components and Technology Conference, 01-04 June, Las Vegas, NV USA pp 601-609. 8. Frank Niklaus et al, “Low-Temperature Wafer-Level Transfer Bonding”, Journal of Micromechanical System, Vol. 10, No. 4, Dec. 2001 pp 525-531. 9. J.Hopkins et al, “The benefits of process parameter ramping during plasma etching of high aspect ratio silicon structures”, Materials Research Society Fall Meeting, Boston, USA, Dec 1998, pp 1-4. 10. J. Bhardwaj et al, “Dry silicon etching for MEMS”, Annual Meeting of the Electrochemical Society, Montreal, Quebec, Canada May 4-9, 1997.

Conclusion Based on the thermal stress modeling we predict that the corners of the via will be the main source of inter-via leakage. We further show that, due to the nature of the BOSCH process, there is a high potential for leakage to occur due to rough sidewall. We have accordingly designed a test structure to electrically measure the impact of the BOSCH and smooth sidewall process and confirm that there is a significant impact due to the sidewall roughness, which gets eliminated with a smooth sidewall process. We have also attempted to extend the usage of BOSCH process by optimizing it to given minimum sidewall roughness though process parameter ramping and further improve it by using thicker barrier layers. However, it creates other process issues like copper peeling due to high film stress. Finally, we have also offered a more

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