1 I, NOVEMBER 1996. High Dbose-Rate Hydrogen Passivation of Polycrystalline Silicon CMOS. TFT's by Plasma Ion Implantation. James D. Bernstein, Member, ...
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 43, NO. 1 I , NOVEMBER 1996
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High Dbose-Rate Hydrogen Passivation of Polycrystalline Silicon CMOS TFT's by Plasma Ion Implantation James D. Bernstein, Member, IEEE, S h u Qin, Member, IEEE, Chung Chan, Senior Member, IEEE, and Tsu-Jae King
Abstract-Plasma ion implantation (PII) hydrogenation is an efficient method for defect passivation in polycrystalline silicon (poly-Si) thin film transistors (TFT's). We have developed a process that can achieve saturation of device parameter improvement in 30 min, whereas conventional plasma hydrogenation takes approximately 4 h. Our model predicts that much shorter process times are possible. We have analyzed the gate oxide charging which occurs during the PI1 process and controlled it to the extent that processed devices are damage-free. The longterm reliability of PI1 hydrogenated devices is superior to that of conventional parallel-plate plasma hydrogenated devices.
I. INTRODUCTION
P
OLYCRYSTALLINE silicon (poly-Si) thin film transistors (TFT' s) have applications to large area electronits, such as active matrix liquid crystal flat panel displays and three-dimensional (3-D) integrated circuits. The performance of poly-Si TFT's is limited by grain boundary and intragranular defects characteristic of polycrystalline films. In the hydrogenation process, hydrogen bonds with Si dangling bonds at grain boundaries, reducing the number of trap states and lowering grain boundary potential barriers. Strain bond trap states are also passivated. Several plasma hydrogenation methods have received considerable attention. One method is by immersion in a capacitively coupled plasma produced by an alternating current parallel plate reactor [ 11-[3]. Another is by immersion in an electron cyclotron resonance (ECR) plasma [4]-[6]. While both of these "ethods have been shown to improve device characteristics, tlheir minimum process times are limited by the physical mechanisms which determine their dose rates. Recently, plasma ion implantation (PII) has been shown to be an effective hydrogenation method capable of short process times [7]. PI1 is a promising technique for materials [SI and semiconductor processing [9], [ 101. The PI1 process is performed by repetitively applying a large Manuscript received August 25, 1995; revised March 23, 1996. The review of this paper was arranged by Editor K. Shenai. This work was supported in part by AFOSR Grant F 49620-94-1-0096. J. D. Bernstein was with the Plasma Science and Microelectronics Research Laboratory, Department of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115 USA. He is now with Eaton Corporation, Semiconductor Equipment Operations, Beverly, MA 01915 USA. S. Qin and C. Chan are with the Plasma Science and Microelectronics Research Laboratory, Department of Ekctrical and Computer Engineering, Northeastern University, Boston, MA 021 1.5 USA. T.-J. King is with Xerox Palo Alto Research Center, Palo Alto, CA 94304 USA. Publisher Item Identifier S 0018-93831:96)07721-0.
negative voltage pulse to a wafer immersed in a hydrogen plasma. Hydrogen ions are accelerated by the target potential and implanted into the sample. Ion energies can range from 1 to 100 keV with average ion flux densities as high as 10IGcmP2 s-I. The major criteria for evaluating a hydrogenation method are the effectiveness of the treatment, process time, and its impact on device reliability. In this paper, the PI1 hydrogenation method is evaluated with respect to each of these three criteria. The effectiveness of the treatment is shown by the dramatic improvement in device characteristics. Saturation of device parameter improvement is achieved in a fraction of the process time required by conventional plasma immersion treatments. Gate oxide charging is kept at safe levels by the appropriate choice of PI1 process parameters. 11. EXPERIMENTAL PROCEDURE Poly-Si TFT's were fabricated on a fused silica substrate. Undoped 100-nm thick amorphous silicon films were deposited by low-pressure chemical vapor deposition (LPCVD) and were crystallized with a 4 h anneal at 600 "C. After the definition of silicon island regions, a 85-nm thick gate oxide was deposited by LPCVD and then annealed at 950 "C in an 0 2 ambient, resulting in a final gate-dielectric thickness of 100 nm. A 350-nm thick poly-Si gate layer was then deposited and patterned. Self-aligned source/drain regions were formed by phosphorus or boron ion implantation for n-channel or p-channel devices, respectively. Afterwards, a 700-nm thick passivating layer of LPCVD oxide was deposited and a 14 h dopant activation anneal was performed at 600 "C. Device fabrication was completed with conventional contact hole formation and AlCu deposition and etch processes, and the TFT's were sintered at 450 "C for 30 min in forming gas. A schematic cross-sectional view of the TFT structure is shown in Fig. 1. The plasma ion implantation system consists of a chamber with a multipolar magnetic field structure, microwave source, vacuum and gas handling, temperature control, and high voltage pulse generator. The aluminum chamber is 30 cm high and 36 cm in diameter. The outside wall of the chamber is surrounded by a ring of parallel rows of permanent magnetic bars (1000 G at the pole) which are arranged such that successive north and south poles face the plasma in the socalled multipolar magnetic bucket structure. The benefit of this structure is that higher ion density and better radial ion density
0018-9383/96$05.00 0 1996 IEEE
BERNSTEIN et al.: HIGH DOSE-RATE HYDROGEN PASSIVATION
PMOS TFT
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HYOROGEN PLASMA
NMOS TFT
GATE DIELECTRIC
BUFFER OXIDE
SUBSTRATE
Fig. 1. Schematic cross-sectional view of the CMOS TFT structure.
SOURCE
QUARTZ
WINDOW
HV PULSE
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Fig. 2. The plasma ion implantation hydrogenation system.
uniformity in the chamber are obtained because the electrons are reflected back into the plasma by the magnetic mirror rather than being lost to the chamber walls. The microwave source includes a magnetron and a three-stub tuner. The magnetron can supply up to 1000 W of continuous microwave power at a frequency of 2.45 GHz. The tuner matches the magnetron output to the plasma load. A high voltage pulse generator is used to bias the wafer holder. A simplified diagram of the PI1 hydrogenation system is shown in Fig. 2. PI1 hydrogenation process conditions were as follows: base pressure torr, working pressure 50 mtorr, microwave power 730 W, pulse voltage -6 kV, pulse repetition rate 4000 Hz, pulse width 5 ps, and sample temperature 3 5 0 f 2 0 "C. Some TFT's were also immersed in the microwave hydrogen plasma without applying the high voltage pulse. Conventional plasma immersion hydrogenation was performed in a parallel plate reactor at 350 "C with a H2 and Ar gas mixture [2]. TFT characteristics were measured throughout the experiment with a Hewlett Packard 5155A semiconductor parameter analyzer.
111. RESULTSAND DISCUSSION Fig. 3(a) and (b) shows typical subthreshold Ids-vgs characteristics for n- and p-channel devices with widthto-length ratios W / L = 50 pm/50 pm before and after microwave PI1 hydrogenation. Conventional plasma immersion hydrogenated TFT's and devices immersed in our microwave plasma without applying a voltage pulse are
Gate Voltage (V) (a)
10 hr. pwae immersion 8 hr. paranid plate ,___
-30 min. PI1
Gate Voltage (4) (b) Fig. 3. Subthreshold Ids-I/gs characteristics for (a) n- and (b) p-channel devices with width-to-length ratios W /L = 50-pd50-fim before and ;after plasma hydrogenation.
included for comparison. N-channel mobility increased from 66.9 to 94.5 cm2/V.s, d o f f current ratio increased from 1.1x lo6 to 4.6 x lo7, threshold voltage decreased from 5.4 to 2.3 V, and subthreshold slope decreased from 0.88 to 0.3 V/dec after PI1 hydrogenation. P-channel devices experienced similar
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL 43, NO. 11, NOVEMBER 1996
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Fig. 4. Evolution of TFT parameter improvement for (a), (b) microwave plasma immersion; (c), (d) conventional parallel plate plasma immersion; and (e), (f) PI1 hydrogenation treatments.
improvements with mobility increasing from 48.3 to 59.9 cm2/V.s, on/off current ratio increasing from 9.9 x l o 5 to 1.2 x lo7, threshold voltage changing from -5.0 to -3.6 V, and subthreshold slope from 1.17 to 0.54 V/dec. The hydrogenated n-channel device characteristics are nearly identical for all three plasma treatments. While all three methods also improve PMOS TFT performance, the microwave immersion treatment
results in better threshold voltage, subthreshold slope, and mobility than do the parallel plate immersion or PI1 treatments. ECR hydrogen plasma immersion also produces better pchannel device characteristics. However, ECR processed NMOS TFT characteristics are significantly worse than those exhibited by the same devices processed by PI1 or parallel plate immersion [7].
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BERNSTEIN et al.: HIGH DOSE-RATE HYDROGEN PASSIVATION
These differences in ECR hydrogenated device performance are not well understood. Evolution of device parameter improvement for the different plasma treatments is shown in Fig. 4. Microwave plasma immersion [Fig. 4(a) and (b)] takes about 10 h, conventional parallel-plate plasma immersion [Fig. 4(c) and (d)] takes about 4 h, and PIT takes about 30 min. [Fig. 4(e) and (01. Fig. 4(c) shows some instability in device parameter improvement during the parallel plate treatment. Although TFT's hydrogenated with this method typically require about 4 h, a treatment that lasts several hours longer (6-8 h total hydrogenation time) is usually needed to ensure that TFT parameter variations have subsided for all the devices on the test chip. There is significant disparity in the required hydrogenation times for the different treatments due to the physical mechanisms specific to each process that limit the rate at which hydrogen enters the device. Hydrogen diffuses through the passivation oxide layer and into the channel, regardless of the hydrogenation method. This is true even for the higher energy PI1 method, where TRIM [ 111 simulations have verified that the stopping range of 6 keV hydrogen is well within the 7000A thick passivation oxide layer. The conventional parallel plate reactor immersion treatment is limited to a low dose rate due to the low ion densities ( a ; % lo9 cm-3) characteristic of capacitively coupled plasmas. Hydrogen is introduced into the passivation oxide by low energy ion penetration. The microwave plasma density is substantially higher (n;z 2.5 x lo1' ~ m - ~ but ) , the dose rate is limited by the 23 V sheath potential when the high voltage PI1 pulse is not applied. In the PI1 process, the sheath potential is dramatically increased by the high voltage pulse. The dose rate enjoys a corresponding increase. There are also other mechanisms which contribute to the short PI1 process time. The ion energies in the conventional and microwave immersion methods place hydrogen at the oxide surface, where they can easily be knocked away by other incoming hydrogen ions. Since the highest hydrogen concentration is at the surface, it quickly diffuses out into the process chamber. The higher energy PI1 method will implant hydrogen deeper into the oxide. Also, different plasma sources operating at a range of pressures produce different ion species compositions. For example, a higher pressure system may produce higher relative concentrations of H t and H3$. Since PI1 ions are accelerated at higher energy, most of the larger species will dissociate upon impact. This is beneficial since the smaller species will diffuse faster and are probably responsible for defect passivation. Temperature control is critical to the hydrogenation process. Wafers were pre-heated on the wafer holder prior to hydrogenation. We have found that devices treated at temperatures significantly lower than 350 "C required an extended treatment or a post-hydrogenation anneal to obtain similar characteristics to the devices described above. Devices treated at 350 f 20 "C could not be improved further. TFT performance was degraded when processed at temperatures over 390 "C. Hydrogen will detrap from Si bonds at temperatures greater than 400 "C [12]. It was previously shown [2] that when the hydrogen influx is relatively small in concentration, the initial hydrogen supplies exhibit a preference toward the grain boundary defects that
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influence threshold voltage and subthreshhold slope. Passivation of the tail states from strain bonds which affect mobility and leakage current does not begin until after a large fraction of the midgap grain boundary defects are passivated. Our investigation of the relation between device parameter improvement and PI1 process time led to the conclusion that there may be a different defect passivation mechanism for PI1 hydrogenation [7]. Both deep and tail states will be passivated simultaneously during PI1 hydrogenation if the hydrogen concentration is large enough compared to that of the coordination defects. In these experiments, all parameters are affected almost immediately for all hydrogenation methods. This is probably due to the relatively low density of trap states in these high temperature processed devices. In order to develop a reliable PI1 hydrogenation process, it is necessary to keep the charging of the gate oxide at a minimum. Since the implant target consists, in part, of dielectric layers, there will be charge accumulation during the time of the PI1 high voltage pulse which can result in gate oxide breakdolwn. The accumulated charge can be calculated by first considering the implant current density. A collisional dynamic shl-ath model [13] modified to account for ions entering the sb-ath with Bohm velocity and the effect of charge accumulation [ 141 results in the following equation for implant current density
j i ( t ) = E o (4;3 -
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VY2(t) s5/2( t )
where
V s ( t )= v, -
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V7(t)is the effective sheath potential, V, is the initial pulse potential, C is the capacitance per unit area of the insulator layers, E O is the free-space permittivity, 7 is the pulse wiidth, A, is the ion-neutral mean free path and M is the ion mass. The position of the sheath edge s ( t ) in (1) can be determined by solving
where U B = is the Bohm velocity, e is the ion charge, and T, is the electron temperature. The quartz substrate, which is the thickest dielectric layer in the device ( d = 525 pm), dominates the wafer capacitance and thus has the greatest effect on the implant current and charge accumulation. The total accumulated charge is obtained by integrating the implant current density across the pulse width ^
