High-Efficiency 312-kVA Three-Phase Inverter Using ... - IEEE Xplore

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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 51, NO. 6, NOVEMBER/DECEMBER 2015

High-Efficiency 312-kVA Three-Phase Inverter Using Parallel Connection of Silicon Carbide MOSFET Power Modules Juan Colmenares, Student Member, IEEE, Dimosthenis Peftitsis, Member, IEEE, Jacek Rabkowski, Senior Member, IEEE, Diane-Perle Sadik, Student Member, IEEE, Georg Tolstoy, Student Member, IEEE, and Hans-Peter Nee, Senior Member, IEEE

Abstract—This paper presents the design process of a 312-kVA three-phase silicon carbide inverter using ten parallel-connected metal–oxide–semiconductor field-effect-transistor power modules in each phase leg. The design processes of the gate-drive circuits with short-circuit protection and power circuit layout are also presented. Measurements in order to evaluate the performance of the gate-drive circuits have been performed using a double-pulse setup. Moreover, electrical and thermal measurements in order to evaluate the transient performance and steady-state operation of the parallel-connected power modules are shown. Experimental results showing proper steady-state operation of the power converter are also presented. Taking into account measured data, an efficiency of approximately 99.3% at the rated power has been measured for the inverter. Index Terms—Inverter, metal–oxide–semiconductor field-effect transistors (MOSFETs), parallel connection, power module, silicon carbide (SiC).

I. I NTRODUCTION

T

HE outstanding performance of silicon carbide (SiC) power semiconductor devices has been shown in a wide range of power electronics applications [1], such as power factor correction [2], telecom [3], microgrids [4], wind power [5], high-voltage direct current transmission [6], modular multilevel converters [7], [8], inverters [9]–[11], automotive applications [12]–[14], solar power [16], and dc–dc converters [17]–[19]. Manuscript received November 27, 2014; revised May 15, 2015; accepted July 3, 2015. Date of publication July 14, 2015; date of current version November 18, 2015. Paper 2014-PEDCC-0967.R1, presented at the 2014 IEEE Energy Conversion Congress and Exposition, Pittsburgh, PA, USA, September 20–24, and approved for publication in the IEEE T RANSACTIONS ON I NDUSTRY A PPLICATIONS by the Power Electronic Devices and Components Committee of the IEEE Industry Applications Society. This work was supported in part by the Swedish Agency for Innovation Systems (Vinnova) and in part by the Swedish Energy Agency. J. Colmenares, D.-P. Sadik, G. Tolstoy, and H.-P. Nee are with the Department of Electrical Energy Conversion, KTH Royal Institute of Technology, 100 44 Stockholm, Sweden (e-mail: [email protected]; [email protected]; gtolstoy@ kth.se; [email protected]). D. Peftitsis is with the Laboratory for High Power Electronic Systems, Swiss Federal Institute of Technology (ETH), 8092 Zurich, Switzerland (e-mail: [email protected]). J. Rabkowski is with the Institute of Control and Industrial Electronics, Warsaw University of Technology, 00-661 Warsaw, Poland (e-mail: rabkow@ kth.se; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIA.2015.2456422

These applications can be categorized either as “highefficiency,” “high-switching-frequency,” or “high-temperature” SiC power electronics applications [1]. Depending on the choice of design target, different characteristic advantages of SiC power devices can be utilized. In order to achieve high production yields, the currently available SiC power devices employ comparably small chip areas, which results in low current ratings for discrete devices [20], [21]. In the literature, two different solutions to reach high current ratings for SiC switches can be found: either to parallel connect several single-chip discrete devices or to build multichip power modules. The first solution has been deeply investigated for parallel-connected SiC junction fieldeffect transistors (JFETs) [20], [21], bipolar junction transistors [22], and metal–oxide–semiconductor field-effect transistors (MOSFETs) [23], [24]. Regardless of the type of SiC power device and the spread of the device parameters, it has been shown in all investigations that the circuit layout and, in particular, the uneven distribution of various parasitic elements in the circuit layout are significant factors affecting the performance of parallel connection of single-chip devices. For multichip modules, on the other hand, it is believed that the influence of the external circuit layout on the switching performance is less significant if a symmetrical layout of the electrical circuit inside the modules can be achieved. However, it has been shown that problems associated with the “Miller effect” might affect the stable operation of the module [25], [26]. In particular, the Miller effect may cause accidental turn on and self-sustained oscillations between the Miller capacitance of the parallel-connected single chips and the stray inductances of the external circuit layout and of the circuit layout of module as such. In [27], a gatedrive circuit, which mitigates the Miller effect, at the cost of slower switching transients for normally on SiC JFETs, has been proposed. Similar solutions have been also proposed for SiC MOSFET and other JFET power modules [28]–[33]. Another possibility to reach power ratings on the order of hundreds of kilovoltamperes, which has not been studied before for SiC, is the parallel connection of power modules, which has been studied for silicon (Si) insulated-gate bipolar transistors [34], [35]. An additional possibility for this power rating is the parallel connection of power converters [36]. Several studies have been performed using SiC MOSFET power modules evaluating the switching performance and high-temperature and

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COLMENARES et al.: THREE-PHASE INVERTER USING PARALLEL CONNECTION OF MOSFET POWER MODULES

high-frequency operation [37]–[42]. If the parallel connection of modules is chosen as a method, several issues must be dealt with, in order to ensure a well-performing converter. The design process of the gate-drive unit and power circuit layout must also comply with the design target of the whole system (i.e., high efficiency, high switching frequency, or high temperature). Moreover, protection against short circuit is necessary during the design process of the whole system. High short-circuit currents might result in severe reduction of the lifetime of the devices [43]–[47]. Unlike previous investigations of parallel connection for increased power ratings [20]–[24], this paper presents the potential benefits and the design process of employing massive parallel-connection SiC MOSFET power modules in a threephase two-level voltage source converter (VSC) for motor-drive applications rated at 312 kVA [48], [49]. The target of this investigation is to show that a higher efficiency might be reached compared with the corresponding silicon VSCs [50], whereas switching frequencies well above 20 kHz are feasible despite the high power rating. In particular, the latter target also results in a less bulky output filter design, which is very important if high compactness and low weight are targeted. The presented VSC consists of ten parallel-connected SiC MOSFET power modules in each phase leg, where each module is configured as a half-bridge. In Section II, a description of the SiC power module is given, as well as the design inputs. A description of the construction process is also given. In Section III, the design process of the gate drivers is presented in detail. Section IV shows recorded experimental results for several cases analyzed. Power losses and efficiency calculations are also presented. Finally, the results are discussed in Section V, and conclusions are drawn in Section VI. II. D ESIGN I NPUTS AND C ONSTRUCTION OF THE T HREE -P HASE I NVERTER As aforementioned, in this paper, the target is high efficiency (> 99%) at a relatively high switching frequency (20 kHz) for a three-phase two-level VSC for motor-drive applications. An output current of 450 A RMS (636 A peak) is considered at a dc-link voltage of 650 V. Assuming a typical three-phase output voltage of 400 V RMS, the rated power of the threephase inverter is 312 kVA. In order to reach high efficiency, it is necessary to study the ON-state losses, switching losses, and driver losses. The ON -state resistance, and therefore the conduction losses, must be reduced. It was consequently decided to connect several power modules in parallel. The half-bridge SiC power module used in this project (Cree, Inc. CAS100H12AM1, which is commercially available) has the ratings of 1200 V and 168 A, at room temperature (RT) [see Fig. 1(a)]. Each switch position of the power module is equipped with five parallel-connected 80-mΩ SiC MOSFET chips and five antiparallel SiC Schottky diodes [see Fig. 1(b)]. The total MOSFET chip area is 80 mm2 , and the ON-state resistance at RT is equal to 16 mΩ for a single module. Due to the placement of the chips inside the module, an appropriate way to represent a power module switch position is shown in the circuit diagram in Fig. 1(c). In this figure, LD , LS ,

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Fig. 1. (a) Photograph of the SiC power module. (b) Schematic of a single switch position of the SiC MOSFET power module. (c) Combined schematic of a single switch position and module.

and LG represent the sum of parasitic inductances of the drain, source, and gate leads, respectively. These parasitic inductances affect the switching performance, and therefore the switching losses, when a parallel connection is targeted [20]–[24]. Parallel connection of the power modules increases the total chip area and decreases the ON-state resistance; thus, expected conduction losses will be reduced, as shown in Fig. 2(a). Therefore, it was decided to connect ten modules in parallel per switch position as a compromise between low ON-state power losses, current density, and system complexity. On the base of the datasheet information, it was found that the ON-state power losses are expected to be between 0.3% and 0.4% of nominal power if ten parallel-connected modules are chosen [see Fig. 2(b)]. This value is reasonable with the project goal (total loss < 1%). A closer examination of Fig. 2(b) reveals a small negative temperature coefficient of the conduction losses below 40 ◦ C. This is, however, not a problem because the estimated operating temperature is approximately 75 ◦ C. It must be noted that the parallel-connected power modules were connected in the phase legs without any sorting whatsoever. The schematic of the phase leg, built with ten parallelconnected SiC power modules, is shown in Fig. 3(a). Based on calculations, it was found that parallel connecting ten power modules meets the requirements for high efficiency and current density. When ten power modules are connected in parallel, the

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Fig. 2. (a) Relative ON-state power loss versus junction temperature and number of parallel-connected modules. (b) Relative ON-state power loss versus junction temperature for ten parallel-connected modules (CAS100H12AM1)— calculation using datasheet values. ON -state resistance and the conduction losses are divided by ten, whereas the switching losses are unchanged. Additionally, at rated load, the current of each power module is sufficiently high to increase the junction temperature to the level where the ON-state resistance is well within the positive-temperaturecoefficient range. This is a necessary requirement for the autobalancing mechanism of the current sharing among the parallel-connected power modules. Moreover, an even number is crucial for a symmetrical placement and system complexity. In order to maximize the efficiency, the channels of the MOSFETs are also used in the reverse direction [52]. A blanking time of 600 ns is chosen to avoid short circuit of the dc power supply. During this blanking time, the antiparallel diodes conduct. In order to reduce and balance the stray inductances between the various connections in the experimental setup, a symmetrical placement of the power modules in the leg was used. This is possible due to U-shaped bus bars in each phase. The positive and negative bus bars are placed on top of each other, and therefore, the stray inductances introduced by them are partially cancelled, as shown in Fig. 3(b). The figure shows in blue and red the magnetic field generated by the positive (bottom) and negative (top) bus bars, respectively.

Fig. 3. (a) Schematic of a single phase setup. (b) Layout of the bus bars for the inverter. (c) Photograph of the partially built three-phase inverter.

This configuration has been used in previous studies using discrete devices [9]. However, in this work, power modules are used. Due to the large dimensions of the circuit, the dc capacitance has been distributed throughout the circuit, ensuring that the energy source is as close as possible to each of the power modules. Moreover, eight interconnections have been made between the bus bars and the phase connections, in order to ensure that the current, including the second-order harmonic, is shared uniformly among the capacitors. These interconnections ensure that the matrix connection of capacitors behaves as a single capacitor. Additionally, distributed gate drivers are connected


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TABLE I E LECTRICAL PARAMETERS OF THE T HREE -P HASE I NVERTER

directly to the gate pins of the power modules so that a reduced stray inductance of the gate leads is achieved. This is important for minimizing the Miller effect. A photograph of the partially built inverter with the proposed bus-bar system and distributed capacitors is shown in Fig. 3(c). By utilizing SiC power devices, higher switching frequencies could be achieved than if Si devices were used. The main benefit of the increased switching frequency is that the dclink capacitance can be reduced. The reduced capacitance simplifies the design by making it easier to distribute a high number of comparably small capacitors along the bus bars, a feature that ensures that all power modules are close to a dclink capacitor. For this design, it was decided to use MKP capacitors (metalized polypropylene film capacitors), which meet the requirements for voltage rating and capacitance for the application, in order to keep the complexity of the system within reasonable limits. Additionally, one of the goals of this design is to show that massive parallel connection of power modules having lower current ratings is possible. These low-current-rating power modules can switch faster than higher current rating ones, and by parallel connecting them, it is possible to achieve both benefits of fast switching performance and high current capability. Taking into account the information presented in [51], the dc capacitance was calculated for a maximum ripple of the direct voltage that is equal to 10 V. Considering the previous design inputs, the total dc capacitance was found to be 720 μF. Table I shows the final electrical parameters of the three-phase inverter. III. G ATE D RIVER The switching losses, defined mainly by the switching times, are controlled by the switching speed of the gate-drive units. A. Design of the Gate Driver First of all, the control signal is fed to the drivers by means of optical fibers in order to avoid parasitic effects associated with electrical signal transmissions. Based on a totem-pole configuration, a simple gate driver is applied for the selected power module. Through the choice of the positive and negative supply voltages along with the turn-on and turn-off gate resistances, the switching speeds, and therefore the switching losses, are controlled. In addition, this driver should be able to supply high current peaks for a short time, ensuring the short switching times, needed for the high-efficiency approach.

Fig. 4. (a) Schematic of the gate driver with the short-circuit protection. (b) Photograph of the gate-drive unit.

A short-circuit detection scheme is also implemented within the driver [46]. When a fault is detected, the device should be turned off slowly. Fig. 4(a) shows the schematic of the gate-drive unit used for the SiC power module. The turn-on current, represented by the solid arrow in Fig. 4(a), is controlled through D1 and R1 . Similarly, the turn-off current shown with the dashed arrow in Fig. 4(a) is controlled through D2 and R2 . The drain–source voltage of the switch position is sensed through diode D3 . An additional Zener diode D4 clamps the voltage in order to protect all logic circuits. A Schmitt trigger AND is chosen for its high noise immunity. Above a certain threshold voltage sensed by the aforementioned diode D3 , the Schmitt-trigger AND M3 will sense a high signal, thus setting its output to the high level. This high level will toggle a D-type latch M4 , which will transfer the enable and error signals. An additional AND gate M2 is necessary to set the module off as soon as the protection is activated. In order to avoid false triggering of the short-circuit detection during transient times, the RC filters τ1 and τ2 are connected before M3 . They are used to adjust the detection delay time depending on the application. During rated inverter operation, each of the power modules will conduct an average peak current of 63.64 A. This value is calculated from the total peak current of the inverter, assuming an RMS current of 450 A. If a shortcircuit condition is detected in one module, the complete phase leg will be disconnected. This is mainly due to the parallel connection between the modules, i.e., the same blocking voltage across the switches. Fig. 4(b) shows a photograph of the gatedrive unit.

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Fig. 5. Short-circuit detection using the proposed gate driver. Measured drain– source voltage of the SiC MOSFET (purple line, 200 V/div), drain–source current of the SiC MOSFET (pink line, 500 A/div), logic signal from the latch (green line, 50 V/div), and gate–source voltage of the SiC MOSFET (yellow line, 50 V/div) (time base: 200 ns/div).

B. Experiments on the Gate Driver Finally, an experimental evaluation of the gate driver was performed for a single power module (CAS100H12AM1). This evaluation is divided into two parts. First, a short-circuit condition test was performed, in order to determine if the driver is able to detect a short circuit. The second part is the so-called “double-pulse test” (DPT), which is carried out to verify the switching capability of the gate drivers. The experimental setup consists of a capacitor C = 160 μF that is connected with a voltage supply VDC and a load, which is an air coil inductor, L, having an inductance of 150 μH. For the first case, the short-circuit condition, the upper transistors of the modules were continuously kept in the ON-state, while a pulse of 1 μs was applied to the gate of the lower position, and VDC was set to 600 V. Fig. 5 shows the shortcircuit detection performance for a single switch position; the driver detects the short circuit within approximately 250 ns and turns off the switch position in 50 ns, i.e., that the switch position is in the OFF-state at approximately 300 ns after the pulse was applied. During this period of time, the current has already increased to 800 A, which is five times higher than the rated current of a single power module. An overshoot of almost 400 V is observed during the turn-off process. This is mainly due to the high di/dt during this period, which generates a voltage over the stray inductance. The switching operations of the SiC MOSFETs power module in a DPT using the proposed gate driver are shown in Fig. 6(a) and (b). The turn-on and turn-off processes take approximately 50 ns, which are similar to the times reported in previous studies [48], [49]. This means that a short-circuit protection is achieved without compromising the switching performance of the power module. From Fig. 6(c), the measured data from voltages and currents were applied to determine switching energies during turn-on and turn-off transients. It is found that the switching losses are approximately 5 mJ per module (700 V DC and 45 A per module). Assuming a VSC rated at 312 kVA, proposed in this paper, an estimation of the total power losses, as well as

Fig. 6. (a) Turn-on and (b) turn-off switching waveforms of the power module with the proposed gate driver. Measured drain–source voltage of the SiC MOSFET (purple line, 200 V/div), drain–source current of the SiC MOSFET (pink line, 50 A/div), and gate–source voltage of the SiC MOSFET (yellow line, 20 V/div) (time base: 50 ns/div). (c) Switching energies during turn on and turn off.

the efficiency, has been performed. With an assumed ON-state resistance of 1.8 mΩ at the junction temperature 75 ◦ C, the corresponding conduction and switching losses were found to be 972 and 1.22 kW, respectively, using Pcd = (Irms )2 RDSon × 3 Psw =

IRMS VDC fsw (Eon + Eoﬀ ) × 30. ITEST VTEST π

(1) (2)


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Fig. 7. Calculated rated power losses of three-phase inverter versus junction temperature and power factor.

The diode losses have been neglected because the diodes only conduct during the blanking time, which is significantly lower than the conduction time of the MOSFET channel. The switching loss estimation was performed using MATLAB. Moreover, the converter efficiency is found to be approximately 99.325%, which has been calculated using η = 100 ×

Pn − (Psw + Pcd ) Pn

(3)

at the rated power. These values together with datasheet information and the third quadrant behavior of the devices [52] were used to estimate the total power losses of the full-scale inverter (ten parallel-connected modules per switch position). As shown in Fig. 7, the expected power losses are below the project goal (1%), and thus, the total efficiency is above 99% in the whole range of junction temperatures and for all possible power factor values. IV. E XPERIMENTAL R ESULTS The experimental verification of the 312-kVA SiC inverter was subdivided into two steps. First, a single phase leg was built and tested. The transient analysis was studied using a DPT. The steady-state operation, on the other hand, was investigated with a phase leg connected as a dc–dc step-down converter. Finally, the complete three-phase inverter was built and tested at the rated power. In order to limit the dissipated power in the laboratory, this part of the tests was performed with an inductive load (This dissipated power was fed by a dc power supply.). 1) Single Phase Leg: The switching performance of the parallel-connected SiC MOSFET power modules was investigated by running several DPTs and dc–dc converter measurements as aforementioned. The definition used for the rise and fall times is the time required for the currents to rise or fall from 10% to 90% of the final values, or vice versa. Fig. 8(a) illustrates the experimental setup, which consists of a dc capacitor C connected with a dc power supply VDC and a load, which is an air coil inductor L, and its resistance represented by R.

Fig. 8. (a) Schematic of the DPT setup. (b) Photograph of the DPT setup prototype.

TABLE II PARAMETERS OF THE E XPERIMENTAL S ETUP FOR THE DPT

A photograph of the DPT setup (single phase leg) is shown in Fig. 8(b). The flying wires shown in the photograph are optical fibers between the microcontroller and the drivers of the power modules. The optical fibers are used in order to avoid electromagnetic interference on the control signal and to avoid a galvanic connection between the control board and the gate drivers. Table II summarizes the parameters of the experimental setup. A data acquisition system is used for these tests, which is of the following type: National Instrument® PXI-5105. It has eight simultaneously sampled channels, 12-bit vertical resolution, 60-MS/s real-time sampling rate, and 60-MHz analog bandwidth. A. Transient Performance The devices under test are the lower switch positions, whereas the upper switches only operate as freewheeling diodes. In this part, VDC was set to 700 V. Fig. 9 shows the steady-state current sharing of the power modules. It is observed that modules 1 and 8 are taking significantly higher currents than module 6. One possible reason for this is the lower stray inductance between the midpoints of modules 1 and 8 and the connection

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Fig. 9. Current sharing of the SiC MOSFETs. Measured drain–source current of each SiC power module.

Fig. 11. Steady-state operation of the phase-leg test setup prototype. Measured drain–source voltage of the SiC MOSFETs (purple line, 200 V/div), drain current of the SiC MOSFET M2 (pink line, 10 A/div), drain current of the SiC MOSFET M6 (green line, 10 A/div), and ripple current of the inductor (yellow line, 50 A/div) (time base: 50 ns/div).

higher current for a certain period of time, as shown in Fig. 10. It is believed that this overshoot of the current is due to a mismatch in the MOSFET power modules characteristics. In particular, for this case, a difference of threshold voltage among the power modules will generate a difference in the instance that the power modules switch off. This difference in time will create an increase in the currents among the power modules that switch slower. This unequal transient current sharing will cause a difference in turn-off losses among the modules. B. Steady-State Operation

Fig. 10. Measured drain–source current of each SiC power module. (a) Turnon transient of the SiC MOSFETs. (b) Turn-off transient of the SiC MOSFETs.

to the inductor, the output of the phase-leg prototype. Another possible reason is a mismatch in the device characteristics of the MOSFET power modules, such as the transconductance, ON -state resistance. The rest of the modules share the static current with a maximum difference of 25%. Fig. 10(a) shows the turn-on transient. The current waveforms of the ten parallel-connected power modules waveform are shown in Fig. 10. The turn-on process takes approximately 35 ns. During this period, the current sharing is acceptably uniform. Fig. 10(b) shows the turn-off transient, where the current waveforms of the parallel-connected power modules and the voltage waveform are shown. The turn-off process takes approximately 50 ns. The turn-off current sharing is uniform for all the modules, except for modules 2 and 8, which conduct a

During the test, VDC was increased until approximately 600 V, resulting in an output current of 90 A, when using a duty ratio of 0.18. A total output power of 9.9 kW was reached, which is approximately 10% of the nominal power for one phase leg. In this case, the data acquisition system was not used due to its saturation limit during the turn-on overshoot. Fig. 11 shows the results during steady-state operation, where it can be noted that the converter is operating in the continuous conduction mode. The current sharing of modules 2 and 6 is observed. The steady-state current is approximately 9 A. It is also noted that the ripple current of the inductor is approximately 50 A. Fig. 12(a) shows the turn-on transient. The current waveforms of the parallel-connected power modules and the drain– source voltage waveform are shown. The turn-on process takes approximately 35 ns. During this period, the current sharing is acceptably uniform. Fig. 12(b) shows the turn-off transient. The turn-off process takes approximately 50 ns. The turn-off current sharing is sufficiently uniform for the modules. During the second test, the load resistor was removed, in order to reach higher currents. The duty ratio was set to 0.1, and using the air coil inductor as load itself, VDC was increased until the output current reached 450 A, i.e., nominal output current. Fig. 13 shows the results during steady-state operation, where it can be noted that the converter is operating in the continuous conduction mode. The current sharing of modules 2, 4, 6, and 8


Fig. 12. (a) Turn-on and (b) turn-off transient of the phase-leg test setup prototype. Measured drain–source voltage of the SiC MOSFETs (purple line, 200 V/div), drain current of the SiC MOSFET M2 (pink line, 10 A/div), drain current of the SiC MOSFET M6 (green line, 10 A/div), and ripple current of the inductor (yellow line, 50 A/div) (time base: 50 ns/div).

Fig. 13. Steady-state operation of the phase-leg test setup prototype. Measured drain current of the SiC MOSFET M8 (purple line, 20 A/div), drain current of the SiC MOSFET M2 (pink line, 20 A/div), drain current of the SiC MOSFET M6 (green line, 20 A/div), and drain current of the SiC MOSFET M4 (yellow line, 20 A/div) (time base: 50 ns/div).

was observed. The steady-state current is approximately 45 A per module. With this higher current, it is possible to notice the difference in the ON-state resistances between the modules.

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Fig. 14. (a) Turn-on and (b) turn-off transient of the phase-leg test setup prototype. Measured drain current of the SiC MOSFET M8 (purple line, 20 A/div), drain current of the SiC MOSFET M2 (pink line, 20 A/div), drain current of the SiC MOSFET M6 (green line, 20 A/div), and drain current of the SiC MOSFET M4 (yellow line, 20 A/div) (time base: 50 ns/div).

Specifically, the steady-state current in module 8 is 40 A, which indicates a higher ON-state resistance than the other modules. Additionally, it is observed that the current sharing among the modules is improved compared with the previous cases. This is mainly due to the continuous operation, which increases the temperature. This makes the power modules operate in the positive-temperature-coefficient range of the ON-state resistance, which results in an autobalancing mechanism of the module currents. Fig. 14(a) shows the turn-on transient. In particular, the current waveforms of the parallel-connected power modules are shown. The turn-on process takes approximately 50 ns. During this period, the current sharing is even more uniform than in the previous results. Fig. 14(b) shows the turn-off transient. The turn-off process takes approximately 50 ns. The turn-off current sharing is also more uniform than in the previous cases. It is the hypothesis of the authors that the delay of the current in module 2 could be due to several reasons. As aforementioned, it is believed that this is due to a mismatch in the MOSFET power module characteristics, a difference in the stray inductances of the interconnections of the modules, and the differences in the Rogowski coil measurement probes.

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TABLE IV M EASUREMENT E QUIPMENT IN THE E XPERIMENTAL S ETUP

Fig. 15. Infrared camera image of the dc–dc converter during operation at 10% of the rated power. (a) Right side. (b) Left side.

TABLE III T EMPERATURE A NALYSIS D URING DC–DC C ONVERTER O PERATION

C. Thermal Analysis During the last experiment with the higher current, a thermal analysis was performed. Due to physical constraints of the prototype, two thermal camera images were recorded from each side of the prototype (see Fig. 15) in order to ensure that steadystate conditions were reached. The steady-state conditions were reached, and Fig. 15 shows infrared images with the temperatures of the modules during this operation. Table III presents the average temperature of each module. The images were analyzed using FLIR Quick Report, provided by the infrared camera. The average temperature of the modules is 38.7 ◦ C, and the maximum difference of temperature between two modules is 1.5 ◦ C. From these results, it is concluded that the loss distribution among the modules is expected to be sufficiently uniform.

2) Three-Phase System: Once the inverter operation was verified, the dc-link voltage was increased until the nominal power was reached. Measurements were conducted while the voltage was increased in small steps of 50 V on the dc side. The power was measured using a power meter with additional current transformer sensors. Table IV gives a brief description of the measurement equipment used in the setup. Fig. 16(a) shows a schematic of the experimental setup with pure inductive load, including the measurement points, whereas a photograph of the experimental setup is shown in Fig. 16(b). A photograph of the three-phase inverter is shown in Fig. 16(c). Using the aforementioned setup, experiments have been performed on the three-phase SiC inverter. The dc power supply was set up to 550 V. The pure inductive load was composed of a series connection of an air coil and laminated iron-cored inductors. A Y-connection of the three-phase inductors was used, resulting in approximately 200 μH per phase with a current rating of 800 A. Considering this, the fundamental frequency was chosen to be 350 Hz in order to reach the rated current at the rated voltage. Voltage and current waveforms were recorded at various operating points of the VSC. An oscilloscope screenshot during steady-state operation at nominal apparent power with a switching frequency of 20 kHz is shown in Fig. 17. Symmetrical phase currents with a pure inductive load and open-loop control are shown. The line-to-line voltage is also illustrated showing typical characteristics for pulsewidth modulation (PWM) as expected. Using a pure inductive load, only the power losses are transferred from the dc power supply to the system. It is the hypothesis of the authors that using a pure inductive load should result in approximately the same losses as for a motor load. When the antiparallel Schottky diodes are needed for reverse conduction, a positive gate signal is fed to the gate of the SiC MOSFETs. During reverse conduction of the SiC MOSFETs at a controlled temperature of operation of approximately TJ = 75 ◦ C, with the rated current of 45 A RMS per module, the voltage drop over the device does not exceed the knee voltage of the body diode and the antiparallel Schottky diode. Thus, almost no current is flowing through the diodes. Moreover, during the reverse conduction, the channel of the SiC MOSFETs presents approximately the same ON-state resistance as in forward


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Fig. 17. Inverter waveforms during operation at nominal power of 312 kVA and switching frequency of 20 kHz. Measured line-to-line voltage (purple line, 500 V/div), dc-link voltage (pink line, 500 V/div), phase current 1 (green line, 500 A/div), and phase current 2 (yellow line, 500 A/div) (time base: 1 ms/div).

Fig. 18. Screenshot of the power meter during operation at nominal power of 312 kVA and switching frequency of 20 kHz.

Fig. 16. (a) Schematic of the experimental setup for pure inductive load with measurement points. (b) Photograph of the setup. (c) Photograph of the inverter.

conduction. This results in approximately the same losses for the inverter independent of the power factor [52]. Power measurements were performed in both input and output points. A screenshot of the power meter screen at nominal power during steady-state conditions with a switching frequency of 20 kHz is shown in Fig. 18. Four different elements are shown in this picture. The first one corresponds to the output power/voltage/current measurement of the total three-phase system. The next two correspond to two different output phases, whereas the last one, Element 5, corresponds to the input point on the dc side. The total losses PTOTAL can be divided into the copper losses PCOPP and the iron losses PIRON , which are both coming from the inductive load, and the conduction losses PCD and

Fig. 19. Classification of the four components of the total measured losses.

the switching losses PSW , which are both coming from the SiC power modules in the inverter. Fig. 19 shows this classification of the losses.

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TABLE V O PERATION P OINTS D URING THE T EST

Based on the information presented earlier, the following power relations are obtained: PINV = PCD + PSW PLOAD = PIRON + PCOPP PINV = PTOTAL − PLOAD η = 100 ×

STOTAL − (PINV ) STOTAL

(4) (5) (6) (7)

where the addition of the iron losses PIRON and the copper losses PCOPP is the active power measured on the ac output (see first element in Fig. 18), and the total introduced losses PTOTAL is the active power measured on Element 5. Using (6) and the measured data shown in Fig. 18, the power losses of the inverter PINV caused in the power circuit of the inverter are found to be 2.29 kW at the rated power. Moreover, the converter efficiency at rated conditions is found to be approximately 99.3%, using (7). This means that the total power loss is around 0.7%, slightly lower than that estimated in Fig. 7. The authors believe that this small difference is caused by better switching performance of SiC MOSFET modules when they operate in three-phase inverter than during DPT. During three-phase continuous operation, the power modules junction temperature rises up to approximately 75 ◦ C. Around this temperature, the ON-state resistance is within the positive temperature coefficient range, and therefore, a balancing of the current sharing among the modules will occur. The positive temperature coefficient works as an autobalancing mechanism of the currents. Finally, Table V shows the different operation points that were tested at a switching frequency of 20 kHz. The last point tested is the nominal power rating with an efficiency of 99.3% at approximately 325 kVA of apparent power. In addition, the overall efficiency is above 99% in the whole power range, therefore achieving the goal of the project.

Special considerations were taken into account regarding the parasitic components of the setup during its construction. As aforementioned in Section II, the positive and negative bus bars placed on top of each other minimize the stray inductances introduced by them. It is also believed that, by ensuring a low inductive setup and selecting lower rated power modules, a more uniform spread of the currents and fast switching could be achieved, which directly affect the switching losses and, therefore, the efficiency. Additionally, the proper selection of the power module is important. The power modules used in this paper have a more similar path for the gate current, in the upper and lower switch positions, than other modules, such as the one selected in [33]. The first set of measurements was electrical measurements performed with a single phase-leg prototype connected in a dc–dc converter configuration. More uniform distributions of the currents were recorded at higher rated power. It is believed that the positive temperature coefficient of the ON-state resistances of the MOSFETs contributes toward a more uniform loss distribution under steady-state operation of the modules in a converter. Moreover, uniform distribution of the temperatures of the modules during steady-state operation was recorded. This indicates that a uniform distribution of the losses during steadystate operation of the inverter was expected. Finally, the three-phase prototype was tested at the rated apparent power with a pure inductive load. A total of 2.29 kW of losses was calculated using the reading from the power meter. Thus, the total efficiency was 99.3%. Performing an error propagation calculation considering the results from Fig. 18 and the accuracy of the power meter, which is 0.1%, as cited in Table IV, it was found that the total losses of the inverter are 2.29 ± 0.0125 kW. This implies that the efficiency of the converter is 99.3 ± 0.15 %. During normal operation at 20 kHz of switching frequency and when a typical space-vector PWM signal was provided to the gates, the drivers approximately consume 360 W. Another heat source was the dc supply (230 V AC/24 V DC) mounted on the left side of the housing. The amount of 360 W (measured at the input of common power supply, 60 W per switch position) is caused by the distributed printed circuit boards and the high number of subdrivers employed. However, an optimal design of the gate-drive circuits might result in lower power consumption. Finally, for this design, 360 W is added to the semiconductor power loss, resulting in total power losses of 2.65 kW. This means that, even if the possible error is the worst one, efficiency, including driving power, is still above 99% or more likely close to 99.19%. VI. C ONCLUSION

V. D ISCUSSION OF THE R ESULTS The goal of this project was to build and experimentally validate a 312-kVA inverter with parallel-connected SiC MOSFET power modules. Our goal was an efficiency exceeding 99%. Thus, a significant part of the laboratory work was concentrated on handling the massive parallel connection in the most adequate form, i.e., current distribution, and therefore loss distribution, among the power modules.

In this paper, a 312-kVA three-phase SiC inverter for motordrive application with high efficiency has been designed, built, and experimentally evaluated. Various electrical measurements were performed at different power levels in order to verify the high efficiency. From measurements, the total losses of the main circuit were found to be 2.29 ± 0.0125 kW at 312 kVA of power, which corresponds to an efficiency of 99.3 ± 0.15 %. The key to reach such high efficiencies is a combination of a


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Juan Colmenares (S’12) was born in Maracaibo, Venezuela, in 1989. He received the Diploma degree in electronic engineering from the Universidad Simon Bolivar, Caracas, Venezuela, in 2012. He is currently working toward the Ph.D. degree in the Department of Electrical Energy Conversion, KTH Royal Institute of Technology, Stockholm, Sweden. In 2010, he spent a year as an Exchange Student at KTH Royal Institute of Technology, conducting research on his diploma thesis about control of modular multilevel converters. His research interests include gate driver design for SiC power modules and SiC power converters.

Dimosthenis Peftitsis (S’03–M’13) was born in Kavala, Greece, in 1985. He received the Diploma degree in electrical and computer engineering from Democritus University of Thrace, Xanthi, Greece, in 2008 and the Ph.D. degree from KTH Royal Institute of Technology, Stockholm, Sweden, in 2013. In 2008, he was with ABB Corporate Research, Västerås, Sweden, for six months, where he was involved in working on his diploma thesis. In 2013–2014, he was a Postdoctoral Researcher of SiC converters with the Department of Electrical Energy Conversion, KTH Royal Institute of Technology. He is currently with the Laboratory for High Power Electronic Systems, Swiss Federal Institute of Technology (ETH), Zurich, Switzerland, working on dc breakers for multiterminal HVDC systems and power electronics converters for energy-storage systems. His current research interests include gate and base driver design for SiC junction field-effect transistors and bipolar junction transistors, as well as dc-breaker concepts for HVDC systems.

Jacek Rabkowski (M’10–SM’14) received the M.Sc. and Ph.D. degrees in electrical engineering from Warsaw University of Technology, Warsaw, Poland, in 2000 and 2005, respectively. In 2004, he joined the Institute of Control and Industrial Electronics, Warsaw University of Technology, where he is currently a Professor of power electronics. During 2010–2013, he was also with the Electrical Energy Conversion Laboratory, KTH Royal Institute of Technology, Stockholm, Sweden. His research interests include novel topologies of power converters and pulsewidth modulation techniques, particularly drive units and converters with wide band-gap devices. Dr. Rabkowski served as Chairman of the Joint Industrial Electronics Society/Power Electronics Society Chapter in the framework of the IEEE Poland Section in 2012–2015.

Diane-Perle Sadik (S’12) was born in Lausanne, Switzerland, in 1988. She received the M.Sc. degree in electrical engineering from the Swiss Federal Institute of Technology in Lausanne (EPFL), Lausanne, in 2012. She is currently working toward the Ph.D. degree in the Department of Electrical Energy Conversion, KTH Royal Institute of Technology, Stockholm, Sweden. Her research interests include converters with SiC devices and protection and reliability circuits for SiC devices.

Georg Tolstoy (S’09) was born in Gävle, Sweden, in 1981. He received the Master’s degree in engineering physics from Uppsala University, Uppsala, Sweden, in 2008 and the Ph.D. degree in power electronics from KTH Royal Institute of Technology, Stockholm, Sweden, in 2015. He is currently a Researcher with the Department of Electrical Energy Conversion, KTH Royal Institute of Technology. His research interests include gate and base drivers for SiC devices and all types of electrical converters, with an extra interest in resonant converters.

Hans-Peter Nee (S’91–M’96–SM’04) was born in Västerås, Sweden, in 1963. He received the M.Sc., Licentiate, and Ph.D. degrees from KTH Royal Institute of Technology, Stockholm, Sweden, in 1987, 1992, and 1996, respectively, all in electrical engineering. In 1999, he became a Professor of power electronics with KTH Royal Institute of Technology, where he is currently the Head of the Electrical Energy Conversion Laboratory. His current research interests include power electronic converters, semiconductor components, and control aspects of utility applications, such as flexible ac transmission systems and high-voltage dc transmissions, and variable-speed drives. Dr. Nee is a Member of the European Power Electronics and Drives Association, involved with the Executive Council and the International Scientific Committee. He is an Associate Editor of the IEEE T RANSACTIONS ON P OWER E LECTRONICS . He was on the Board of the IEEE Sweden Section for several years, serving as its Chairman during 2002–2003. He has been a recipient of several awards for his research.