F. Maloberti: "High-performance data converters: Trends, process technologies and design challenges"; IEEE Asia Pacific Conf. on Circuits and Systems, APCCAS 2008, Macao, November 30-‐December 3, 2008, pp. 12-‐16. ©20xx IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
High-Performance Data Converters: Trends, Process Technologies and Design Challenges F. Maloberti Department of Electronics, University of Pavia, Italy Email:
[email protected] and a reduction of a factor two of the transistor line-width every 18 months. However, the sector that derived the major advantages is the digital processing and digital storing of data. The analog area, by contrast, suffered by various drawbacks that can not be fully compensated by the benefits of technology shrinking. Therefore, analog designers preferred using mature technology and to move to thinner line-width only when economical reasons or system integration needs forced to do that. Nevertheless, even with a delay, analog circuits and data converters followed the evolution of process technology. The technology used by an electronic system mainly depends on its required specifications: for very high speed and non demanding analog performance nanometer technologies are beneficial. For example, a current steering DAC only requires a reasonable matching between current sources whose output resistance must be large; since the key feature of the DAC is the speed of operation, for resolutions in the 10 − −14 bit range, the use of the most advanced technologies benefits the conversion rate. It is reasonable to predict that the data conversion rate for medium resolution will increase by almost two decades in approximately 10 years from now. On the contrary, data converters for sensors, that must ensure resolutions of 18bit or more, still prefer mature technologies and benefit from the precision qualities. Recently, the trend is to incorporate data converters with large digital sections, but the designers compliance is at significantly different speed for dissimilar applications and markets. The recent history of data converters can be dated back to 90s when the major data converter applications were instrumentation, measurement, industrial process control, medical imaging, audio and video. At that time, communication field was in an initial phase of development and all the apparatuses were plugged without low power requirements. Later, the communication market became a big driving force for low-cost, medium-power, high-performance data converters, that were used in modems, and wireless infrastructure (base stations). Even for those applications, low power was not a pressing request, but shortly later the cell phone handset and other portable battery-powered applications emphasised the need of lower power and singlesupply voltages. Therefore, the use of lower voltage CMOS processes was a proper choice because the reduced supply voltages allowed higher speed. However, the lower signal range and the almost unchanged headroom made the designs more sensitive to noise. Nevertheless, for medium resolution and wide
Abstract— High-performance electronic systems use more and more use high-performance data converters for improving and shaping the architecture and opening new application perspectives. The current and future trend depends on old and new factors that include global economy, technology evolution and marketing. All these elements are driving forces and create new challenges for the designer that answer the requests of new applications by exploiting the advantages and limiting the drawbacks due to the amazing growth of process technologies.
I. I NTRODUCTION Data converters are essential gateways leading an analog signal, which features many situations encountered in the realworld, to a digital format suitable for signal processing, data transmission, computing and control; or, the other way around, data convertes transform a transmitted signal, a stored data, or the product of digital processing into a real-world signal for control, actuation, or further processing in the analog domain. Data converters are increasingly important for system architectures [1], [2], [3]. The strategy of many system designers is to move processing as much as possible to digital, as they rely on data converters able to provide high speed and large resolution. Moreover, the necessities of high-performance are often accompanied by the need of low power consumption, or, more frequently, the low-power feature is itself a key performance and as a result speed and resolution become trade-off elements together with silicon area and cost. The design [4] and fabrication of data converters follow (or, in some cases, must follow) the evolution of process technologies, but also exploit other advancements like the ones of special technologies and packaging. Thanks to them, in some critical situations, ultra-thin line-width technologies with very low supply voltages can be avoided and optimum performance obtained. This paper considers first previous trends and the resulting applications. Then, it derives the most important features of the recent high-performance data converters. The process technology and its advantages and limits are examined for identifying the challenges that the designer faces. Finally, emerging design directions are discussed. II. H ISTORY AND T REND Two factors mainly drove the data converter development: technology and applications. It is well known that technology evolved with the incredible pace predicted by the so-called Moore Law [5], that foresees a doubling of the circuit complexity
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chain for permitting different processing required by various architectures. The same concept is extended to other needs. Therefore, for data converters used in software defined systems, wide bandwidth is essential. The required number of bit depends on the standard and the current trend is to limit the resolution at the expenses of a relatively larger signal band. C. Portable and Autonomous Systems
Fig. 1.
An increasing number of electronic systems become portable and nomadic. For these applications the main concern is to have a long battery life and, more frequently, to harvest energy and to operate without external refueling. Therefore, low power is very important and, often, some of the above mentioned performance, are constrained for an higher power effectiveness which is quantified by the figure of merit (FoM), that links the power, Ptot , the effective number of bit, ENoB and the signal band, fB , defined as
Evolution of the first generation packages.
bandwidth data conversions, the use of the same technology that is also used by digital processors became the general trend. Also, the utilization of the sigma delta technique, that trades speed with accuracy, permits to obtain an increasing signal band with medium resolution (60 − 75 dB). The use of the same technology in high resolution systems (80 dB or more) is problematic and rarely pursued: instead, it is more viable to use the optimum technology (like the BiCMOS or the SiGe ones) for the analog part and realize a multiple chip system. The packaging trend facilitates the approach. Packaging evolved from the first generation (Fig. 1) that started from the traditional DIP of the early times to smaller and smaller footprints that enable the surface mount packages which are suitable for high-volume automatic mass-assembly manufacturing techniques. The modern packages include both leaded types and non-leaded types such as the laminated substrate package or ball grid array (BGA). More recently 3D packages (stack dice, stack package and system in package, SiP) were introduced.
F oM =
Ptot . EN 2 oB 2fB
(1)
Modern systems demand for a data converter capable to obtain FoM in the ten of fJ-conv-level for signal band in the hundreds of KHz to MHz range [8], [9]. IV. P ROCESS T ECHNOLOGY The IC complexity increases continuously [10] thanks to the continued improvements in optical projection lithography by about 30% every two years. Process technology is now in subwavelength mode where extreme Ultra-Violet (EUV) lithography obtains the patterning of lines below 30 nm dimensions. At the same time, the minimum feature size, oxide thickness, supply voltage and transistor thresholds diminish for controlling various short channel effects like the VT h roll-off or the Drain-Induced Barrier Lowering (DIBL). One of the major problems of ultra-thin technology is gate leakage caused by direct band-to-band tunneling. Moreover, highly energetic carries generate electron-hole pairs leading to charges trapped in the oxide, causing a steadily increase in the tunneling current until, in the end, the oxide breakdown occurs. Moreover, the threshold voltage steadily degrades. Another important limit comes from the reduction of the supply voltage that, on one hand, lowers the power dissipation, but, on the other hand, degrades the signal-to-noise ratio (SNR) of analog circuits. Moreover, low thresholds enhance the leakage and this dissolves signals stored on capacitors. A possible (expensive) remedy, is using dual threshold technologies when the high threshold devices have low leakage. The above points indicate that the push toward deep submicron technology is not very attractive for analog functions that, when implemented alone or with a small digital part, are more conveniently obtained with analog technologies whose line-width is 2–3 times larger than digital applications. The challenge is for large digital systems integrated in deep submicron technologies with few analog functions (mainly data converters).
III. C ONVERTER A PPLICATIONS Almost all the systems that process signals of the real word use data converters. The ones that require high-performance can be classified into three categories: high-precision systems, software defined systems, and portable or autonomous systems. The features and key performances are resumed below. A. High-Precision Systems Applications in the field of open and closed loop industrial process control, robotics, medical instrumentation, test and data acquisition systems need ADCs and DACs with high accuracy (16-bit or more). For those applications the speed is not important as the signal band is often in the range of tens of kHz [6]; by contrast, it is essential ensuring clean supply and reference voltages, an excellent component matching and a good driving capability. B. Software De ned Systems The most important application of this category is the software defined radio [7] which is the current trend for communication systems. The data converters are the endings of the processing
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100
Output Resistance
6
10
Supply Voltage [V]
Output resistance [ Ω]
Si-G 5
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eB
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iCM
BiC
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OS
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fT (GHz)
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Fig. 3.
Supply voltage versus the technology unity gain frequency.
Output resistance decrease for low channel length.
not much beneficial in moving non-dominant poles at high frequencies.
V. C ONSEQUENCES OF S CALING ON A NALOG
D. Matching Accuracy
In the next 5–10 years the transistor line-width will become 35–22 nm with 1–1.5 nm equivalent oxide thickness. The VDD , limited by reliability consideration, will drop below 1 V [2]. Therefore, especially for analog, it will be important using oxides with high field strength for higher supply voltages. In addition to the low supply voltage other factors limit the analog performance.
The offset of any analog circuit and the static accuracy of data converters depend on the matching between nominally identical devices. The stochastic nature of physical and chemical fabrication steps causes a random time-independent difference between equally designed elements. The stochastic mismatch between corresponding parameters p of close elements is A2p + Sp2 d2 (3) WL where Ap and Sp are matching parameters at unity area and unity distance, d is the distance between the centroids of the two identically designed elements. Typically, for preserving matching, the area of transistors or capacitors must diminish as a function of the shrinking factor, while the area of resistors should diminishes less because of the perimetrical term.
A. Transconductance
σ(∆p)2 =
With very short channels the carrier velocity quickly reaches the saturation limit, the transconductance saturates and becomes independent on gate length or bias, as approximated by Wef f Cox vsat . (2) 2 A low transconductance is not desirable for analog design: for obtaining high gain it is necessary to use wide transistors thus augmenting parasitic capacitances and, in turn, reducing bandwidth and slew rate. B. Output Resistance gm =
E. Signal Swing The shrink of processes reduces the supply voltage. Since it is necessary to ensure a suitable headroom for keeping transistors in saturation, the minimum swing of signals cannot be close to VDD or ground by more than about 100 mV . Therefore, the trend shown in Fig. 3 predicting CMOS supply voltages well below 1 V in the next few years conceives signal swing as small as few hundred mV. More expensive technologies like the BiCMOS can become competitive for high precision data converters. Low voltage is also problematic for driving CMOS switches as the on-resistance can become very high or at the limit the switch does not close at all in some interval of the input amplitude.
Even the output resistance is affected by shrinking and quickly decreases when the gate lengths becomes lower than 0.1µm (much faster than L, Fig. 2). The reduction of the output resistance and the saturation of gm affect the intrinsic gain: with a given transconductance limit, when the output resistance r0 becomes 1/gm , the intrinsic gain gm r0 is unity and the device cannot be used anymore for amplification purposes. Obtainig high gain is more and more problematic as using cascode structures with stack of transistors reduces the signal swing.
VI. D ESIGN C HALLENGES
C. Diffusion and Gate Capacitances
The changing features of process technologies challenge the design of high-performance data-converters especially with high accuracy. For high-precision convertes, the main difficulties come from • the design and the integrity of reference voltages; • the rejection of interferences coming from the digital sections.
Scaling makes the gate oxide thinner; therefore, the specific capacitance Cox increases as function of the shrinking factor. Since the gate area can be made smaller, parasitics remain constant or diminish as the process shrinks. However, interconnections use thick and close metals whose parasitics may become dominant. Therefore, globally, modern technologies are
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For high speed [11][12] the technology trend is favourable, but the velocity saturation in very short channel that limits the transconductance gain imposes higher current in amplifiers. The reduction of the supply voltage also diminishes the reference voltage of the converter and, in turn, scales the amplitude of the quantization steps. Another challenge to high speed conversion comes from the clock jitter. As known a gaussian uncertainity in the clock δji t gives rise to a noise power
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(2πfin Ain )2 = δji t2 (4) 2 where Ain is the amplitude of an input sine wave at fin . Using the maximum amplitude VRef /2 and assuming that the jitter power equals to the one of the quantization (loss of 0.5-bit), it is possible to obtain the diagram of Fig. 4 that gives the required jitter versus the resolution at different input frequencies. Notice that for resolutions in the 10-bit range requires clock jitter of few hundred of psec for signals below 200 M Hz which is difficult to obtain. For higher frequencies it is necessary to ensure clock jitters in the tens of psec range. Therefore, the design of high-speed converters, albeit facilitated by the technology, engages the designer for • sustaining the SNR; • designing high-gain OTAs; • reducing the limits caused by the CMOS switches, • properly handling the clock for a minimum jitter degradation. The low-power data converters use relatively low conversion frequency and mature technologies [8], [9]. When the sampling rate increases and thin line-width technologies are used, the power effectiveness significantly decreases. There is a combination of negative effects that includes the reduced supply voltage that imposes bigger sampling capacitors, the augmented bias current necessary to increase the transconductance gain and the short channel effects that diminish the transconductance and the dc gain effectiveness. All these factors can be accounted for in a behavioral model that gives the results as predicted in Fig. 2 vn,ji
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Fig. 5.
• • •
Clock Jitter [psec]
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Estimated power consumption of ADC versus the conversion speed.
the use of algorithms that do not need active devices; the design of wide-swing OTAs; the invention of techniques that allow using supply voltages higher than the technology limit. VII. D ESIGN D IRECTIONS
The design challenges are faced with various strategies that, in addition to what mentioned before, follow new design directions. A. New Algorithms and Architectures The need of data conversion gave rise to numerous algorithms adapted to a given technology. Moreover, many of the invented algorithms become eventually obsolete because of the technology evolution. As outlined, there are limitations in obtaining desired performance and the solution can be the attempt to obtain those performance with the evolving technology or to invent new algorithms or new architectures that fit the advantageous feature of the new processes. Since speed is one of the key advantages, methods that trade speed with other paramenters are good candidates for future developments [13–18].
1
25 MHz 50 MHz 100 MHz 200 MHz 400 MHz 800 MHz
0
#!!
5. A state-of-the-art 10 bit pipeleine converter that consumes about 5mW at 100MS/s increases the power by a factor 30 for augmenting the sampling rate by 8. The simulation gives even worse figures for higher resolutions. Therefore, we have to expect a significant reduction of the FoM for high speed, highperformance data converters. The challenges for the designer in this area are
10
10
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B. Use of Parallelism A method that helps in reducing the power consumption is the use of interleaved structures. The same can be used to improve the accuracy by averaging the results. The cost of using schemes working in parallel for processing the same input becomes negligible for the decresing cost per transistor. Therefore, new conversion methods that use a massive parallelism can become feasible in the near future [19][20].
!2
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8
9
10
11
12
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Fig. 4.
Required clock jitter at different resolutions and bandwidths.
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Fig. 6. dies.
[5] Moore, G. E., “Cramming more components onto integrated circuits”, Electronics, Vol. 38, n. 8 April 19, 1965. [6] V. Quiquempoix, P. Deval, A. Barreto, G. Bellini, J. Markus, J. Silva, and G. C. Temes, ”A low-power 22-bit incremental ADC,” IEEE Journal of Solid-State Circuits, vol. 41, pp. 1562 – 1571, 2006. [7] Walter H.W. Tuttlebee (Editor), ”Software Defined Radio: Enabling Technologies” Wiley Interscience, 2002. [8] M. D. Scott, B. E. Boser, ard K. S. J. Pister, “”An Ultralow-Energy ADC for Smart Dust”, IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1123 – 1129, 2003. [9] Agnes, A. Bonizzoni, E. Malcovati, P. Maloberti, F. “A 9.4-ENOB 1V 3.8µ W 100kS/s SAR ADC with Time-Domain Comparator”. IEEE International Solid-State Circuit Conference, ISSCC, Vol. 51 pp. 246 – 247, 2008. [10] Matsuzawa, A., “Analog IC technologies for future wireless systems”, IEICE Trans. Electron, Vol. E89-C, pp. 446 – 454, 2006. [11] Ginsburg, B.P.; Chandrakasan, A.P., “Highly Interleaved 5b 250MS/s ADC with Redundant Channels in 65nm CMOS”, IEEE International Solid-State Circuit Conference, Vol. 51 pp. 240 – 241, 2008. [12] S. Mehta, W. W. Si, H. Samavati, M. Terrovitis, M. Mack, K. Onodera, S. Jen, S. Luschas, J. Hwang, S. Mendis, D. Su, and B. Wooley, ”A 1.9GHz single-chip CMOS PHS cellphone” IEEE International Solid-State Circuits Conference, vol. XLIX, pp. 484 – 485, 2006. [13] S. K. Gupta, M. A. Inerfield, and J. Wang, ”A 1-GS/s 11-bit ADC with 55-dB SNDR, 250-mW power realized by a high bandwidth scalable timeinterleaved architecture,” IEEE Journal of Solid-State Circuits, vol. 41, pp. 2650 - 2657, 2006. [14] S. Shahramian, A. C. Carusone, and S. P. Voinigescu, ”Design methodology for a 40-Gsamples/s track and hold amplifier in 0.18-m SiGe BiCMOS technology,” IEEE Journal of Solid-State Circuits, vol. 41, pp. 2233 - 2240, 2006.
System in package with wired bonded and embedded in the substrate
C. Use of Multi-rate Solutions The present distinction between Nyquist rate and oversampled methods will become softer as the high-speed processing capability can be exploited in section of architectures for answering some special request. The resulting multi-rate architectures can obtain, for example, relaxed anti-aliasing specifications or focus on segment of the signal band. D. Digitally Assisted Analog The limitations of analog features are more and more corrected with digital techniques. Presently, digital processors support calibration algorithms for improving the matching of elements and static linearity. The approach will be extended for improving the performance of analog sections. For example, the output dynamic of analog cells can be expanded by a digitally controlled dynamic level shifting. Architectures can be digitally reconfigured for an optimum use of power and so forth[21-24].
[15] G. Manganaro, S. Kwak, and A. R. Bugeja, ”A dual 10-b 200-MSPS pipelined D/A converter with DLL-based clock synthesizer,” IEEE Journal of Solid-State Circuits, vol. 39, pp. 1829 - 1838, 2004. [16] Shen, D.-L., Lee, T.-C, “A 6-bit 800-MS/s Pipelined A/D Converter With Open-Loop Amplifiers”, IEEE Journal of Solid-State Circuits, Vol. 42 pp. 258 – 268, 2007. [17] G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holuigue, and E. Romani, ”A 20-mW 640-MHz CMOS continuous-time Σ∆ ADC with 20MHz signal bandwidth, 80-dB dynamic range and 12-bit ENOB,” IEEE Journal of Solid-State Circuits, vol. 41, pp. 2641 – 2649, 2006. [18] Mercer, D.A, “Low-Power Approaches to High-Speed Current-Steering Digital-to-Analog Converters in 0.18-mum CMOS”, IEEE Journal of SolidState Circuits, Vol. 43 pp. 1688 – 1698, 2008.Vol. 2 pp. 191 – 201, 2008. [19] Asemani, D., Oksman, J., Duhamel, P., “Subband Architecture for Hybrid Filter Bank A/D Converters”, IEEE Selected Topics in Signal Processing, Vol. 2 pp. 191 – 201, 2008. [20] Cheng-Chung Hsu, Fong-Ching Huan, Chih-Yung Shih, Chen-Chih Huang, Ying-Hsi Lin, Chao-Cheng Lee, Behzad Razavi, ”An 11b 800MS/s TimeInterleaved ADC with Digital Background Calibration”,” IEEE International Solid-State Circuits Conference, vol. XLX, pp. 464 – 465, 2007. [21] Blecker, E. B., McDonald, T. M., Erdogan, O. E, Hurst, P. J and Lewis, S. H., “Digital background calibration of an algorithmic analog-to-digital converter using a simplified queue”, IEEE Journal of Solid-State Circuits, vol. 38, pp. 1059 – 1062, 2003. [22] Chan, K. L., Zhu, J.; Galton, I., “Dynamic Element Matching to Prevent Nonlinear Distortion From Pulse-Shape Mismatches in High-Resolution DACs”, IEEE Journal of Solid-State Circuits, Vol. 43 pp. 2067 – 3078, 2008. [23] M. Daito, H. Matsui, M. Ueda, and K. Iizuka, ”A 14-bit 20-MS/s pipelined ADC with digital distortion calibration,” IEEE Journal of SolidState Circuits, vol. 41, pp. 2417 – 2423, 2006. [24] K. Iizuka, H. Matsui, M. Ueda, and M. Daito, ”A 14-bit digitally selfcalibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40 MS/s,” IEEE Journal of Solid-State Circuits, vol. 41, pp. 883 – 890, 2006. [25] H. Reichl, A. Ostmann, R. Wieland, and P. Ramm, ”The third dimension in microelectronics packaging,” Proc. 14th Eur. Microelectronics Packaging Conf. Exhibition, p. 1 – 4, 2003.
VIII. C ONCLUSIONS The future of data conversion is full of expectations and challenges. Modern systems, either on chip or in package, possibly using advanced packaging techniques [25] like the one illustrated in Fig. 6 that enables a exible system partitioning and 3D integration, will base their architecture and performance on the data converter that they have on board. The collaboration of system architects and analog circuit designers will be the driving force of future research and development. ACKNOWLEDGMENT The author would like to thank FIRB, Italian National Program #RBAP06L4S5 for partial economical support. R EFERENCES [1] Counts l., “Analog and Mixed-Signal Innovation: The Process- CircuitSystem-Application Interaction”. IEEE International Solid-State Circuit Conference, ISSCC, Vol. 50 pp. 26 – 29. 2007 [2] van Roermund, A.H.M., ”Smart, exible, and future-proof data converters”, 18th European Conference on Circuit Theory and Design, ECCTD, pp. 308 – 319, 2007. [3] Robertson D., ”The Past, Present, and Future of Data Converters and Mixed Signal ICs: a Universal Model” . IEEE Symposium on VLSI Circuits, pp. 1 – 4, 2006. [4] F. Maloberti, “Data Converters”, Springer Ed., Dordrecht, The Netherland, 2007.
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