High-Speed Germanium-on-SOI Lateral PIN Photodiodes

IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 16, NO. 11, NOVEMBER 2004

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High-Speed Germanium-on-SOI Lateral PIN Photodiodes G. Dehlinger, S. J. Koester, Senior Member, IEEE, J. D. Schaub, Member, IEEE, J. O. Chu, Q. C. Ouyang, Member, IEEE, and A. Grill

Abstract—We report the fabrication and characterization of high-speed germanium on silicon-on-insulator lateral PIN pho10- m todetectors. At an incident wavelength of 850 nm, 10 detectors with finger spacing of 0.4 m (0.6 m) produced a 3-dB bandwidth of 29 GHz (27 GHz) at a bias voltage of 1 V. The detectors with = 0 6 m had external quantum efficiency of 34% at 850 nm and 46% at 900 nm and dark current of 0.02 A at 1-V bias. Index Terms—Germanium (Ge), optoelectronic devices, photodetectors, silicon-on-insulator (SOI) technology.

I. INTRODUCTION

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HE ABILITY of germanium (Ge) to absorb in the near infrared makes it an interesting candidate for high-speed photodetector applications, since it holds the prospect for integration with mainstream Si complementary metal–oxide–semiconductor technology. Though Ge photodetectors have previously been investigated for applications at wavelengths of 1.3 and 1.55 m [1]–[3], virtually no attempts have been reported so far to use these devices at nm. This wavelength is of interest for short range highly parallel interconnects due to the availability of inexpensive and efficient GaAs vertical-cavity surface-emitting lasers. Ge is ideal for use at 850 nm, because is only a few hundred nanometers the absorption length [4], opening the possibility for extremely fast detectors due to the thin absorbing layer needed. However, operation at 850 nm requires isolation from the underlying Si substrate since Si is a m), and slow carweak absorber at this wavelength ( rier drift–diffusion from the Si substrate can lead to bandwidth degradation [5]. In this letter, we describe the characterization of lateral PIN photodetectors that utilize Ge films deposited on ultrathin silicon-on-insulator (SOI) substrates. These devices have bandwidths as high as 29 GHz, high external quantum efficiencies, and operate at extremely low bias voltages. II. SUBSTRATE PREPARATION The layer structure was grown by ultrahigh vacuum chemical vapor deposition directly on an ultrathin SOI substrate with initial SOI thickness of 15 nm and buried oxide layer thickness of Manuscript received June 7, 2004; revised July 5, 2004. G. Dehlinger is with Infineon Technologie, 9500 Villach, Austria (e-mail: [email protected]). S. J. Koester, J. D. Schaub, J. O. Chu, Q. C. Ouyang, and A. Grill are with the IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 USA (e-mail: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]). Digital Object Identifier 10.1109/LPT.2004.835631

Fig. 1. Schematic cross section of the lateral PIN design. After annealing, the boundary between the Si and Ge layers blurs considerably.

140 nm. After the growth of a thin Si buffer layer ( 30 nm), the temperature was lowered to 350 C and a 50-nm-thick Ge seed layer was grown in order to suppress three-dimensional growth [6], [7]. Next, the temperature was increased to 600 C nm, and the Ge was grown to a total thickness of as determined by cross-sectional scanning electron microscopy (SEM). The layer structure then underwent thermal cyclic annealing (TCA) to reduce the density of threading dislocations [8]. For this step, the temperature was ramped ten times between 780 C and 900 C and held at each temperature for 6 min. The threading dislocation density after the TCA step was found to cm , as determined by transmission electron mibe croscopy. We have previously found that for Ge layers grown on bulk Si, the TCA treatment leads to substantial diffusion of the underlying Si into the Ge layer [5]. The use of ultrathin SOI minimizes this effect by limiting the amount of Si available for interdiffusion. Hall measurements indicated that, after TCA, the Ge-on-SOI layers were p-type with a mobility and carrier dencm , respectively. sity of 1200 cm Vs and III. PHOTODETECTOR FABRICATION A schematic cross-sectional diagram of the device structure is shown in Fig. 1. A planar, lateral PIN geometry was chosen to minimize parasitic capacitance and maximize the bandwidth. The devices were fabricated by first defining square mesas ranging in size from 10 10 m to 30 30 m by optical lithography and combined wet and dry etching down to the buried oxide. In the same step, sputtered oxide was deposited to create self-aligned isolation regions. The oxide serves to insulate the contact metal from the defect-rich sidewalls of the Ge mesa, decrease capacitive coupling to the substrate, and reduce the step height at the mesa edge. Electron-beam lithography was used for the remaining patterning steps. For

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IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 16, NO. 11, NOVEMBER 2004

Fig. 2. I –V characteristics of 10 S of 0.4 and 0.6 m.

2 10-m

Fig. 3. Calculated and measured external quantum efficiency. The measured data was obtained on a 30 30-m detector with a finger spacing S of 1.3 m. The model accounts for the shadowing factor (0.87) of the interdigitated fingers.

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photodiodes with finger spacings

the n-type contacts, resist openings were defined and used as a cm mask for implantation of As with a dose of and an energy of 15 keV. Next, resist openings were created was implanted with a dose for the p-type contacts, and cm at 5 keV. After deposition of a sacrificial of oxide layer to prevent dopant outdiffusion, the implants were annealed at 700 C for 3 s, and then the oxide layer removed. Finally, contact fingers were defined by patterning resist openings and then evaporating and lifting off Ti–Al metal with total ranged from thickness of 180 nm. The electrode spacing 0.3 to 1.3 m, while the implant width was 0.3 m. In all cases, the metal contact fingers were contained within the implant boundaries, with clearance of 0.05 m on either side. No antireflection coating was used. IV. RESULTS Fig. 2 shows the current–voltage ( – ) characteristics of and m. At a bias 10 10- m devices with m had a dark current of 1 V, the device with of 0.08 A, while the device with m had A. Taking into account the smaller electrode spacings of our devices, these values are comparable to results in the literature for Ge PIN diodes [2], [3]. The photocurrent m device due to increased was slightly lower for the finger shadowing. Fig. 3 shows the calculated and measured 30- m quantum efficiency versus wavelength for a 30 device with finger spacing of 1.3 m, where the calculated response has been corrected for the electrode shadowing factor m). The model is based on the transfer ma(0.87 for trix method for calculating the optical properties of thin films [9]. The refractive index data from [4] was used for the model. We obtained excellent agreement between the experimental data and the model using a Ge layer thickness of 392 nm, which is close to the thickness measured by SEM. The quantum nm, which is near an absorption efficiency was 38% at minimum. The responsivity could be increased further by adjusting the buried SiO and Ge layer thicknesses. However, because of the strong absorption at short wavelengths, precise tuning is not absolutely necessary to achieve acceptable responsivity, in contrast to Si resonant cavity detectors [10]. The

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Fig. 4. Impulse response of a 10 10-m device with finger spacing of 0.4 m at a bias of 2 V. Inset: Fourier transform of impulse response for same device showing 3- and 6-dB bandwidths. The responses of the probe, cable, and bias-tee have been de-embedded from the shown response.

0

0

0

peak efficiency was 52% at nm. Devices with smaller finger spacing had lower responsivity in good agreement with expectations based upon the calculated shadowing factor of the metal electrodes. The measured efficiency decreases to 3.4% at 1300 nm, and goes nearly to zero at wavelengths longer than about 1360 nm. The discrepancy between the measured data and the model at longer wavelengths is consistent with an increase in the direct transition energy of 0.1 eV, which can be explained by diffusion of Si into the Ge, creating a SiGe layer with average Si content of 5% [11]. Impulse response measurements were performed at a wavelength of 850 nm using a mode-locked Ti–sapphire laser, highspeed electrical probe, bias tee, and sampling oscilloscope. The m impulse response of a 10 10- m device with is shown in Fig. 4. The response, measured at a bias of 2 V, consists of a single sharp peak with a full-width at half-maximum of only 14.9 ps. No low-frequency tail is observed since electron-hole pairs generated in the Si substrate cannot reach the electrodes and simply recombine. We calculated the Fourier transform of the impulse response and de-embedded effects of the bias tee, cable, and probe. The resulting frequency response

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because it allows photoreceivers to operate on a single supply. The high performance at low bias also allows the devices to operate in a regime where the dark current is low. However, the dark current most certainly would need to be decreased for useful operation at higher bias voltages. The degree to which the dislocations affect the dark current and device reliability also requires further investigation. Optimization of the device design could include optimization of the Ge or SiO thickness as well as the addition of an antireflection coating. The combination of low voltage, high speed, and integration could allow Ge-on-SOI photodetectors to be an enabling technology for dense highly parallel on-chip optical interconnects. Fig. 5. Bandwidth versus bias voltage for 10 spacings S ranging from 0.4 to 1.0 m.

2 10-m

detectors with finger

is shown in the inset of Fig. 4 and indicates that the 3-dB ( 6 dB) bandwidth is over 29 GHz (36 GHz). The 10 10- m devices with and m produced 3-dB bandV. Pulsewidths of 27, 23, and 19 GHz, respectively, at response measurements were also performed on 20 20- m and 30 30- m devices, and it was found that the bandwidth decreased with increasing device area due to increased resistance–capacitance delay. This suggests that further improvement could be obtained by increasing the thickness of the metal fingers to reduce series resistance, and optimizing the finger implant and annealing conditions to reduce the device capacitance. Finally, the bias dependence of the bandwidth for different electrode spacings is shown in Fig. 5. The figure shows that the bandwidth saturates at lower voltages with decreasing finger m, the bandwidth satuspacing. For instance, when m the bandwidth saturates rates around 4 V, while at near 1 V. Even at , the latter device had a 3-dB bandm had the width of 25 GHz. Overall, devices with best performance, combining a 3-dB bandwidth of 29 GHz at V, with a peak efficiency value of 46% to produce a bandwidth-efficiency product of 13.2 GHz. To our knowledge, this is the highest bandwidth-efficiency product ever reported for a silicon-based photodetector. V. CONCLUSION We have fabricated and characterized Ge photodetectors grown directly on thin SOI substrates. The detectors feature thin ( 400 nm) absorption regions and small finger spacings, which enable 29-GHz operation while maintaining peak quantum efficiencies as high as 46%. The extremely low voltage operation is a distinct advantage over existing detectors [12],

ACKNOWLEDGMENT The authors would like to acknowledge M. J. Rooks, R. A. Carruthers, J. A. Ott, S. McNab, and P. A. Saunders for technical support. REFERENCES [1] S. B. Samavedam, M. T. Currie, T. A. Langdo, and E. A. Fitzgerald, “High-quality germanium photodiodes integrated on silicon substrates using optimized relaxed buffers,” Appl. Phys. Lett., vol. 73, no. 15, pp. 2125–2127, Oct. 1998. [2] S. Fama, L. Colace, G. Masini, G. Assanto, and H.-C. Luan, “High performance germanium-on-silicon detectors for optical communications,” Appl. Phys. Lett., vol. 81, no. 4, pp. 586–588, July 2002. [3] J. Oh, S. Csutak, and J. C. Campbell, “High-speed interdigitated Ge PIN photodetectors,” IEEE Photon. Technol. Lett., vol. 14, pp. 369–371, Mar. 2002. [4] E. D. Palik, Handbook of Optical Constants of Solids II. Boston, MA: Academic, 1991. [5] G. Dehlinger, J. D. Schaub, J. O. Chu, S. J. Koester, Q. C. Ouyang, and A. Grill, “High speed lateral PIN germanium-on-silicon photodetectors,” presented at the 1st Int. SiGe Technology and Device Meeting, Nagoya, Japan, Jan. 15–17, 2003. [6] B. Cunningham, J. O. Chu, and S. Akbar, “Heteroepitaxial growth of Ge on (100) Si by ultrahigh vacuum, chemical vapor deposition,” Appl. Phys. Lett., vol. 59, no. 27, pp. 3574–3576, Dec. 1991. [7] L. Colace, M. Gianlorenzo, and A. Gaetano, “Ge-on-Si approaches to the detection of near-infrared light,” IEEE J. Quantum Electron., vol. 35, pp. 1843–1852, Dec. 1999. [8] H.-C. Luan et al., “High-quality Ge epilayers on Si with low threadingdislocation densities,” Appl. Phys. Lett., vol. 75, no. 19, pp. 2909–2911, Nov. 1999. [9] E. Hecht and A. Zajac, Optics. Reading, MA: Addison-Wesley, 1974, ch. 6. [10] J. D. Schaub, R. Li, C. L. Schow, J. C. Campbell, G. W. Neudeck, and J. Denton, “Resonant-cavity-enhanced high-speed Si photodiode grown by epitaxial lateral overgrowth,” IEEE Photon. Technol. Lett., vol. 11, pp. 1647–1649, Dec. 1999. [11] M. V. Fischetti and S. E. Laux, “Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys,” J. Appl. Phys., vol. 80, no. 4, pp. 2234–2252, Aug. 1996. [12] M. Yang et al., “A high-speed, high-sensitivity silicon lateral trench photodetector,” IEEE Electron Device Lett., vol. 23, pp. 395–397, July 2002.