Highly Reliable, Backside Emissivity Independent Cobalt Silicide Process Using a. Susceptor-Based Low Pressure Rapid Thermal Processing System. Woo Sik ...
Jpn. J. Appl. Phys. Vol. 37 (1998) pp. L 1221–L 1223 Part 2, No. 10B, 15 October 1998 c °1998 Publication Board, Japanese Journal of Applied Physics
Highly Reliable, Backside Emissivity Independent Cobalt Silicide Process Using a Susceptor-Based Low Pressure Rapid Thermal Processing System Woo Sik YOO, Ashur J. ATANOS and David M. W HITWORTH Mattson Technology, Inc., 3550 West Warren Avenue, Fremont, CA 94538, USA (Received August 11, 1998; accepted for publication September 9, 1998)
Very thin cobalt silicide formation and annealing processes were investigated as a function of process temperature (350– 700◦ C) and Co film thickness using a susceptor-based low pressure rapid thermal processing (RTP) system. TiN capped thin Co films were investigated. Highly reliable, backside emissivity independent, low resistance, production worthy shallow silicide contact formation process has been demonstrated. Both a wide process window and an excellent sheet resistance uniformity have been demonstrated in cobalt silicide process integration steps. The net added non-uniformity of typical TiN capped 10 nm thick cobalt films was less than 0.5%. KEYWORDS: rapid thermal processing (RTP), susceptor-based RTP, cobalt silicide, backside emissivity, thermal budget, sheet resistance, uniformity, repeatability, throughput
Cobalt silicide is the most attractive material for subhalf micron technology because of its low resistivity (600◦ C, respectively. Very wide process windows for both 1st and 2nd step cobalt silicide anneal were characterized. Sheet resistance and uniformity change were tracked at each step in the cobalt silicide process integration. We selected 500◦ C and 660◦ C as process temperatures for the 1st step and 2nd step cobalt silicide process conditions, respectively. The sheet resistance and uniformity data were obtained on the as received samples, after the 1st step anneal (500◦ C, 90 s) with TiN cap in place, after TiN removal by wet etch and after the 2nd step anneal (660◦ C, 90 s). Figure 2 shows the average sheet resistance and non-uniformity of eight samples after each of the process steps. The average sheet resistance changed from 20.50 to 51.24 Ä/sq. after the 1st step anneal. By removing TiN cap layers in wet etchant, the average sheet resistance became 89.30 Ä/sq. A very low average sheet resistance of 5.73 Ä/sq. was obtained after the 2nd step anneal. An excellent average sheet resistance uniformity of 1.18% was achieved after the final step (2nd step anneal) in cobalt silicide integration. The NANU throughout the process steps was −0.87% (i.e. the sheet resistance uniformity was improved during the process steps). For process repeatability test, we performed a 500 wafer marathon run at the 2nd step anneal condition (660◦ C, 90 s).
32 reacted cobalt silicide wafers were used in the test after TiN cap removal. To investigate the accumulation effect of air exposure after wet etching of TiN cap layer, the 32 reacted cobalt silicide wafers were placed in 4 different blocks (8 wafers in each block). The test was started 6 hours after the TiN cap removal. There is a two hour air exposure time difference between blocks. In other word, the 8 cobalt silicide wafers in the second block have 8 hours of air exposure before the 2nd step anneal and the wafers in the third block have 10 hours of air exposure. The cobalt silicide wafers in the last block have 12 hours of air exposure. Figure 3 shows the sheet resistance and NANU repeatability over 500 wafers. As seen in the figure, the sheet resistance and NANU are very repeatable. In addition, no accumulation effect of air exposure up to 12 hours after TiN cap removal was observed from this test. The effect of backside emissivity on sheet resistance and uniformity of cobalt silicide layers was investigated using wafers with different backside film structures. SiO2 (100 nm) and polycrystalline Si (50, 150 or 250 nm) were deposited on both side of Si wafer by a low pressure chemical vapor deposition (LPCVD). TiN (10 nm thick) capping layer and Co films (10 nm thick) were sputtered on the front side of polycrystalline Si layer. Figure 4 shows the sheet resistance and the NANU of TiN capped Co films on Si(100) and polycrystalline Si with different backside film structure in the temperature range of 350◦ C– 700◦ C. Since the average sheet resistance and uniformity of as received TiN capped Co films were different between film structures, the sheet resistance change ratio (post-Rs/preRs) was plotted as a function of temperature. The average sheet resistance and sheet resistance uniformity in different film structures were summarized in Table I. Trends in sheet resistance change with temperature is same as TiN capped Co films on Si(100) wafers. As temperature increases from 350◦ C, the sheet resistance of the films start to increase as various phases of cobalt silicide are formed. For process temperatures between 460◦ C and 520◦ C, the sheet resistance change ratio became constant at 3.0. The sheet resistance change ratio in Co/Si(100) is constant at 2.6 in this temperature region. The sheet resistance of Co/poly-Si varies between 74.4–
Fig. 2. Average sheet resistance and uniformity of eight samples after each process steps.
Fig. 3. Sheet resistance change ratio (post-Rs/pre-Rs) and net added non-uniformity (NANU) of TiN capped, 10 nm thick Co films on poly-Si.
Jpn. J. Appl. Phys. Vol. 37 (1998) Pt. 2, No. 10B
W. S. YOO et al.
Fig. 4. Normalized temperature sensitivity curve for sheet resistance change ratio (post-Rs/pre-Rs) in TiN/Co films on various Si under layers.
Table I. Average sheet resistance and average sheet resistance uniformity of as sputtered TiN(10 nm)/Co(10 nm) on different Si underlayers. Underlayer Structure
Average Sheet Resistance (Rs) (Ä/sq.)
Average Rs Uniformity (%)
Si(100)
20.50
2.05
Poly-Si
50 nm
25.62
4.44
100 nm
26.32
2.66
250 nm
27.68
2.58
85.4 Ä/sq. depending on the film structure. Then, at around 560◦ C, the sheet resistance change ratio and sheet resistance rapidly decrease with temperature increase due to the phase transition. Above 560◦ C, the sheet resistance became constant (5.4–6.0 Ä/sq.) again. Backside film structure variation did not result in sheet resistance variation. In most lamp-heated RTP systems, wafer temperature is directly monitored by optical pyrometer(s) and controlled through sophisticated temperature controller during the process. Emissivity of Si wafer changes drastically as temperature change below 600◦ C.10) This makes wafer temperature control below 600◦ C very difficult. Since the backside film structure also changes the effective emissivity of wafer in a wide range, accurate wafer temperature measurement and control become even more difficult. In contrast, the susceptorbased RTP (Aspen RTP) system measures and controls susceptor (SiC coated graphite) temperature using optical pyrometer to provide the same thermal environment to incoming wafers regardless of backside film structure. The susceptor shows nearly black body optical characteristics (higher emissivity >0.95) and does not change its emissivity much compared to Si wafer. Higher emissivity material provides stronger optical signal at a given temperature. By measuring the temperature of higher emissivity material, we can improve the signal-to-noise ratio (S/N) of measurement. As a result, susceptor temperature can be controlled very accurately. Below 700◦ C, heat transfer through gas conduction is predomi-
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nant wafer heating mechanism. The environment temperature control and wafer heating through gas conduction are the key factors for highly reliable, backside emissivity (induced by backside film structure) independent cobalt silicidation process. Phase transition temperature of Co/poly-Si was found to be ∼40◦ C lower than that of Co/Si(100). The shift in phase transition temperature between single crystalline and polycrystalline Si is fairy common phenomena in metal silicide.1) In self-aligned silicidation process, there are two types of metal silicide interfaces (i.e. metal/poly-Si in gate area and metal/single crystalline Si in source and drain areas). It is important to have a wide overlapped process window between Co/poly-Si and Co/Si(100) for process robustness. Although the sheet resistance change ratios for Co/poly-Si and Co/Si(100) in the cobalt silicide formation temperature region, process windows for both cobalt silicide formation and anneal are overlapped in relatively wide temperature range (Fig. 4). This wide overlapped process temperature window as well as backside emissivity (induced by backside film structure) independence will provide extremely repeatable and reliable process results in device manufacturing environment. Due to the vacuum load lock, dual wafer processing capability, and highly efficient temperature ramp up/down characteristics of Aspen RTP system, a very high wafer throughput is achieved. Throughputs 63 and 50 wafers per hour were achieved for 75 s and 90 s processes, respectively. Average steady state power consumption at cobalt silicidation process temperatures (
