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Procedia Engineering 5 (2010) 902–905 Procedia Engineering 00 (2009) 000–000
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Proc. Eurosensors XXIV, September 5-8, 2010, Linz, Austria
Hybrid low temperature wafer bonding and direct electrical interconnection of 3D MEMS S. Kühne*, Ch. Hierold Micro and Nanosystems, Department of Mechanical and Process Engineering, ETH Zurich, Tannenstrasse 3, 8092 Zurich, Switzerland
Abstract The presented fabrication technology enables the direct integration of electrical interconnects during low temperature wafer bonding of 3D MEMS and wafer-level packaging. The fabrication process relies on wafer stacking by hydrophilic direct bonding of plasma activated Si/SiO2 surfaces and the simultaneous interconnection of two metallization layers by eutectic bonding of ultra-thin AuSn connects. This hybrid low temperature bonding and interconnection technology allows for the integration of metal interconnects and multiple materials in stacked MEMS devices. Further, the technology is fully compatible with waferlevel packaging approaches based on through silicon vias (TSV) or CMOS/MEMS integration. The process flow is successfully validated by fabricating test structures made out of a two wafer stack and featuring multiple ohmic electrical interconnects.
c 2009
2010 Published Published by © by Elsevier ElsevierLtd. Ltd.Open access under CC BY-NC-ND license. Hybrid wafer bonding; Vertical interconnect; Direct bonding; AuSn eutectic bonding; 3D MEMS
1. Introduction There is a growing interest in improving the performance and functionality of MEMS by integrating different materials combined with high-aspect-ratio 3D silicon structures fabricated by wafer stacking [1, 2]. The integration and electrical connection of metal electrodes for actuation and sensing in such devices is challenging and an important factor for cost and reliability issues [3, 4]. Especially, established wafer stacking technologies, based on anodic or fusion bonding, strongly restrict the integration of a metallization before the bonding due to the required elevated process temperatures. Recent advances in 3D integrated circuit (3D IC) technology demonstrated the potential of metal direct bonding for the stacking and interconnection of ICs [5]. This technology involves a demanding planarization process for adequate mechanical and electrical properties. On the other hand, Cu-Cu thermo-compressive bonding requires an annealing at elevated temperatures in order to allow Cu inter-diffusion and grain growth to achieve high enough bonding strength and low number of interfacial voids [6].
* Corresponding author. Tel.: +41 44 632 0913; fax: +41 44 632 1462. E-mail address:
[email protected].
c 2010 Published by Elsevier Ltd. Open access under CC BY-NC-ND license. 1877-7058 doi:10.1016/j.proeng.2010.09.255
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Author name / Procedia Engineering 00 (2010) 000–000
In this paper we present a hybrid low temperature fabrication technology allowing for bonding wafers featuring MEMS structures and metallization layers. One low temperature process is used to locally connect different materials and layers. A strong mechanical bond is performed by hydrophilic direct bonding of plasma activated Si and SiO2 interfaces [7, 8]. The prevailing bonding mechanism is the polymerization of hydroxyl functional groups which form strong covalent siloxane bonds [9]. Simultaneously ultra-thin AuSn contact pads are forming local electrical interconnects between the metallization layers of the two bonded substrates. Since the electrical interconnect is formed by eutectic bonding and reflow of the AuSn metallization, no substrate planarization by CMP is required before bonding. Further, the eutectic AuSn allows for the process temperature not exceeding 300°C. The fabricated test structures are made out of a two wafer stack and are featuring multiple vertical interconnects. The chip-level top view in Figure 1 shows the test device layout (a), an interconnect cross-section (b), as well as a picture of a fabricated chip (c). The basic validation concept is to prepare two substrates with complementary metallizations and interconnecting these by the presented hybrid bonding process. The lower and upper substrates are called bottom and cap wafer, respectively (Fig.1b)). The bottom wafer features the bottom metal-I, which forms the connection pads for the characterization and testing. As shown in Fig.1a), the bottom metal-I forms 8 probing pads per chip. The cap metal-II of the cap substrate constitutes the electrical path, which interconnects all 8 probing pads. Thus, the cap wafer features the cap metal-II as well as the AuSn interconnect metallization, both completely deposited into a 300nm deep cavity. The electrical connection of the bottom metal-I and the cap metal-II takes place by bonding the cap wafer onto the bottom wafer. This is schematically shown in the cross-section of Figure 1b).
Fig. 1. a) Schematic top view of the test structure showing the two complementary metallization layers and the direct bond area; b) cross-section of interconnected metal-I and metal-II; c) photograph of a fabricated test structure showing the probing pads and the bonded cap.
2. Fabrication process The process flow is illustrated in Figure 2. For the cap wafer preparation, first alignment markers and cavities for the metallization are structured by ICP dry etching processes (Fig.2a). The isotropic etching of the 300nm deep metallization cavities is time controlled and enables an interconnection by means of thin metal layers and AuSn pads. Then the cap and AuSn metallizations are deposited by e-beam evaporation and structured by a subsequent lift-off process (Fig.2b-c). A white light interferometer (WLI) 3D picture and corresponding profile of a cap metallization with connection line and deposited AuSn pad is shown in Figure 3. The bottom wafer preparation also starts with etching alignment markers and a cavity for the probing pads. This is followed by the deposition and liftoff of the bottom metal-I (Fig.2d).
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Fig. 2. Fabrication process flow.
Then the hybrid low temperature hydrophilic wafer bonding with the local eutectic bonding and reflow of the AuSn interconnects is performed. After the O2-plasma activation for the hydrophilic direct bonding, the bottom and cap wafers are aligned and brought into contact (Fig.2e)). First the eutectic bonding takes place by applying a bond tool pressure of 3 bar at a temperature of 300°C, which is above the eutectic AuSn melting point of 278°C. This step is followed by an extended direct bond annealing at 250°C for four hours (Fig.2f). Finally, a multi-level dicing is performed in order to release the chips and the probing pads for testing (Fig.2g).
Fig. 3. White light interferometer (WLI) 3D picture of a interconnection pad on the cap wafer (left), and the corresponding profile A:A (right top); plot of I-V measurements performed on multiple test structures (right bottom).
S. K¨uhne, C. Hierold / Procedia Engineering 5 (2010) 902–905 Author name / Procedia Engineering 00 (2010) 000–000
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3. Results and discussion The process flow is successfully validated by fabricating test structures made out of a two wafer stack and featuring multiple ohmic electrical interconnects as discussed in section 1. The white light interferometer (WLI) profile in Figure 3 illustrates the interconnect pad geometry. A successful electrical interconnection is achieved by countersinking the bottom metal-I in the cap wafer cavity and the AuSn reflowing at temperatures above the eutectic point. At the same time, the surrounding Si/SiO2 surfaces (red surface in the WLI 3D picture Fig.3) are forming the direct bond between bottom and cap wafer. Thus, an inherent advantage of the process is having the strong oxide bond assuring mechanical stability [6,8] and the reflown eutectic AuSn performing an electrical interconnection. A successful interconnection was evaluated by resistance measurements between the device probing pads. The fabricated interconnects were characterized by I-V measurements and are shown to perform ohmic contacts between the bottom and cap metallization. Figure 3 shows measured I-V curves of different connections. The measurements were performed between two probing pads and therefore always include two AuSn interconnects. The resistance variation of the devices is due to a non-uniform cap metal-II thickness across the wafer. The total resistance of 145±47: between two pads is in well agreement with the measured variation of the cap metallization sheet resistance being 0.855±0.29 :/Ƒ on wafer-level. 4. Conclusion The presented wafer-level process flow was applied to fabricate test structures featuring multiple electrical interconnects. The hybrid bonding process composed of an eutectic AuSn bonding and reflow at 300°C and a hydrophilic direct bonding of plasma activated Si/SiO2 surfaces was successfully validated. The interconnection was evaluated by I-V measurements across the probing pads of the test structures and evidenced the AuSn interconnects to perform ohmic contacts. Therefore this hybrid low temperature bonding and interconnection technology allows for the integration of metal interconnects and multiple materials in stacked MEMS devices. Further, the technology is fully compatible with wafer-level packaging approaches based on TSV or CMOS/MEMS integration.
Acknowledgements The authors would like to thank Shih-Wei Lee for the support with the evaporation system, Nina Wojtas for the assistance for the I-V measurements, as well as the FIRST-CLA clean room operational team.
References [1] Q.-Y. Tong and U. M. Gosele. Wafer bonding and layer splitting for microsystems. Advanced Materials 1999; 11; 1409-25. [2] J. Chae, H. Kulah, and K. Najafi. A CMOS-compatible high aspect ratio silicon-on-glass in-plane micro-accelerometer. J. Micromech. Microeng. 2005; 15; 336-45. [3] M. Esashi. Wafer level packaging of MEMS. J. Micromech. Microeng 2008; 18; 073001. [4] N. Belov, T. K. Chou, J. Heck, K. Kornelsen, D. Spicer, S. Akhlaghi, et al. Thin-layer Au-Sn solder bonding process for wafer-level packaging, electrical interconnections and MEMS applications. In: Interconnect Technology Conference, IITC 2009; 128-30. [5] P. Enquist, G. Fountain, C. Petteway, A. Hollingsworth, and H. Grady. Low Cost of Ownership scalable copper Direct Bond Interconnect 3D IC technology for three dimensional integrated circuit applications. In: 3D System Integration, 3DIC 2009; 1-6. [6] C. S. Tan, K. N. Chen, A. Fan, A. Chandrakasan, and R. Reif. Silicon Layer Stacking Enabled by Wafer Bonding. MRS Symposium Proceedings 2007; 970; 193-204. [7] T. Suni, K. Henttinen, I. Suni, and J. Makinen. Effects of Plasma Activation on Hydrophilic Bonding of Si and SiO2. J. Electrochemical Soc. 2002; 149; G348-G351. [8] S. Kuhne, R. Blattmann, and C. Hierold. Low Temperature Fabrication Process for High-Aspect-Ratio and Multi-Compliant MEMS. In: Micro Electro Mechanical Systems, MEMS 2009; 673-676. [9] T. Qin-Yi, T. Qin-Yi, G. Cha, R. Gafiteanu, and U. A. G. U. Gosele. Low temperature wafer direct bonding. J. Microelectromechanical Systems 1994; 3; 29-35.
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