IBM Synchronous Data Link Control (SDLC) Adapter

- ---------------_.­

Personal Computer Hardware Reference Library

mM Synchronous Data Link Control (SDLC) Communications Adapter

6361497

ii

Contents

Description .................................... 1

8273 SDLC Protocol Controller ................ 2

8255A-5 Programmable Peripheral Interface ...... 2

8253-5 Programmable Interval Timer ............ 4

Programming Considerations ...................... 5

Initializing the Adapter (Typical Sequence) ....... 5

8253-5 Programmable Interval Timer ............ 5

Address and Interrupt Information .............. 6

Interface ...................................... 7

Specifications .................................. 9

Logic Diagrams ................................ 11

iii

iv

Description The IBM Synchronous Data Link Control (SDLC) Communications Adapter provides communications support to the system in a half-duplex synchronous mode. The adapter receives address, data, and control signals from the system board through the internal bus. Electronic Industries Association (EIA) drivers and receivers connect to an RS232-C standard 25-pin, D-shell, male connector. The adapter is programmed by communications software to operate in a half-duplex mode. Maximum transmission rate is 9600 bits per second, as generated by the attached modem or other data communications equipment. The SDLC adapter uses an Intel 8273 SDLC Protocol Controller and an Intel 8255A-5 Programmable Peripheral Interface (PPI) for an expanded external modem interface. An Intel 8253 Programmable Interval Timer (PIT) generates timing and interrupt signals. Internal test-loop capability is provided for diagnostic purposes. The following figure is a block diagram of the IBM SDLC Communications Adapter.

/---:D""a"""ta--"-. 8255A·5 Data ~-"'" Bus Buffer

EIA Drivers Receivers

System Bus

Address

Address Decode logic

DCE

Modem

Status Change logic

SDLC Communications Adapter Block Diagram

SDLC Communications Adapter 1

8273 SDLC Protocol Controller The 8273 SDLC Protocol Controller has three operations­ transmission, reception, and port read-with each operation consisting of three phases:

Command: Commands and/or requirements for the operation are issued by the system unit's microprocessor.

Execution: Executes the command, manages the data link, and may transfer data to or from memory using direct memory access (DMA), and thus freeing the system unit's microprocessor except for minimal interruptions.

Result: Shows the effect of the command by returning the interrupt results. Support of these phases is through the internal registers and control blocks of the controller.

8255A-5 Programmable Peripheral Interface The 8255A-5 PPI has three 8-bit ports-A, B, and C. Descriptions of each bit of these ports follow. 8255A-5 Port A Assignments* Bit

7

6

5 4 3 2

Hex Address 380

1 0

~

0= Ring Indicator is on from Interface 0= Data Carrier Detect is on from .Interface Oscillating = Transmit Clock Active 0= Clear to Send is on from Interface Oscillating = Receive Clock Active 1 = Modem Status Changed 1 = Timer 2 Output Active 1 = Timer 1 Output Active

* Port A is defined as an input port

2 SDLC Communications Adapter

8255A-5 Port B Assignments* Bit

7

6

5 4

3

2

1

Hex Address 381 0

~

0= Turn On Data Signal Rate Select at Modem Interface 0= Turn On Select Standby at Modem Interface 0= Turn On Test 1 = Reset Modem Status Changed Logic

1 = Reset 8273 1 = Gate Timer 2 1 = Gate Timer 1 1 = Enable Level 4 Interrupt

* Port B is defined as an output port

8255A-5 Port C Assignments* Bit

7

6

5 4

3

2

1

Hex Address 382

0

III L~

h

Got, ;o"m,; C;ook(Oo'po,";';

1 = Gate External Clock (Output Bit) 1 = Electronic Wrap (Output Bit) 0= Gate Interrupts 3 and 4 (Output Bit) Oscillating = Receive Data (Input Bit) Oscillating = Timer 0 Output (Input Bit) 0= Test Indicate Active (Input Bit) Not Used

'Port C is defined for internal control and gating functions. It has three input and four output bits. The four output bits are defined during initialization, but only three are used.

SDLC Communications Adapter 3

8253-5 Programmable Interval Timer The 8253-5 PIT is driven by a microprocessor clock signal that is divided by 2. The PIT's three counters provide the following output: Counter 0 Programmed to generate a square-wave signal that is

used as an input to timer 2. Also connected to port C, bit 5 of the PIT. Counter 1 Connected to PPI port A, bit 7, and interrupt-level 4. Counter 2

Connected to PPI port A, bit 6, and interrupt-level 4.

4 SDLC Communications Adapter

~

Programming Considerations

Initializing the Adapter (Typical Sequence) Before the 8273 SDLC Protocol Controller is started, the support devices on the adapter must be set to the correct modes of operation. Setup of the 8255A-5 Programmable Peripheral Interface is accomplished by selecting the mode set address for the PPI and by writing the appropriate control word to hex 98 to set ports A, B, and C to the modes described previously in this section. Next, a bit pattern sent to port C disallows interrupts, sets wrap mode on, and gates the external clock pins (address is hex 382, data is hex OD). The adapter is now isolated from the communications interface. ,~



The controller reset line is brought high through bit 4 of port B, held, then dropped. This action resets the internal registers of the controller.

8253-5 Programmable Interval Timer The PIT's counters 1 and 2 terminal-count values are set to values that will provide the desired time delay before a level-4 interrupt is generated. These interrupts may be used to indicate to the communication programs that a predetermined amount of time has elapsed without a result interrupt (interrupt-level 3). The terminal-count values for these counters are set for any time delay the programmer requires. Counter 0 also is set to mode 3 (generates square-wave signal used to drive counter 2 input). The counter modes are set up by selecting the address for the PIT's counter-mode register and by writing the control word for each individual counter to the device separately.

SDLC Communications Adapter 5

When the support devices are set to the correct modes and the 8273 SDLC Protocol Controller is reset, it is ready to be set up for the operating mode that defines the communications environment in which it will be used.

Address and Interrupt Information The following tables provide address and interrupt information for the SDLC adapter. Hex Code

Device

Register Name

Function

380 381 382 383 384 384 385 385 386 386 387 388 389 38A 38B 38C

8255 8255 8255 8255 8253 8253 8253 8253 8253 8253 8253 8273 8273 8273 8273 8273

Port A Data Port B Data Port C Data Mode Set Counter 0 LSB Counter 0 MSB Counter 1 LSB Counter 1 MSB Counter 2 LSB Counter 2 MSB Mode Register Command/Status Parameter/Result Transmit INT Status Receive INT Status Data

Internal/External Sensing External Modem Interface Internal Control 8255 Mode Initialization Square Wave Generator Square Wave Generator Inactivity Time-Outs Inactivity Time-Outs Inactivity Time-Outs Inactivity Time-Outs 8253 Mode Set Out = Command In = Status Out = Parameter In = Status DMA/INT DMA/INT DPC (Direct Program Control)

SDLC Communications Adapter Device Addresses

Interrupt Level 3

Transmit/Receive Interrupt

Interrupt Level 4

Timer 1 Interrupt Timer 2 Interrupt Clear to Send Changed Data Set Ready Changed

DMA Level 1 is used for Transmit and Receive

Interrupt Information

6 SDLC Communications Adapter

Interface

The SDLC Communications Adapter conforms to interface signal levels standardized by the Electronic Industries Association (EIA) RS232-C Standard. These levels are shown in the following figure. Receivers

Drivers

+ 25 Vdc

+15VdC_

+5Vdc

+ 3 Vdc

­ Invalid Level

- 5 Vdc -15VdC-

Inactive Level: Data = 1

~

-3Vdc

~

-25Vdc

Additional lines used but not standardized by the EIA are pins 11, 18, and 25. These lines are designated as 'select standby,' 'test,' and 'test indicate,' respectively. 'Select standby' supports the switched network backup facility of a modem that has this option. 'Test' and 'test indicate' support a modem-wrap function for modems that are designed for business-machine controlled modem-wraps. Two jumpers on the adapter (PI and P2) connect 'test' and 'test indicate' to the interface.

SDLC Communications Adapter 7

8 SDLC Communications Adapter

Specifications

25-Pin D-Shell Connector

o •• • •• • • • • •• ••

•

• • • • • •• • • ••

25

14

0 Pin

Signal Name - Description

1

2

3

4

5

6

No Connection Transmitted Data Received Data Request to Send Clear to Send Data Set Ready

7

Signal Ground Received Line Signal Detector No Connection No Connection External Device

Select Standby* No Connection No Connection No Connection Transmitter Signal Element Timing No Connection

8 9 10 11 12 13 14 15 16

Receiver Signal Element Timing

17

Test (IBM Modems Only)*

18 19 20 21 22 23 24 25

No Connection Data Terminal Ready No Connection Ring Indicator Data Signal Rate Selector No Connection Test Indicate (IBM Modems Only)*

Synchronous Data Lin k Control Communications Adapter

*Not standardized by EIA (Electronic Industries Association).

Connector Specifications

SDLC Communications Adapter 9

~,

10 SDLC Communications Adapter

Logic Diagrams The following pages contain the logic diagrams for the IBM Synchronous Data Link Control (SDLC) Adapter.

SDLC Communications Adapter 11

SOLC Communications Adapter (Sheet 1 of 2)

12 SDLC Communications Adapter

.. ··.. a

a

"

M

'WO--:'~:l=======================+=-============~ ~~~:~t==========================t==~===========1

llIIO.J

+ 1113 (U5) +1If4(IN1 +II1II(111)

"

_5·_: fiiiCi z~ ':"'

-'.

~~ n u •

.M