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IEEE 802.11 Wireless LAN Implemented on Software Defined Radio With Hybrid Programmable Architecture Takashi Shono, Senior Member, IEEE, Yushi Shirato, Hiroyuki Shiba, Kazuhiro Uehara, Member, IEEE, Katsuhiko Araki, and Masahiro Umehira, Member, IEEE
Abstract—This paper describes a prototype software defined radio (SDR) transceiver on a distributed and heterogeneous hybrid programmable architecture; it consists of a central processing unit (CPU), digital signal processors (DSPs), and pre/ postprocessors (PPPs), and supports both Personal Handy Phone System (PHS), and IEEE 802.11 wireless local area network (WLAN). It also supports system switching between PHS and WLAN and over-the-air (OTA) software downloading. In this paper, we design an IEEE 802.11 WLAN around the SDR; we show the software architecture of the SDR prototype and describe how it handles the IEEE 802.11 WLAN protocol. The medium access control (MAC) sublayer functions are executed on the CPU, while the physical layer (PHY) functions such as modulation/ demodulation are processed by the DSPs; higher speed digital signal processes are run on the PPP implemented on a fieldprogrammable gate array (FPGA). The most difficult problem in implementing the WLAN in this way is meeting the short interframe space (SIFS) requirement of the IEEE 802.11 standard; we elucidate the potential weakness of the current configuration and specify a way of implementing the IEEE 802.11 protocol that avoids this problem. This paper also describes an experimental evaluation of the prototype for WLAN use, the results of which agree well with computer-simulation results. Index Terms—Hybrid programmable architecture, IEEE 802.11, Personal Handy Phone System (PHS), software defined radio (SDR), wireless communications, wireless local area network (WLAN).
I. I NTRODUCTION
I
N the mobile communication field, many kinds of secondgeneration (2G) mobile telecommunication systems such as Interim Standard 54 (IS-54) and IS-136, Global System for Mobile Communication (GSM), Personal Digital Cellular (PDC), and IS-95 are now in use. These existing mobile communication standards are primarily regional rather than Manuscript received June 19, 2003; revised April 24, 2004 and July 16, 2004; accepted July 21, 2004. The editor coordinating the review of this paper and approving it for publication is V. K. Bhargava. This paper was presented in part at the IEEE International Conference on Communications (ICC’03), Anchorage, AK, May 11–15, 2003. T. Shono, H. Shiba, K. Araki, and M. Umehira are with the Network Innovation Laboratories, NTT Corporation, Yokosuka 239-0847, Japan (e-mail:
[email protected];
[email protected];
[email protected];
[email protected]). Y. Shirato is with the Access Network Service Systems Laboratories, NTT Corporation, Yokosuka 239-0847, Japan (e-mail:
[email protected]). K. Uehara is with the Science and Core Technology Laboratory Group, NTT Corporation, Atsugi 243-0198, Japan (e-mail:
[email protected]). Digital Object Identifier 10.1109/TWC.2005.853967
universal. Although the third-generation (3G) concept, i.e., International Mobile Telecommunications-2000 (IMT-2000), aims at global standardization, the trend appears to be toward several different standard systems, most of which are based on code division multiple access (CDMA). In addition to these public mobile services, many private systems such as the IEEE 802.11 wireless local area network (WLAN) and Bluetooth have become popular. Variants have emerged even in the IEEE 802.11 WLAN standard, such as 802.11b, 802.11a, and 802.11g, since interest in the WLAN application called hot spotting is growing. Under the current approach, users must buy a dedicated wireless terminal for each system, and operators must prepare a dedicated wireless base station for each system because these systems have their own specifications such as frequency, modulation and coding scheme, and communication protocol. However, the urgent need is to be able to seamlessly hand the user terminal over among different cellular systems or between a cellular system and a hot spot system [1], [2]. Therefore, a new challenge for the next era of mobile communications, namely fourth-generation (4G) mobile communications, is the integration of multiple systems and applications into a single device. This is fortunately supported by the very rapid advances in wireless communication services and digital devices such as analog-to-digital converters (ADCs), digital-toanalog converters (DACs), and digital signal processors (DSPs), combined with recent improvements in memory and input/ output (I/O) bandwidth. The system called software defined radio (SDR), which can change its radio functions by swapping software instead of replacing hardware, seems to be the best solution given that mobile standards are springing up like mushrooms [3]–[8]. Given the above background, more and more international researchers are tackling SDR. In particular, to prove the feasibility of SDR, several organizations have developed SDR prototypes as the first step in SDR-application studies [9]–[14]. We previously reported an SDR prototype that supports only narrow bandwidth systems (up to a few hundred kilohertz) such as PDC and the Personal Handy Phone System (PHS) [15]. Although the prototypes in [9]–[14] support several modulation schemes or one type of radio standard with the multiprocessor architecture or personal computer (PC)-based architecture, no previous report has described a practical SDR implementation that supports several radio-communication standards with quite different bandwidths and communication protocols.
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Fig. 1. Block diagram of the prototype.
This paper describes an advanced prototype SDR transceiver, fabricated by us, which uses a newly developed flexible-rate pre/postprocessor (PPP) [16], and offers improved bandwidths (more than 20 MHz) and improved flexibility, such that it can handle WLAN systems. This SDR prototype was first described in [17], and the details of the prototype were discussed in [18]. The prototype supports both PHS [19] and IEEE 802.11 WLAN [20] (WLAN mode can be easily expanded to IEEE 802.11b), as well as system switching between PHS and WLAN, as well as over-the-air (OTA) software downloading with secure encryption by secure socket layer (SSL). In this paper, we design an IEEE 802.11 WLAN around the SDR; we show the software architecture of the prototype with its distributed and heterogeneous hybrid programmable architecture, which combines a central processing unit (CPU), DSPs, and PPPs, and describe how it handles the IEEE 802.11 WLAN protocol. The medium access control (MAC) sublayer functions are executed on the CPU, while the physical layer (PHY) functions such as modulation/demodulation are processed by the DSPs; higher speed digital signal processes are run on the PPP implemented on a field-programmable gate array (FPGA). The most difficult problem in implementing the WLAN in this way is meeting the short interframe space (SIFS) requirement of the IEEE 802.11 standard; we elucidate the potential weakness of the current configuration and specify a way of implementing the IEEE 802.11 protocol that avoids this problem. This paper also describes an experimental evaluation of the prototype for WLAN use. This paper is organized as follows. Section II describes the basic design of the prototype. Section III explains the software architecture of the prototype and the methodology used to design a WLAN for our SDR. Section IV gives experimental results that validate this methodology. Section V draws some conclusions and provides some final remarks. II. D ESIGN OF THE SDR P ROTOTYPE A. Prototyping Philosophy In general, the signal processes needed for wireless communications have a variety of properties. Coding schemes such as forward error correction (FEC), interleaving, and scrambling need bit manipulation, while modulation/demodulation schemes demand symbol processing, and layer-2 (L2) process-
ing needs frame handling. Moreover, some operations need iterative processing, while others need a lot of program branching. Existing processors seem rather suboptimum given the variety of operations. In an effort to optimize the processor architecture for SDR, considering such radio functions, we started by assigning these radio signal processes to the appropriate commercial processors, and only those with the highest requirements were assigned to our flexible-rate PPP. Our prototyping aim was not to create a fully commercial hybrid programmable architecture but to identify the problems with this architecture and the direction for the ideal architecture of SDR terminals. B. Composition of the Prototype The prototype consists of three stages: radio frequency (RF), intermediate frequency (IF), and baseband (BB) stages. The RF/IF stages consist of multiband analog circuits. Analog-todigital (A/D) conversion is performed at the IF. The digital IF and BB stages consist of just programmable devices. Fig. 1 shows a block diagram of the prototype; its reconfigurable portion has a hybrid programmable architecture that combines one CPU, four DSPs, and three PPPs. It has three independent RF/IF branches for the future adoption of simultaneous multimode operation and/or smart antennas. A 64-bit Versa Module Eurocard (VME) bus connects the CPU, DSP, and external interface (I/F) modules, and the DSP connects to the PPP via a mezzanine I/F. The CPU is a 400-MHz PowerPC with the real-time operating system (OS), VxWorks. Memories, a hard disk drive (HDD), and man–machine-interface (MMI) devices for user operation are connected to the CPU via local and expansion buses. The DSP module is a general-purpose DSP board consisting of four fixed-point arithmetic chips, each with a 200-MHz clock and 1600 million instructions per second (MIPS) maximum operation power. For PHS operation, the external I/F module provides an integrated services digital network (ISDN) service in the cell-station (CS) platform and voice and bearer services in the personal-station (PS) platform. This is the only difference between the CS and PS platforms. For WLAN operation, the CPU module provides an ethernet I/F in both the access-point (AP) and station (STA) platforms. Fig. 2 shows the appearance of the prototype. The RF signal received by the antenna is down converted to an IF signal by analog circuits and then A/D converted. A
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TABLE I MAJOR SPECIFICATIONS OF PHS AND WLAN MODES
Fig. 2.
Appearance of the prototype.
multiband RF/IF circuit based on a super-heterodyne scheme was developed. The multiband operation for PDC, PHS, and IEEE 802.11 WLAN was realized with a single amplifier by switching bandpass filters to support 1.5-, 1.9-, and 2.45-GHz operations. A multiband monopole antenna that resonates at these frequencies is used. A/D conversion is performed by undersampling the 66 ± 11-MHz IF signal in an ADC with 12-bit resolution and 88-Msps sampling rate. The automatic-gain-control (AGC) circuit is set before the ADC. Digital-to-analog (D/A) conversion is performed using a DAC with 14-bit resolution after upsampling the 22 ± 11-MHz BB signal. Imaging at 66 ± 11 MHz yields the IF signal. The IF cannot be processed by BB processors, so PPPs are used to realize the high-speed real-time digital signal processing required; the processes include filtering, waveform shaping, and spectrum despreading. In particular, the PPP was newly developed so that the prototype could offer an improved bandwidth of more than 20 MHz and better flexibility for handling WLAN systems [16]. The prototype uses a CPU and DSPs to perform BB processing and control. The CPU handles high-layer protocols including the call control for PHS and MAC processes for WLAN. PHY processes such as modulation/demodulation, spreading, scrambling/descrambling, automatic frequency control (AFC), and voice coding/decoding are handled by the DSPs. Two DSP chips are used: one for transmitting, and the other for receiving. C. Implemented Radio Systems Table I shows the major specifications of the radio systems currently implemented on the prototype: PHS and IEEE 802.11 WLAN. PHS is a four-channel time division multiple access (TDMA) and time division duplex (TDD) wireless system. The voice coder/decoder (CODEC) uses 32 kbit/s adaptive differential pulse-code modulation (ADPCM), and the modulation/ demodulation schemes are π/4-shift quadrature phase-shift keying (QPSK) and differential detection. In WLAN mode, direct-sequence spread-spectrum (DS/SS) is selected for the PHY. Multirate transmission is enabled by two modulation schemes: binary phase shift keying (BPSK) and QPSK. The
TABLE II FUNCTION ASSIGNMENT TO PROCESSORS
prototype offers a distributed coordination function (DCF) that supports asynchronous frame-transfer services based on carriersense multiple access with collision avoidance (CSMA/CA). DCF is also offered by many current commercial products. The AP is a portal with a bridge function to Ethernet/IEEE 802.3. Moreover, passive scanning with a beacon frame is adopted in order to allow the STA to join the basic service set (BSS). The functions not implemented at this time include wired equivalent privacy (WEP), power management, and virtual carrier sense realized by the request-to-send (RTS) and clear-to-send (CTS) frames transfer. Note that IFS has variable length, as described later. III. S OFTWARE A RCHITECTURE The hybrid programmable architecture using a CPU, DSPs, and PPPs enables more flexible task assignment, but the arrangement adopted seriously influences system performance. This section describes the architecture of software assignment to each processor in WLAN mode and the SIFS issue, which is the most difficult problem when implementing IEEE 802.11 WLAN on this architecture. A. Function Assignment of Communication Tasks Table II summarizes the assignment of functions to the processors. System performance depends, to a large extent, on how the critical functions such as modulation/demodulation and protocol sequence processing are assigned to the different processors. Since most DSPs have a special instruction
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Fig. 3. Software configuration of WLAN mode.
Fig. 4. Delay elements of the SIFS process.
set, parallel operation unit, and a memory bus optimized for the digital signal processing, they can achieve higher digital signal-processing speeds than CPUs with the same clock speed and the same power consumption. Accordingly, the prototype has a multiprocessor architecture like other SDRs; protocol sequence processing and equipment control are done by the CPU, while digital signal processing is done in the DSPs. This approach was used in our previous SDR prototype [15].
Fig. 3 shows the software configuration of the prototype in WLAN mode. We used VxWorks because the WLAN protocol has far stricter requirements in terms of interrupt response time than PHS. This real-time OS also allowed optimization of the function assignment. Our previous SDR prototype used Solaris and was unable to achieve adequate interprocess communication. VxWorks offers significantly shorter interrupt times and allows finer allocation of tasks. Future
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work includes optimizing the SDR design by examining other factors that influence the hardware and software configurations such as interrupt response time, context-switching interval, bus bandwidth, and the control of shared memories (semaphore processing). In implementing the various IEEE 802.11 functions on the prototype, we assumed that the MAC sublayer functions would be executed on the CPU while the PHY functions such as modulation/demodulation would be processed by the DSPs. The PPP is used to perform the high-speed processes that cannot be run on the CPU or DSP. For instance, the spreading process for DS/SS incurs small loads and can be implemented on a DSP. However, detecting the correlation peak in real time at the despreading stage is beyond the ability of current DSPs, so it is done as a preprocess in the PPP. B. Resolving the SIFS Issue An analysis of the PHY/MAC processes of IEEE 802.11 shows that the SIFS value imposes the most severe requirements in terms of response time. SIFS in the DCF mode represents the time available for completing high-priority operations such as the acknowledgment (ACK) response to MAC protocol data unit (MPDU) reception and the CTS response to RTS reception. The SIFS period is defined for each PHY specification (10 µs in DS/SS), and meeting the value specified imposes very severe demands on any multiprocessor architecture. In particular, the context-switching interval of a real-time kernel is usually of the order of milliseconds and the CPU may fail to complete a task if the interval is very short. If the function assignment for the CPU and DSP is ideal, the delay elements of the SIFS process are as shown in Fig. 4, which gives an example of the sequence from the PHY convergence protocol (PLCP) PDU (PPDU) reception to the ACK response. SIFS is the time from the reception of the last PPDU symbol to the transmission of the first symbol of the response PPDU. The period from PPDU reception in the RF part to ACK-PPDU transmission is defined as SIFS in this paper. The delay of the processes described in the time line in Fig. 4 can be decreased to some extent by using parallel processing. The designs of a high-speed interrupt handler, direct memory access (DMA), shared memory, and I/O are very important in realizing such parallel processing. To complete the testing of the prototype in the shortest period of time, we restricted ourselves to using only commercial hardware. This imposed several restrictions on system performance. The key problem was satisfying the SIFS specified in IEEE 802.11. We found that the VME bus did not offer adequate performance; 40 µs was needed simply to transmit a 1500-byte Ethernet frame between the DSP and CPU. Moreover, the CPU interrupt response time was not short enough. VxWorks running on the CPU yielded an interrupt response time of 3 µs, which is an appreciable fraction of the SIFS period of IEEE 802.11 (10 µs). Due to the above problems, ACK frames cannot be transmitted within the original SIFS period, which means that frame acknowledgment fails (ACK timeout). Accordingly, to allow the performance of the prototype to be tested, we slightly
Fig. 5. Relation between IFS multiplier and throughput; unicast-frame transfer for M values of 1, 5, 10, 15, and 20.
modified the software to use a longer IFS. To be more precise, each IFS value was multiplied by the same integer value. The relationship between the IFS multiplier M and each IFS value is as follows: SIFS = M · SIFS
(1)
DIFS = M · DIFS = M · (SIFS + 2 · aSlotTime)
(2)
EIFS = SIFS + DIFS + (8 · ACKSize) + aPreambleLength + aPLCPHeaderLength (3) where SIFS, DIFS is the standard IFS value of IEEE 802.11. SIFS , DIFS , EIFS is the IFS value of the prototype. For aSlotTime, ACKSize, aPreambleLength, and aPLCPHeaderLength, please see the IEEE 802.11 specification [20]. Our SDR with the hybrid programmable architecture can provide WLAN support by selecting a suitable value of M . Note that the slot time and ACK timeout also change as the IFS value changes. The relationship between the IFS multiplier and WLAN-mode throughput is shown in Fig. 5 (the MAC frame is unicast without fragmentation). The throughput means the maximum data transmission rate of MPDU assuming that the wireless channel has no bit error or congestion. When M is 10, throughput is about 70% of the original performance. IV. E XPERIMENTAL E VALUATION To evaluate the WLAN performance of the prototype, we examined both the PHY and MAC sublayers. For the PHY, we conducted a transmitter-spectrum analysis, correlationdetection analysis, and frame error rate (FER)-performance analysis. The MAC sublayer examination analyzed the throughput and DSP load.
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Fig. 6. PHY characteristics. (a) Transmitter spectrum. (b) Correlation output.
A. PHY Performance Output signals of the PPP were measured to evaluate the basic PHY performance for WLAN mode. The spectrum at the output of the PPP of the transmitter in WLAN mode is shown in Fig. 6(a). The measured spectrum satisfied the transmit-spectrum mask described in the IEEE 802.11 specification: less than −30 dBr (dB relative to the sinc peak) for 11 MHz < |f − fc | < 22 MHz, and less than −50 dBr for |f − fc | > 22 MHz, where fc is the channel center frequency. Fig. 6(b) shows the correlation output of the PPP of the receiver in WLAN mode. Peaks were monitored every 22 samples for 11 MHz, which represents twice-oversampled data. Next, the performance was assessed in terms of FER versus carrier-to-noise power ratio (CNR). The carrier and noise power were measured at the input of the PPP, so the carrier power is the one before despreading. The measurement results for QPSK modulation and 1024/2048-byte-long frame transmission are shown in Fig. 7. The performance of the theoretical analysis based on Bennet and Davey [21] is also shown for comparison. These plots show good agreement between experimental and theoretical results.
Fig. 7. FER performance for QPSK. (a) 1024-byte-long frame. (b) 2048-bytelong frame.
B. MAC Sublayer Performance After implementing WLAN mode on the prototype, we found that M should be at least 10. The main barrier to supporting IEEE 802.11 on the prototype is the context-switching interval of the real-time OS. The context-switching interval of VxWorks can be reliably reduced to 200 µs (10 ms is the default value), which supports the IFS-extended version of the IEEE 802.11 standard. We also found that VxWorks was sensitive to the system clock because its internal timer is triggered from the system clock. The 5-kHz system clock on the CPU board used creates significant jitter (399 µs). We determined that by
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Fig. 8.
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Measurement system for MAC layer performance. (a) One-to-one communication. (b) One-to-two communication.
extending SIFS to 100 µs, the default value of the prototype, we could fully support CSMA/CA operation. We measured throughput across a one-to-one cable connection (one AP and one STA), and across a one-to-two cable connection (one AP and two STAs). First of all, we examined the one-to-one throughput characteristics. The measurement environment is shown in Fig. 8(a). Packets were generated and received by connecting LAN analyzers via ethernet to SDR sets; ethernet frames were used. At the SDR transmission set, the ethernet frames received from the ethernet I/F were converted into IEEE 802.11 frames without a frame check sequence (FCS) and then transmitted to the DSPs via the VME bus. The PLCP frames were first generated by adding FCS, the PLCP header, and PLCP preamble in the DSP and then writing them into the first-in first-out (FIFO) buffer in the DSP board. The FIFO output was passed to the PPP for subsequent hardware processing. The reverse process was done in the reception set, and the ethernet frames were analyzed on the LAN analyzer. Fig. 9(a) shows the measured throughput when transmitting multicast frames with BPSK and M = 10. Computer-simulation results are also shown for reference. The contention-window (CW) size used in the computer simulation was set to 17. This value represents the average of the initial CW size because the one-to-one connection prevented frame congestion and collision. For multicast transmission over the uplink, because channel contention occurs between the frame retransmitted by the AP and the next frame of the STA, the
average initial CW size is about 10. Therefore, in the computer simulation of the uplink, the CW size was set to 10, assuming that frame collision did not occur. Fig. 9(b) shows the measured throughput when transmitting unicast frames with M = 10. Moreover, Fig. 9(c) shows the throughput for various IFS multipliers and BPSK. It can be seen that WLAN operation was achieved, regardless of the IFS multiplier value. Fig. 9(a)–(c) indicates that the prototype offers good throughput characteristics that closely match the results of the computer simulations. Next, we assessed the one-to-two throughput characteristics. The measurement environment is shown in Fig. 8(b). To confirm CSMA/CA operation in WLAN mode, we measured the throughput while varying the offered load. Throughput was measured for two frame lengths: 82 and 1536 bytes. Fig. 9(d) shows the measured throughput across the AP with equal traffic from each STA. The horizontal axis shows the total traffic from STA 1 and STA 2, and the vertical axis shows the MAC-frame throughput as received by the AP. The computer simulations considered two cases. In Case 1, the local STA timer had no jitter, and perfect slot synchronization was achieved between STAs. In Case 2, frame collision occurred when STA 1 and STA 2 selected adjacent slot numbers when performing backoff. Such a situation can occur in a real system because STA slots are asynchronous due to the timer jitter of the OS. One of the factors causing the discrepancy between the measured and Case-1 plots is this jitter. Moreover, when the traffic exceeds
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Fig. 9. Throughput characteristics. (a) Multicast-frame transfer for BPSK and M = 10. (b) Unicast-frame transfer for M = 10. (c) Unicast-frame transfer for various IFS multipliers and BPSK. (d) Throughput versus traffic load; unicast-frame transfer for BPSK and M = 10.
the maximum rate of the wireless channel, packets are dropped due to buffer overflow, which causes the throughput to saturate. Short frames (82 bytes) yield low throughput due to the large overhead in the PLCP sublayer, as can be understood from Figs. 5 and 9(a)–(c). Therefore, the throughput versus offered traffic characteristics of the prototype agreed well with the computer-simulation results, and we could confirm normal CSMA/CA operation. Finally, we investigated the DSP-load characteristic, which we measured by computing the number of fetch cycles of each task; the result is shown in Fig. 10. Transmission/reception processes were executed in different DSPs. The DSP load on the transmitting side was measured when four of the symbols constituting the MPDU underwent QPSK modulation, while the
DSP load on the receiving side was measured when demodulating one symbol. Transmission loads were heavier than reception loads because the transmit (Tx) DSP could transmit MPDU while reading PLCP preamble and PLCP header, whereas the receive (Rx) DSP read data from the PPP symbol by symbol. The maximum DSP load was 60%, which means that the DSPs can handle IEEE 802.11 signal processing. V. C ONCLUSION This paper reviewed our methodology of designing an SDR that has a distributed and heterogeneous hybrid programmable architecture and is intended to realize IEEE 802.11 WLAN operation. The keys to achieving this were elucidated:
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Fig. 10. DSP-load characteristic.
assignment of signal-processing functions to processors and reconfigurable hardware (CPU, DSP, and PPP) and IFS extension for full support of CSMA/CA operation, which is a fundamental MAC protocol of IEEE 802.11. The latter resolves the problem caused by the low speed of the bus between the processors, interrupt response time of each processor, and context-switching interval of real-time OS. A prototype SDR transceiver that supports both PHS and IEEE 802.11 WLAN in line with this policy was successfully fabricated. Additionally, experiments to verify the operation of WLAN mode were performed, and we confirmed that their results agreed well with theoretical results or with computer-simulation results. We found that, to fully support the IEEE 802.11 protocol, which has severe time-critical requirements, a dedicated programmable hardware chip is required. We are now developing a terminal-size SDR transceiver to meet all the requirements of certain existing wireless standard specifications based on our experience with the prototype.
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[7] W. H. W. Tuttlebee, Software Defined Radio: Origins, Drivers and International Perspectives. New York: Wiley, 2002. [8] ——, Software Defined Radio: Enabling Technologies. New York: Wiley, 2002. [9] T. Turlett, H. J. Bentzen, and D. Tennenhouse, “Toward the software realization of a GSM base station,” IEEE J. Sel. Areas Commun., vol. 17, no. 4, pp. 603–612, Apr. 1999. [10] M. Laddomada, F. Daneshgaran, M. Mondin, and R. M. Hickling, “A PC-based software receiver using a novel front–end technology,” IEEE Commun. Mag., vol. 39, no. 8, pp. 136–145, Aug. 2001. [11] J. Glossner, D. Iancu, J. Lu, E. Hokenek, and M. Moudgill, “A softwaredefined communications baseband design,” IEEE Commun. Mag., vol. 41, no. 1, pp. 120–128, Jan. 2003. [12] J. R. Moorman, “Implementation of a 3G W-CDMA software radio,” in Proc. IEEE Int. Conf. Communications, Anchorage, AK, May 2003, vol. 4, pp. 2494–2499. [13] C. Zhang, X. Su, X. Xu, and Y. Yao, “Implementation issues of PCbased software radio systems,” in Proc. IEEE Int. Symp. Personal, Indoor Mobile Radio Communications, Beijing, China, Sep. 2003, vol. 1, pp. 140–143. [14] I. Teshima, K. Takahashi, Y. Kikuchi, S. Nakamura, and M. Goami, “Development of software radio prototype,” in Proc. Software Defined Radio Technical Conf. Product Expo., San Diego, CA, Nov. 2002, vol. 1, pp. 169–174. [15] Y. Suzuki, K. Uehara, M. Nakatsugawa, Y. Shirato, and S. Kubota, “Software radio base and personal station prototypes,” IEICE Trans. Commun., vol. E83-B, no. 6, pp. 1261–1268, Jun. 2000. [16] M. Nakatsugawa, Y. Shirato, H. Yoshioka, A. Shibuya, and M. Matsui, “An SDR platform for cellular/WLAN systems based on a systematic analysis of hardware implementation issues to maximize system func tionality,” in Proc. IEEE Radio Wireless Conf., Boston, MA, Aug. 2001, pp. 185–188. [17] K. Uehara, H. Shiba, T. Shono, Y. Shirato, H. Yoshioka, M. Nakatsugawa, S. Kubota, and M. Umehira, “Design and performance evaluation of software defined radio prototype for PHS and IEEE 802.11 wireless LAN,” in Proc. IEEE Int. Symp. Personal, Indoor Mobile Radio Communications, Lisbon, Portugal, Sep. 2002, vol. 1, pp. 452–457. [18] H. Shiba, T. Shono, Y. Shirato, I. Toyoda, K. Uehara, and M. Umehira, “Software defined radio prototype for PHS and IEEE 802.11 wireless LAN,” IEICE Trans. Commun., vol. E85-B, no. 12, pp. 2694–2702, Dec. 2002. [19] Personal Handy Phone System, RCR Standard 28, 1995. [20] Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications, IEEE Standard 802.11, 1999. [21] W. R. Bennet and J. R. Davey, Data Transmission. New York: McGrawHill, 1965.
ACKNOWLEDGMENT The authors wish to express their gratitude to H. Tanaka of NTT Resonant Inc. for his great contribution toward the WLAN connection in the first stage of their SDR project. R EFERENCES [1] R. Becher, M. Dillinger, M. Haardt, and W. Mohr, “Broadband wireless access and future communication networks,” Proc. IEEE, vol. 89, no. 1, pp. 58–75, Jan. 2001. [2] T. Shono, K. Uehara, and S. Kubota, “Proposal for system diversity on software defined radio,” IEICE Trans. Fundam., vol. E84-A, no. 9, pp. 2346–2358, Sep. 2001. [3] J. Mitola, III, “The software radio architecture,” IEEE Commun. Mag., vol. 33, no. 5, pp. 26–38, May 1995. [4] A. K. Salkintzis and N. Hong, “ADC and DSP challenges in the development of software radio base stations,” IEEE Pers. Commun., vol. 6, no. 4, pp. 47–55, Aug. 1999. [5] J. Mitola, III, Software Radio Architecture: Object-Oriented Approaches to Wireless Systems Engineering. New York: Wiley, 2000. [6] E. D. Re, Software Radio: Technologies and Service. Berlin, Germany: Springer-Verlag, 2001.
Takashi Shono (M’00–SM’04) received the B.E. and M.E. degrees in electrical engineering in 1996 and 1998, respectively, and the Ph.D. degree in information and computer science in 2004, all from Keio University, Yokohama, Japan. He joined the Wireless Systems Laboratories of Nippon Telegraph and Telephone (NTT) Corporation, Yokosuka, Japan, in 1998, where he was involved in the research and development of spread spectrum (SS), orthogonal frequency division multiplexing (OFDM), multicarrier code division multiple access (MC-CDMA), and software defined radio (SDR) systems. He is currently with NTT Network Innovation Laboratories, Yokosuka. His current research interests include signal-processing functions such as synchronization, detection, channel estimation, and interference cancellation for multicarrier modulation including OFDM and MC-CDMA. Dr. Shono was awarded the Young Researcher’s Award from IEICE and the 18th Telecom System Technology Award from the Telecommunications Advancement Foundation of Japan in 2002 and 2003, respectively. He is a Member of IEICE.
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Yushi Shirato received the B.E. and M.E. degrees in electrical engineering from Tokyo University of Science, Tokyo, Japan, in 1990 and 1992, respectively. Since joining NTT, Yokosuka, Japan, in 1992, he has been engaged in the research and development of digital signal-processing techniques on adaptive equalizers, automatic-gain-controlled amplifiers and diversity combining, as well as SDR systems. He is currently a Research Engineer at NTT Access Network Service Systems Laboratories. His current research interest is the modems for fixed wireless access (FWA) systems. Mr. Shirato received the Young Researcher’s Award from IEICE in 1999. He is a Member of IEICE.
Hiroyuki Shiba received the B.E. and M.E. degrees from Gunma University, Maebashi, Japan, in 1995 and 1997, respectively. He joined NTT Wireless Systems Laboratories, Yokosuka, Japan, in 1997, and engaged in the research of data communication and SDR systems. He is currently with NTT Network Innovation Laboratories, Yokosuka. Mr. Shiba received the Young Researcher’s Award from IEICE and the 18th Telecom System Technology Award from the Telecommunications Advancement Foundation of Japan in 2001 and 2003, respectively. He is a Member of IEICE.
Kazuhiro Uehara (M’92) received the B.E., M.E., and Ph.D. degrees from Tohoku University, Sendai, Japan, in 1987, 1989, and 1992, respectively. In 1992, he joined NTT, Yokosuka, Japan and was engaged in the research of array antennas, active antennas and indoor propagation in millimeterwave and microwave frequency bands. He was also engaged in the research and development of SDR systems. From 1997 to 1998, he was a Visiting Associate at the Department of Electrical Engineering, California Institute of Technology, Pasadena. From 2003 to 2004, he was a Part-Time Lecturer at the Department of Electrical Engineering, Tohoku University. He is also a Senior Manager at NTT Science and Core Technology Laboratory Group, Atsugi, Japan, where he engages in research planning. Dr. Uehara received the Young Researcher’s Award and the Excellent Paper Award from IEICE in 1995 and 1997, respectively, the first Yokosuka Research Park (YRP) Award from the YRP R&D Promotion Committee of Japan in 2002, and the 18th Telecom System Technology Award from the Telecommunications Advancement Foundation of Japan in 2003. He is a Member of IEICE.
Katsuhiko Araki received the B.E. and M.E. degrees from Tokyo Institute of Technology, Tokyo, Japan, in 1979 and 1981, respectively. He joined NTT Electrical Communications Laboratories, Yokosuka, Japan, in 1981, where he has been engaged in the research of GaAs monolithic microwave circuits and the development of communication satellite-onboard transponders. He is currently a Senior Research Engineer and Supervisor at NTT Network Innovation Laboratories, Yokosuka. Mr. Araki was the recipient of the 1987 Shinohara Memorial Young Investigators Award presented by IEICE. He is a Member of AIAA and IEICE.
Masahiro Umehira (M’85) received the B.E., M.E., and Ph.D. degrees from Kyoto University, Kyoto, Japan, in 1978, 1980, and 2000, respectively. Since joining NTT, Yokosuka, Japan in 1980, he has been engaged in the research and development of modem and time division multiple access (TDMA) equipment for satellite communications, TDMA satellite communication systems, wireless asynchronous transfer mode (ATM), and broadband wireless access systems for mobile multimedia services. From 1987 to 1988, he was with the Department of Communications, Communications Research Center, Ottawa, ON, Canada, as a Visiting Scientist. He was involved in the ATM wireless access communication system (AWACS) project in the advanced communications technologies and services (ACTS) from 1997 to 1998. He has been active in the standardization activities related to wireless ATM and WLANs that use the 5 GHz band in Japan, Europe, and the USA. He is now a Director of Wireless Systems Innovation Laboratory in NTT Network Innovation Laboratories, Yokosuka, where he is responsible for the research and development of wireless technologies in the areas of next-generation fixed/nomadic/mobile wireless systems, future satellite communication systems, and ubiquitous services using radio frequency identification (RFIDs). Dr. Umehira received the Young Researcher’s Award and Achievement Award from IEICE in 1987 and 1999, respectively. He also received the Education, Culture, Sports, Science, and Technology Minister Award in 2001. He is a Member of IEICE.
