Aug 13, 2012 - To continue the work of six previous workshops ... Devices Society (EDS) and Solid-State ... CAMP ED Student Branch Chapter, .... Electronic.
PEOPLE
IEEE SSCS DL Vladimir Stojanovic Lectures at SEMINATEC 2012 Seventh Annual Workshop on Semiconductors and Micro- and Nanotechnology Sponsored by SSCS-Sao Paulo in April
T
To continue the work of six previous workshops, all focused on technology trends in the areas of micro and nanotechnology, and to promote interaction among industry, academy, R&D centers, government, and students looking for opportunities to improve education, research, and technology, VII SEMINATEC was organized jointly by the IEEE South Brazil Section of the Electron Devices Society (EDS) and Solid-State Circuits Society (SSCS), the IEEE UNICAMP ED Student Branch Chapter, the Brazilian Microelectronic Society, and the NAMITEC Science and Technology National Institute. Held 12–13 April, the 2012 workshop covered topics related to semiconductors such as optoelectronic devices, optics, fabrication of microand nanostructures, microsystems, device modeling and characterization, and integrated circuits. Having attracted more than 130 participants, including 50 professionals from industry and academia, and about 80 graduate and undergraduate students from universities and companies mostly from the State of Sao Paulo, the event was deemed a success. In addition to the four EDS DLs who were invited to speak, SSCS DL and MIT Prof. Vladimir Stojanovic presented a talk titled “Designing VLSI Interconnects with Monolithically Integrated Silicon-Photonics.” Digital Object Identifier 10.1109/MSSC.2012.2202474 Date of publication: 13 August 2012
74
S U M M E R 2 0 12
From left: James Merz, University of Notre Dame, United States; Sorin Cristoloveanu, INPG, France; Vladimir Stojanovic, MIT, United States; Marcelo Antonio Pavanello, FEI, Brazil, SEMINATEC general chair; Denis Flandre, ICTEAM Institute, UCLouvain, Belgium; and Francisco Garcia-Sanchez, Universidad Simon Bolivar, Venezuela.
SSCS DL Vladimir Stojanovic lecturing on an experimental platform for monolithic integration of silicon photonic devices at VII SEMINATC in Sao Paulo in April.
IEEE SOLID-STATE CIRCUITS MAGAZINE
In it he explained experimental and modeling efforts in designing high-performance, energyefficient, monolithically integrated photonic links (Figure 1). Link modeling illustrates the inherent tradeoffs between circuit and device components and points to both efficient system approaches and critical device design sensitivities (Figure 2). In addition, Prof. Stojanovic presented an experimental platform for monolithic integration of silicon photonic devices into
EOS Platform for Monolithic CMOS Photonic Integration
2011
ices
ic ton
Dev
ho
nd
rs a
to nsis
s 100
of P
ra
s1
Transmission (dB)
2007
rd owa
0 –2 –4 –6 –8 –10 –12 –14
MT
T
45 nm SOI CMOS IBM 12SOIs0 –200 0 200 400 600 8001,000 Frequency (GHz)
32 nm Bulk CMOS Texas Instruments
90 nm Bulk CMOS IBM CMOS9sf Created Integration Platform to Accelerate Technology Development and Adoption
65 nm Bulk CMOS Texas Instruments FIGURE 1
Energy–Cost (fJ/b)
400
300
200
b1
r1
Φ
r2
b2
r3
b3
r4
Modulator Driver
λ1 λ2 λ0 λ3 λ4
λ4
Ring Tuning Control
512 Gb/s Aggregate Throughput
Ring Tuning Control
Off-Chip Laser Optical ΦF Fiber r0 b0
Clock Buffer Tree
500
Vertical Coupler Drop Rings r9 Data b3 Rx
λ3 λ0 λ2 λ1
r7
b2 Data Cx b1
r6 r5
b0 Photodiode
Waveguide
a) Chip-to-Chip
100
r8
Clock Buffer Tree
Electronic-Photonic WDM Link Tradeoffs: Need to Optimize Carefully
b) Intrachip
Optical Fiber
Tune Heating 0
Tune Backend 1
2 4 8 16 Data Rata Per λ (Gb/s)
24
32
• Laser Energy Increases with Data Rate – Limited Rx Sensitivity
Clock Serdes Rx Tx Laser
–Modulation More Expensive -> Lower Extinction Ratio • Tuning Costs Decrease with Data Rate • Moderate Data Rates Most Energy Efficient FIGURE 2
IEEE SOLID-STATE CIRCUITS MAGAZINE
S U M M E R 2 0 12
75
EOS Platform Organization Monolithic Electronic-Photonic Circuit Test Region 9-Cell Test Cell Row 1 Cell
Row 2 Row 3 Row 4 Row 5 Row 6 2.9 mm
2.3 mm 256 μm Coupler
Modulator
Coupler Ring
PD
2x Receiver
Double Data Rate Modulator Driver
Self Test
2 2x BER Test
2x Snapshot
BER Test
Snapshot
2
Clock Receiver
2x PRBS
Clock Count
PRBS
Counter
80 μm
Electronic Backend
Coupler
PD
Waveguide to Next Site
Cell Test Site
~57 k Transistors
Scan Chain Digital I/O Interface • 3M Transistors, Hundreds of Photonic Devices, 54 Link Test Sites Orcutt et al, Optics Express, May 2012 FIGURE 3
a mainstream sub-100 nm foundry CMOS process flow. This platform serves as an infrastructure hub for research in photonic device design, integration and process issues as well as circuit design (Figure 3). It facilitates the full integration of circuits and photonic components and highspeed in-situ testing infrastructure. Finally, Prof. Stojanovic presented very interesting experimental results from optical interconnects
76
S U M M E R 2 0 12
on silicon designed in standard 45 nm and 32 nm CMOS processes without any change in the actual process flow. Beyond, Prof. Vladimir showed the necessary testing environment for such systems needing electrical and optical characterizations. The EDS presenters were ■ Denis Flandre, ICTEAM Institute, UCLouvain, Belgium, “Disruptive Design Techniques Based on Ultra-Low-
IEEE SOLID-STATE CIRCUITS MAGAZINE
Leakage CMOS blocks for Ultra-LowPower Circuits and Microsystems” ■ James Merz, University of Notre Dame, United States, “Flatland Revisited—The Land of Quantum Structures in Compound Semiconductors” ■ Sorin Cristoloveanu, INPG, France, “Ultrathin SOI for Logic, Memory, and Steep Slope Devices” ■ Francisco Garcia-Sanchez, Universidad Simon Bolivar, Venezuela, “Explicit Lumped-Parameter Modeling of Solar Cells.” SEMINATEC session paper titles and authors and additional photos can be found on the conference Web site, www.fei.edu.br/seminatec2012/ default.html. —Wilhelmus Van Noije Chair, SSCS-Sao Paulo Professor, University of Sao Paulo, Brazil
