III-V/Ge CMOS Device Technologies for High Performance Logic ...

ECS Transactions, 53 (3) 85-96 (2013) 10.1149/05303.0085ecst ©The Electrochemical Society

III-V/Ge CMOS Device Technologies for High Performance Logic Applications S. Takagi1, M. Yokoyama1, S.-H. Kim1, R. Zhang1, R. Suzuki1, N. Taoka1, 2, and M. Takenaka1 1

The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656 Japan 2 Nagoya University, Furo-cho, Chikusa-ku, Nagoya 464-8603 Japan

One of the ultimate CMOS structures can be the combination of III-V nMOSFETs and Ge pMOSFETs, because of high mobility and low effective mass. In order to realize III-V/Ge CMOS, common gate stack and source/drain (S/D) formation technologies are important. Here, an atomic layer deposition (ALD) Al2O3 gate insulator and Ta metal gate were used for common gate stacks for InGaAs and Ge. This is because ALD Al2O3 can provide good MOS interfaces with InGaAs as well as Ge with post electron cyclotron resonance (ECR) plasma oxidation. Also, self-aligned Ni-Ge and Ni-InGaAs, which can be formed simultaneously for InGaAs nMOSFETs and Ge pMOSFETs, were used as the metal S/D regions. By utilizing these technologies, we have demonstrated successful integration of InGaAs-OI nMOSFETs and Ge p-MOSFETs on the same wafer. In order to realize the integration of III-V/Ge MOSFETs, we have bonded III-V substrates with Ge substrates. We have found good transistor operation in both devices. High Ion/Ioff ratio of ~106 was obtained for InGaAs-OI nMOSFETs. The high electron and hole mobility of 1800 and 260 cm2/Vs and the mobility enhancement against Si of 3.5× and 2.3× have been demonstrated for InGaAs-OI nMOSFETs and Ge pMOSFETs, respectively. Introduction It has been well recognized that new device engineering is indispensable in overcoming difficulties of advanced CMOS and realizing high performance LSIs under 10 nm regime. According to the future evolution scenario of CMOS device/process technologies presented in the International Technology Roadmap for Semiconductors (ITRS) 2012 edition [1], introduction of new channel materials with enhanced carrier transport properties into MOSFETs are strongly expected or even accelerated for further increasing current drive and resulting LSI performance. Here, the channel materials with high mobility and, more essentially, low effective mass, are preferable under quasiballistic transport expected in ultra-short channel regime [2]. Because of extremely high electron mobility and low electron effective mass of Ge and III-V semiconductors such as GaAs, InP, InGaAs and InAs, these materials are suitable for nMOSFET applications. Also, extremely high hole mobility and low hole effective mass of Ge make Ge one of promising materials for pMOSFETs. Also, GaSb and InSb can be promising III-V materials for pMOSFET applications, because of higher hole mobility among III-V materials. As a result, Ge and III-V materials are quite suitable for high performance

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ECS Transactions, 53 (3) 85-96 (2013)

CMOS applications. Thus, one of the ultimate CMOS structures can be the combination of III-V nMOSFETs and Ge pMOSFETs, as shown in Fig. 1 [2-6]. While III-V CMOS including Sb-based III-V materials would also be interesting [7, 8], device research on the Sb-based III-V MOSFETs has not matured yet. Thus, the combination of III-V nMOSFETs and Ge pMOSFETs can be more realistic at present.

High-k gate insulator

Metal G

Metal S/D

Metal G

BOX

Si sub. III-V-OI nMOSFET

strained GOI pMOSFET

BOX Si sub.

III-V-OI n-FinFET or TriGate n-FET

strained GOI p-FinFET or TriGate p-FET

Fig. 1. Ultimate CMOS structure composed of III-V nMOSFET and Ge pMOSFET In order to realize this CMOS structure, however, there are still many technological issues to be solved for realizing Ge/III-V MOSFETs on Si substrates, which are listed as follows [5, 6]; (1) high quality Ge/III-V film formation on Si substrates (2) gate insulator formation with superior MOS/MIS interface quality (3) low resistivity S/D formation (4) total CMOS integration. In this study, particularly, we focus on the possible solutions of fabrication technologies for realizing CMOS integration of III-V and Ge MOSFETs on the same wafer. Gate Stack Formation The gate stack formation is a critical issue for III-V/Ge CMOS integration. A common gate stack structure is preferable for simplicity of integration. In the present integration process, we have employed Al2O3 gate insulators for both InGaAs and Ge MOSFETs. It is well known that MOS interfaces between III-V materials and gate insulators include a large number of interface states and interface defects, making the MOS interface control important for III-V MOS gate stacks. A recent important finding in the III-V MOS interface control is the effectiveness of ALD Al2O3 deposition [9-11] for suppressing the interface defects. We have also confirmed that the combination of InGaAs and ALD Al2O3 can lead to superior MOS interface properties [12], often attributed to the cleaning effect of tri-methyl-aluminum (TMA) on InGaAs surfaces [9, 10]. Also, it has been reported that sulfur (S) passivation [13, 14], typically realized by immersing InGaAs epiwafers into (NH4)2S solutions, can improve the Al2O3/InGaAs MOS interface properties. Fig. 2 shows typical C-V characteristics of Au/Al2O3/InGaAs MOS capacitors with the sulfur treatment, fabricated by ALD Al2O3 at 200 ºC [15].

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0.6 Au/Al2O3/InGaAs 0.5 w/ S with Sulfur 0.4 Treatment 0.3 0.2

1 kHz 10 kHz 100 kHz 1 MHz

0.1 0 -2

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Fig. 2. C-V characteristics of Au/Al2O3/InGaAs MOS capacitors with sulfur treatment On the other hand, the interface properties of Al2O3/Ge MOS gate stacks are not necessarily excellent. However, we have recently realized Al2O3/GeOx/Ge MOS gate stacks with low Dit and thin equivalent oxide thickness (EOT) by employing ALD thin Al2O3 and subsequent plasma oxidation [16-20]. A novel plasma post-oxidation method has been proposed to form an Al2O3/GeOx/Ge gate stack by using ECR oxygen plasma through a thin ALD Al2O3 layer, as shown in Fig. 3. While we have already reported that GeO2/Ge interfaces can provide low interface state density (Dit) [21, 22] and high electron [23, 24] and hole mobility [25, 26], the previous results were taken from devices with quite thick GeO2 films formed by thermal oxidation. In contrast, the Ge gate stack with GeOx interfacial layers formed by the present post-oxidation method has simultaneously realized both thin EOT of ~1 nm and low Dit of < 1011 cm-2eV-1. It has been reported [18-20] that the Al2O3/GeOx/Ge pMOSFETs with 1.4-, 1.2- and 0.27-nmthick GeOx interfacial layers (ILs) have exhibited the peak mobilities of 515, 466 and 401 cm2/Vs, respectively. Actually, the Ge pMOSFET with EOT of 0.98 nm has realized around 1.8 time enhancement against the general decreasing trend of the hole mobility in this thin EOT range, reported in the previous studies. Consequently, this technology allows us to use Al2O3-based gate stacks for both InGaAs and Ge channels in the integration process of InGaAs/Ge CMOS. Plasma O2

O2

Al2O3

Al2O3

Ge

Ge

GeOx

O2

GeO2 IL

Fig. 3. Novel Al2O3/GeOx/Ge gate stack formation process by using oxygen plasma through a thin ALD Al2O3 layer S/D Formation Another concern in the integration process of III-V and Ge MOSFETs is S/D formation. We would consider that metal S/D scheme can be the best solution for III-V/Ge CMOS. This is partly because (1) low dopant solubility in III-V materials is an essential issue (2) ion implantation is difficult for III-V materials owing to the damage and thermal stability

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of III-V (3) modulation doping and in-situ doping of re-growth S/D, which are common for III-V FETs, lead to complicated processes and additional extension resistance. Furthermore, doping by ion implantation is not preferred for ultrathin body (UTB), fin or nano-wire structures, which are mandatory for future scaled MOSFETs, because of difficulties in re-crystallization of implanted regions and conformal doping. These limitations make the metal S/D structure a promising alternative.

(b)

(a)

Fig. 4. Schottky barrier height of (a) Ge [27] and (b) InGaAs [28] The Schottky barrier height (SBH) for S/D metals is a strong concern for realizing high performance metal S/D MOSFETs. Sufficiently low SBH for electrons and holes is needed for high current drive of n- and p-MOSFETs, respectively. It is well known that Ge and III-V materials have strong Fermi level (EF) pinning at metal-semiconductor interfaces. Fig. 4(a) shows the experimental results of metal/Ge SBH reported by A. Dimoulas [27]. Fig. 4(a) shows the EF level position at metal/Ge interfaces is strongly pinned near the valence band edge, which is the charge neutral position of Ge. This pinned position is almost independent of the metal species, leading to quite low SBH against holes. This nature makes Ge channels suitable for metal S/D p-MOSFETs. The Schottky barrier of III-V materials is known to depend on III-V materials. However, the pinning position of the EF level position at metal/III-V interfaces is still strongly correlated with the charge neutral position. It has been reported in InGaAs system, as shown in Fig. 4(b), [28] that the surface EF level has an almost constant position from the vacuum level, while the conduction band edge decreases with an increase in the indium content from GaAs toward InAs. These facts indicate that SBH for electrons decreases monotonically with an increase in the In content and can be reduced down to zero, suggesting that InGaAs, particularly with high In contents, has quite low SBH of electrons and, thus, is suitable for metal S/D n-MOSFETs. As a result, metal S/D structure is quite promising for CMOS with InGaAs nMOSFETs and Ge pMOSFETs. The formation of metal S/D demands a self-aligned formation process like silicide S/D in Si CMOS. For Ge, there are many reports on MOSFETs with metal-germanide S/D. Particularly, NiGe metal S/D has been intensively studied by many groups [29-34]. It has been reported that NiGe can be formed by rapid thermal annealing at least at 200 ºC and the excellent Ge p-MOSFETs with NiGe S/D can be realized. We have recently revealed that the that Ni- and Co-InGaAs alloys formed by direct reaction of InGaAs with Ni and

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Co, respectively, can be material systems allowing us to fabricated self-aligned metal S/D structures for InGaAs MOSFETs [35-40]. We have also confirmed that the same process is applicable to InP [41] and GaSb [42]. It has been found that the Ni-InGaAs alloy layers exhibited low sheet resistance of around 25 Ω/square, which is lower by 1/3 than that of InGaAs layers doped with n-type impurities up to the solid solubility (~80 Ω/square). Also, it has been confirmed that Ni can be selectively etched by HCl solution without etching the Ni-InGaAs alloy, allowing us to employ the salicide-like self-aligned metal S/D formation process.

Barrier height for electron [eV]

Another important issue on metal S/D MOSFETs is to realize low SBH between S/D metal materials and channels. While SBH of Ni-InGaAs/InGaAs interfaces is expected to be low, further lower SBH values are preferable. The experimental results of SBH between Ni-InGaAs and InGaAs as a function of the indium content are shown in Fig. 5(a). We have confirmed that SBH of almost 0 eV is obtained at Indium content of 0.7 and 0.8, indicating that the SBH engineering utilizing InGaAs channels with higher indium contents is promising [35-40]. We have employed this technique to ultrathin body InGaAs/InAs-OI channels [37-40], for which metal S/D is mandatory. The schematic fabrication flow is shown in Fig. 5(b). We have confirmed excellent performance of the ETB MOSFET with channel thickness down to 3 nm, because of low resistance and low thermal budget Ni-InGaAs metal S/D. We have applied this technique to UTB InGaAs/InAs-OI channels [37-40], for which metal S/D is mandatory. We have confirmed excellent performance of the UTB MOSFET with channel thickness down to 3 nm, because of low resistance and low thermal budget Ni-InGaAs metal S/D. 0.4 0.3 0.2

As-deposited o

RTA at 250 C for 1min

0.1 0 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Indium content

Ni for S/D Ta In0.7Ga0.3As

Ta In0.7Ga0.3As

Si

Si

Ni-InGaAs Ta

Si

Fig. 5. (a) Indium content dependence of electron SBH of as-deposited Ni/InxGa1-xAs and Ni-InGaAs/InxGa1-xAs with RTA at 250oC for 1min (b) Fabrication process of selfaligned InGaAs-OI MOSFETs with metal S/D structure using Ni–InGaAs alloys III-V-OI Channel Formation The high quality III-V channel formation on the Si platform is very challenging. We have employed the direct wafer bonding (DWB) process of InGaAs/InP wafers with Si

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substrates for fabricating the In0.53Ga0.47As-on-Insulator substrates [43-51]. ECR-plasma SiO2 [43, 44, 47, 50] and ALD Al2O3 films [45-49, 51] have been used as buried-oxide (BOX) layers. Fig. 6 shows a schematic illustration of the DWB process flow of III-V-OI on Si wafers with an ALD-Al2O3 BOX layer. This process is based on the hydrophilic DWB using hydrophilic surfaces of ALD Al2O3 layers and low-temperature annealing after bonding wafers. Here, we can precisely control the thickness of the BOX layers, because the bonded Al2O3 layers are used as BOX layers. As a result, we can realize the UTB III-V-OI on Si wafers with the Al2O3 UTBOX layers without any serious damage. ALD-Al2O3 deposition

Al2O3 InGaAs

Al2O3

InP(001) Si(001)

Pre-bonding annealing

Al2O3 InGaAs

Bonding

Al2O3

InP(001) Si(001)

Post-bonding InP annealing removing

InP(001)

InP(001)

InGaAs Al2O3

InGaAs Al2O3

InGaAs Al2O3

Si(001)

Si(001)

Si(001)

Fig. 6. Process flow of a III-V-OI on Si wafer with an ALD-Al2O3 BOX layer. The detail of the DWB process is as follows. First, the UTB InGaAs layers were grown on the 2-inch (001) InP wafers with etching sacrifice layers (ESLs) by metalorganic vapor phase epitaxy. The ELSs contributed to realize the UTB InGaAs transfer with the excellent uniformity. After pretreatment of InGaAs surfaces using NH4OH and (NH4)2Sx solutions, Al2O3 layers were deposited on both wafers by ALD. Then, the wafers were manually bonded in air, followed by post-bonding annealing. The InP substrates were removed by highly selective wet-etching with a HCl solution. The ELSs were etched with H3PO4:H2O2:H2O and HCl solutions, resulting in the UTB InGaAs-OI on Si wafers. Fig. 10 shows a cross-sectional TEM micrograph of the bonded interface [49, 51]. The 3.2-nm-thick InGaAs-OI layer shows excellent uniformity and smooth and abrupt interfaces. The thickness of the UTBOX layer was approximately 7.7 nm. We could not find any serious damage in the UTB InGaAs-OI layers, indicating that the developed DWB process is suitable for fabricating the UTB III-V-OI on Si wafers. We have fabricated the InGaAs-OI n-MOSFETs under front-gate configuration [46, 48]. Here, an InGaAs-OI structure with 100-nm-thick InGaAs-OI channels and 11-nm-thick ALDAl2O3 BOX was used. A 13-nm-thick Al2O3 was used as a gate oxide. The S/D regions were formed by standard Si ion implantation. We have found the maximum electron mobility of ~3000 and ~2000cm2/Vs for i- and p-InGaAs-OI, respectively, meaning that the present InGaAs/Al2O3/Si bonding substrates have immunity against the high temperature process, at least up to 600 ºC. We have also demonstrated ultrathin-body (3.5 and 9 nm) InGaAsOI MOSFETs on Si substrates with Al2O3 ultrathin BOX layers fabricated by the direct wafer bonding [49, 51]. 3.5-nm-thick UTB InGaAs-OI MOSFETs under the double-gate operation have exhibited the Ion/Ioff ratio and the S factor of approximately 107 and 150 mV/dec, respectively. Also, Ioff as low as 0.1 pA/μm was realized. CMOS Integration By employing the technologies describe above, we have recently demonstrated successful integration of InGaAs-OI nMOSFETs and Ge p-MOSFETs on a same wafer and their

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superior device performance [52, 53]. In order to realize the integration of III-V/Ge MOSFETs and examine the feasibility of proposed integration processes, we have bonded III-V substrates with Ge substrates as a preliminary work. An ALD Al2O3 gate insulator and Ta metal gate were used for common gate stacks for InGaAs and Ge. This is because ALD Al2O3 can provide good MOS interfaces with InGaAs as well as Ge under post ECR plasma oxidation. Also, self-align Ni-Ge and Ni-InGaAs, which can be formed simultaneously for InGaAs nMOSFETs and Ge pMOSFETs, were used as the metal S/D regions. In addition, symmetric Vth InGaAs/Ge CMOS based on TaN metal gate and metal S/D has also been proposed as another possible option of the InGaAs/Ge CMOS integration [54].

Fig. 7. Fabrication process flow of III-V/Ge CMOS with InGaAs-OI nMOSFETs and Ge pMOSFETs with Ni-based metal S/D on the InGaAs-OI-on-Ge wafer. We have fabricated InGaAs-OI nMOSFETs and Ge pMOSFETs with Ni-based metal S/D using the fabricated InGaAs-OI-on-Ge wafers with 20-, 50-, and 100-nm-thick InGaAs layers. The schematic flow of the III-V/Ge CMOS common fabrication process is shown in Fig. 7. After pretreatment of the InGaAs surfaces by NH4OH and (NH4)2Sx solutions, a 90-cycle Al2O3 layer was deposited as a gate insulator by ALD. Next, the InGaAs n-channel areas were isolated using a HCl:H2O2:H2O solution, and the areas of the Ge pMOSFETs were opened. Here, we used the Al2O3 BOX layer as a gate insulator for Ge pMOSFETs, which was prepared by plasma post-oxidation as described above. Next, a Ta metal gate was formed by sputtering and dry-etching, followed by post metallization annealing at 350 ºC. Subsequently, 30-nm-thick Ni was sputtered on the InGaAs layer and the Ge substrate in order to form the Ni-InGaAs and Ni-Ge metal S/D. Ni-InGaAs and Ni-Ge require similar reaction temperatures for the alloy formation [35, 55, 56] which makes a one-step S/D formation process possible. Ni-based metal S/D for both InGaAs and Ge was formed by annealing at 250 ºC for 1 min, followed by selective wet-etching using a HCl solution to remove the unreacted Ni.

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Ge wafer

Ta Gate

InGaAs layer

5 μm Ni-InGaAs S/D

Ni-Ge S/D

Fig. 8. Top-view of III-V/Ge CMOS transistors. Here, the right and left transistor is an InGaAs-OI nMOSFET with Ni-InGaAs S/D and a Ge pMOSFET with Ni-Ge S/D, respectively.

InGaAs nMOSFET

Ge pMOSFET

Fig. 9. Cross-sectional TEM photos of III-V/Ge CMOS transistors. Here, the left and right photos are in Ge pMOSFET and InGaAs nMOSFET regions, respectively. Fig. 8 shows a top-view micrograph of the fabricated InGaAs-OI nMOSFET with NiInGaAs metal S/D and the Ge pMOSFET with Ni-Ge metal S/D on the InGaAs-OI-onGe wafer. We confirmed that the Ni-InGaAs and Ni-Ge metal S/D are formed without any connection with the Ta gate. Fig. 9 shows the cross sectional TEM photos of IIIV/Ge CMOS transistors. Here, the left photograph shows the gate stack region of Ge pMOSFET and the right photograph shows the stack structures of Ta/Al2O3/InGaAs gate stacks on Ge substrates with Al2O3 buried oxides. It has been confirmed that the flat and uniform structures are fabricated by the DWB process. Fig. 10 shows the ID-VD characteristics of a 20-nm-thick InGaAs-OI nMOSFET and a Ge pMOSFET. The normal MOSFET operation is observed for both the InGaAs-OI nMOSFET and the Ge pMOSFET. Fig. 11 shows the electron and hole mobilities of the InGaAs-OI nMOSFETs with InGaAs-OI channel layer thickness of 20, 50, and 100 nm and Ge pMOSFET as a function of surface charge density (μeff − Ns characteristics). The InGaAs-OI nMOSFETs show the higher electron mobility than Si MOSFET regardless of InGaAs-OI channel layer thickness. We have demonstrated the high electron and hole mobilities of 1800 and 260 cm2/Vs and the mobility enhancement against Si of 3.5× and 2.3× for InGaAs-OI nMOSFET and Ge pMOSFET, respectively. The InGaAs-OI nMOSFETs even fabricated on Ge wafers show the higher electron mobility than Si MOSFET regardless of InGaAs-

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OI channel layer thickness with 20 – 100 nm. As a consequence, we have realized high mobilities for both InGaAs-OI nMOSFETs and Ge pMOSFETs even with integrated on a same wafer. -6 -5

D

-3

6

-2 V

-2

1V 4

-1.5 V

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1

I (mA/mm)

I (mA/mm)

12 InGaAs-OI nMOSFET 2 V 10

Ge pMOSFET W/L = 100/50 μm

2 2

0

D

Fig. 10. ID–VD characteristics of a Ge pMOSFET and a 20-nm-thick InGaAs-OI nMOSFET. 3000

400

InGaAs-OI nMOSFET

Ge pMOSFET 300

µeff (cm2/Vs)

µeff (cm2/Vs)

50 nm

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20 nm

1000 800

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100 90 Si 80 15 -3 70 Nsub = 7.8x10 cm 60 12 1x10 -2 (a) N (cm )

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sub 12

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1x10

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15

= 3.9x10

-3 13

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N (cm ) s

Fig. 11. µeff − Ns characteristics of (a) Ge pMOSFETs and (b) InGaAs-OI nMOSFETs with InGaAs-OI channel layer thickness of 20, 50, and 100 nm. The InGaAs-OI nMOSFETs show higher electron mobilities than Si MOSFETs regardless of InGaAs-OI channel layer thickness. Conclusions The critical issues and the key technologies for realizing integration of Ge/III-V-based channel MOSFETs on the Si platform have been addressed. As key technologies for the process integration of InGaAs nMOSFETs and Ge pMOSFETs, we have introduced Al2O3/GeOx/Ge gate stack technology using ECR plasma post oxidation and Ni-based self-aligned metal S/D technologies for both InGaAs and Ge. Actually, the integration of InGaAs(-OI) nMOSFETs and Ge pMOSFETs on a Ge substrate has been successfully presented by employing these process technologies as well as ALD-Al2O3 DWB technique and Ta/Al2O3 metal-gate/high-k gate-stacks. The mobility of both n and pMOSFETs is more than twice higher than those of the Si MOSFETs. The developed CMOS fabrication processes can open up a way to realize the ultimate CMOS structure.

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Acknowledgments This work was partly supported by a Grant-in-Aid for Scientific Research (No. 23246058) from MEXT, and Innovation Research Project on Nano electronics Materials and Structures, and Research and Development Program for Innovative Energy Efficiency Technology from NEDO. The authors would like to thank Drs. T. Yasuda, T. Maeda, W. Jevasuwan, N. Miyata, Y. Urabe and H. Takagi in AIST, Drs. M. Hata, T. Osada, O. Ichikawa, and N. Fukuhara in Sumitomo Chemical, and Dr. H. Yokoyama in NTT for their collaborations. References 1. International Technology Roadmap for Semiconductors (ITRS) 2012 Edition, http:// http://www.itrs.net/Links/2012ITRS/Home2012.htm 2. S. Takagi, T. Irisawa, T. Tezuka, T. Numata, S. Nakaharai, N. Hirashita, Y. Moriyama, K. Usuda, E. Toyoda, S. Dissanayake, M. Shichijo, R. Nakane, S. Sugahara, M. Takenaka, and N. Sugiyama, IEEE Trans. Electron Devices, 55, 21, (2008). 3. S. Takagi, Nikkei Micro Devices, vol. 22, No. 8, 54 (2005). 4. S. Takagi, T. Tezuka, T. Irisawa, S. Nakaharai, T. Numata, K. Usuda, N. Sugiyama, M. Shichijo, R. Nakane, S. Sugahara, Solid-State Electron., 51, 526 (2007) . 5. S. Takagi and M. Takenaka, IEEE Symp. on VLSI Technol., 147 (2010). 6. S. Takagi and M. Takenaka, ECS Trans. 35 (3), 279 (2011). 7. A. Nainani, S. Raghunathan, D. Witte, M. Kobayashi, T. Irisawa, T. Krishnamohan, K. Saraswat, IEEE Int. Electron Device Meeting, 857 (2009). 8. Z. Yuan, A. Nainani, A. Kumar, X. Guan, B. R. Bennett, J. B. Boos, M. G. Ancona and K. C. Saraswat, IEEE Symp. on VLSI Technol., 185 (2012). 9. M. M. Frank, G. D. Wilk, D. Starodub, T. Gustafsson, E. Garfunkel, Y. J. Chabal, J. Grazul, and D. A. Muller, Appl. Phys. Lett., 86, 152904 (2005). 10. M. L. Huang, Y. C. Chang, C. H. Chang, Y. J. Lee, P. Chang, J. Kwo, T. B. Wu, and M. Hong, Appl. Phys. Lett., 87, 252104 (2005). 11. Y. Xuan, H. C. Lin, P. D. Ye, and G. D. Wilk, Appl. Phys. Lett., 88, 263518 (2006). 12. T. Yasuda, N. Miyata, Y. Urabe, H. Ishii, T. Itatani, H. Takagi, H. Yamada, N. Fukuhara, M. Hata, A. Ohtake, M. Yokoyama, T. Hoshii, T. Haimoto, M. Deura, M. Sugiyama, M. Takenaka, and S. Takagi, Mater. Res. Soc. Symp. Proc., 1194, A08-0701~12 (2010). 13. Y. Xuan, Y. Q. Wu, T. Shen, T. Yang and P. D. Ye, IEEE Int. Electron Device Meeting, 637 (2007). 14. Y. Urabe, N. Miyata, H. Ishii, T. Itatani, T. Maeda, T. Yasuda, H. Yamada, N. Fukuhara, M. Hata, M. Yokoyama, N. Taoka, M. Takenaka and S. Takagi, IEEE Int. Electron Device Meeting, 142 (2010). 15. R. Suzuki, N. Taoka, M. Yokoyama, S.-H. Kim, T. Hoshii, T. Maeda, T. Yasuda, O. Ichikawa, N. Fukuhara, M. Hata, M. Takenaka and S. Takagi, J. Appl. Phys. 112, 084103 (2012). 16. R. Zhang, T. Iwasaki, N. Taoka, M. Takenaka and S. Takagi, Appl. Phys. Lett., 98, 112902 (2011). 17. R. Zhang, T. Iwasaki, N. Taoka, M. Takenaka and S. Takagi, IEEE Symp. on

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