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Impact of HfTaO Buffer Layer on Data Retention Characteristics of Ferroelectric-Gate FET for Nonvolatile Memory Applications Minghua Tang, Xiaolei Xu, Zhi Ye, Yoshihiro Sugiyama, and Hiroshi Ishiwara, Fellow, IEEE
Abstract—A p-channel metal–ferroelectric–insulator–silicon field-effect transistor (FET) with a 300-nm-thick SrBi2 Ta2 O9 (SBT) ferroelectric film and a 10-nm-thick HfTaO layer on silicon substrate was fabricated and characterized. The device shows a nearly unchanged memory window of about 0.9 V after a 2 × 1011 -cycles fatigue test, an on/off current ratio of more than 107 , and a field-effect mobility of approximately 42 cm2 /V · s. Moreover, a drain-current on/off ratio as high as 105 was obtained with a fixed gate voltage of 2.5 V after over a 105 -s elapsed time without any obvious degradation. These results may suggest that the Pt/SBT/HfTaO/Si FET is suitable for high-performance ferroelectric memory. Index Terms—Data retention, ferroelectric field-effecttransistor (FeFET), HfTaO, memory window, metal–ferroelectric– insulator–silicon (MFIS), SrBi2 Ta2 O9 (SBT).
I. I NTRODUCTION
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ONVOLATILE memories are extensively used in modern integrated circuits. Recently, ferroelectric field-effect transistors (FeFETs) with a metal–ferroelectric–insulator– silicon (MFIS) structure have attracted considerable attention as promising high-density and high-speed nonvolatile memories
Manuscript received May 29, 2010; revised September 15, 2010 and October 28, 2010; accepted October 29, 2010. Date of publication December 10, 2010; date of current version January 21, 2011. This work was supported in part by the Key Project of the National Natural Science Foundation of China (NSFC) under Grant 10732100, by the NSFC under Grant 60876054 and Grant 51072171, by Hunan Provincial NSFC under Grant 08JJ3122, by the Natural Science Foundation of the Hunan Province for Innovation Group under Grant 09JJ7004, by the Project of the Scientific and Technological Department of the Hunan Province under Grant 2010FJ3029, and by the Scientific Research Foundation for the Returned Overseas Chinese Scholars, State Education Ministry. The review of this paper was arranged by Editor S. Deleonibus. M. Tang is with the Key Laboratory of Low-Dimensional Materials and Application Technology of the Ministry of Education, Xiangtan University, Hunan 411105, China, and also with the Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology, Yokohama 226-8503, Japan (e-mail:
[email protected]). X. Xu is with the Key Laboratory of Low Dimensional Materials and Application Technology of the Ministry of Education, Xiangtan University, Hunan 411105, China (e-mail:
[email protected]). Z. Ye is with the Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Kowloon, Hong Kong (e-mail:
[email protected]). Y. Sugiyama is with Fujitsu Laboratories, Kanagawa 243-0197, Japan (e-mail:
[email protected]). H. Ishiwara is with the Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology, Yokohama 226-8503, Japan (e-mail:
[email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2010.2090883
due to their superior characteristics such as having a singledevice structure, a simple process flow, a low power consumption, and, in particular, a nondestructive readout operation [1]– [6]. High-κ gate dielectrics have been investigated for replacing SiO2 for further scaling down of CMOS devices. However, mobility degradation and electrical instability are two key obstacles for the high-κ dielectrics to be integrated into the conventional CMOS process. In the case of the MFIS FET, a very thin insulating layer, which is the buffer layer, is expected to prevent the chemical reaction and/or the interdiffusion of the atoms between the ferroelectric film and the silicon substrate and to improve the interface and retention properties [7]. Even so, high-quality MFIS FETs with good retention properties have been found arduous to be fabricated because of the difficulty in selecting appropriate ferroelectric and dielectric materials [8]–[10]. Recently, a kind of gate dielectric material of HfTaO thin film has been found to be very promising as the buffer layer for future MFIS-FET applications due to its relatively high crystallization temperature, suitable dielectric constant, low interfacial-state density and charge trapping, and good electrical stability [11]–[14]. In this paper, we report on the fabrication and the characterization of ferroelectric-gate thinfilm transistors (TFTs) with a Pt/SiBi2 Ta2 O9 (SBT)/HfTaO/Si structure, in which the HfTaO thin film is used as the buffer layer and SBT is used as the ferroelectric gate. Our observations on the memory window, the electrical properties, and the retention characteristics indicate that the MFIS FET with Pt/SBT/HfTaO/Si structures may be promising for the next generation of nonvolatile-memory applications. II. E XPERIMENTS Fig. 1(a) shows the diagram of a fabricated p-channel MFIS FET. A p-channel MOSFET structure without the electrodes was first fabricated as the substrate using a conventional local oxidation of the silicon process by Fujitsu Laboratories Ltd., Japan. Their channel length L and width W are 10 and 50 μm, respectively. Before fabricating the gate stack, the substrates were treated by a buffered hydrofluoric-acid solution in order to remove the original gate insulator. A HfTaO film approximately 10 nm in thickness was first deposited as a buffer layer on the substrate by using a ultrahighvacuum electron beam (EB) method. A stoichiometric HfTaO tablet with the nominal atomic ratio of Hf : Ta = 0.6 : 0.4 was adopted as an evaporation source and heated using an EB gun
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Fig. 1. (a) Schematic illustration of the Pt/SBT/HfTaO/Si MFIS FET. (b) P –E hysteresis loops of the 300-nm-thick SBT film under various applied voltages from 2 to 10 V. (c) C–V measured at 1 MHz and (d) I–V characteristics of Al/HfO2 /p-Si(100) MIS diode.
to deposit HfTaO films on the substrate. The pressure in the vacuum chamber during the deposition was around 10−7 torr, and the substrate was kept at room temperature (RT). The film thickness was in situ, observed by a crystal thickness monitor attached in the chamber, and the typical growth rate was around 0.01 nm/s. These were followed by the postdeposition annealing, which was carried out at 800 ◦ C for 10 min in the oxygen flow for improving the interface properties. The SBT ferroelectric film was then deposited after the formation of a HfTaO buffer layer. A commercially available 8 wt.% precursor solution with 20% Sr-deficient and 10% Biexcess composition Sr0.8 Bi2.2 Ta2 O9 (0.33 mol/kg) was spin coated at 3500 r/min for 20 s. The coated film was dried by using a hot plate at 240 ◦ C for 3 min in the air in order to remove the organic materials and was successively fried using a rapid thermal annealing furnace at 750 ◦ C for 1 min, with a heating rate of 100 ◦ C/s in the oxygen flow (1 L/min). These processes were repeated 6 times until the total thickness of the coated film approaches about 300 nm. Then, the SBT film was crystallized by using a rapid thermal annealing furnace at 750 ◦ C for 30 min in the oxygen flow (1 L/min). Finally, the Pt film with a 80-nm thickness was deposited by a radio-frequency sputtering system at RT using the Pt target in the Ar atmosphere, and the Pt top electrodes were formed by etching a uniform film using a reactive ion etching (RIE) apparatus with Ar and Cl2 gases. The area of the fabricated top electrodes is 50 × 45 μm2 . Via holes for the source and
drain contacts were opened by successive processes of wet chemical treatment with a mixed solution of 50% hydrofluoric acid and 36% hydrochloric acid, and the RIE using the Ar and Cl2 mixture gas. In the next step, Al electrodes for gate, drain, and source terminals were patterned by a lift-off process. The samples were sintered at 450 ◦ C for 5 min in the N2 flow in order to decrease the contact resistance. III. R ESULTS AND D ISCUSSION Fig. 1(b) shows the polarization–electric field (P –E) characteristics of the SBT film fabricated by sol–gel spin technique on Pt/Ti/SiO2 /Si(100) substrates. The well-saturated hysteresis loops were found under various electric fields. A remanent polarization Pr of ∼ 7 μC/cm2 measured at 10 kHz under the 200-kV/cm external electric field was also observed, which is enough for the ferroelectric-gate FET application. Fig. 1(c) demonstrates the C–V characteristic of the Al/HfTaO(10 nm)/p-Si(100) MIS diode measured at 1 MHz. The well-behaved C–V curve with a negligible hysteresis loop caused by the charge-injection and ion-drift effects was observed during the forward-and-reverse voltage sweeping from +4 to −4 V. The interface-trapped density Dit is estimated to be about 3.63 × 1010 /eVcm2 , and the capacitance equivalent thickness without quantum mechanical corrections calculated from the accumulation capacitance of the sample is 3.5 nm, as indicated in Fig. 1(c). These results imply that the charge
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transistor characteristics with the drain-current saturation can be clearly observed from Fig. 2(b). The drain current ID increases with either increasing the drain voltages VDS or increasing the gate voltage. The ON-state current of −2.5 mA was obtained with the −4-V gate voltage and the −4-V drain voltage, which is comparable to the value (1.2 mA when VG = 4 V at VD = 4 V, n-channel MFIS FET, W = 120 μm, and L = 40 μm) reported by Miyasako et al. [16]. The field-effect mobility μ is a critical parameter of the MFIS FET, and it can be derived using the equation in the saturation region, i.e., IDS =
Fig. 2. Electrical properties of the MFIS FET with (a) transfer characteristics demonstrated by ID –VGS and (b) output characteristics demonstrated by ID –VDS .
traps are absent in the annealed film and the interface property between the HfTaO buffer layer and the Si substrate is excellent [15]. As shown in Fig. 1(d), the leakage current density of the HfTaO sample at ±4 V is about 10−6 A/cm2 , which is much smaller than that of a 3.5-nm-thick SiO2 film (about 2 × 10−2 ∼ 1 A/cm2 under a ±4-V external applied voltage in our experiment) and is very helpful for the performance improvement. Fig. 2(a) illustrates the typical drain current–gate voltage ID – VGS characteristics (transfer characteristics) of the fabricated MFIS FET with the SBT/HfTaO gate structure. In this measurement, an applied drain voltage VDS was fixed at −0.5 V, while the gate voltage here is swept from +4 to −4 V and then returns to +4 V. The ID –VGS characteristics show a clockwise hysteresis loop due to the polarization reversal in the ferroelectric films. Fig. 2(a) clearly shows a memory-window width around 0.9 V and a drain current on/off ratio as high as 107 . The derived subthreshold slope is about 145 mV/dec, indicating the good device performance on the leakage-current and switching characteristics [7]. Fig. 2(a) also highlights the variations in the ID –VGS characteristics before and after the fatigue test. The excellent fatigue characteristics of the SBT/HfTaO sample can be inferred from the slight shift of the ID –VGS curve before and after applying 2 × 1011 pulses (square-shaped bipolar pulses 4 V in amplitude and 1 MHz in frequency). Fig. 2(b) shows the ID –VDS characteristics of the MFIS FET. VDS was swept from 0 to −4 V, and VGS changed from 0 to −4 V with a −1-V increment. Typical p-channel
Ci μW (VG − VT )2 2L
(1)
where Ci is the equivalent capacitance per unit area of the gate insulator, VT is the threshold voltage, W is the channel width, and L the channel length. Due to the nonlinear characteristics of the P –E curve in the SBT ferroelectric thin film as shown in Fig. 1(b), the Ci in (1) can be equivalently given by P (VG )/VG , where P (VG ) is the ferroelectric polarization as a function of the gate voltage. Note that the applied gate voltage of −4 V induced a drain current of −2.5 mA, the thickness of ferroelectric-gate insulator is around 300 nm, and the applied electric field to the ferroelectric is 130 kV/cm, which results in a polarization of 6 μC/cm2 according to the P –E characteristics shown in Fig. 1(b). Using these values [P (VG ) = 6 μC/cm2 and VG = 4 V], together with a drain current of 2.5 mA and device parameters (W = 50 μm and L = 10 μm), and assuming the threshold voltage VT = 0 V, we have estimated that the field-effect mobility of the device is about 42 cm2 /V · s. This value is comparable with that of the TFTs with a conductive oxide channel [16]. Fig. 3(a) shows the typical data retention characteristics of the fabricated MFIS FET at RT. It is noticed that a drain current was continuously monitored after applying a single 1-μs-wide WRITE pulse to the gate terminal and the applied gate voltage was fixed at +2.5 V during the retention measurement. The expression of “ON-state” and “OFF-state” represents the variation of the drain current after applying WRITE pulses of −10 and +10 V, respectively. We observed that the reduction of the drain-current on/off ratio is very small even after over 105 s have elapsed at RT and the drain-current on/off ratio larger than 105 is obtained at 24 h after the WRITE operation. Furthermore, a simple extrapolation of the currents implies that the data will be retained for a time period longer than 10 years (3 × 108 s). In order to verify the stress endurance and the hightemperature stability on the retention properties of the FeFET, we carried out both the fatigue test at RT and the hightemperature test at 85 ◦ C after the 2 × 1011 -cycles stress endurance for 24 h, as shown in Fig. 3(b) and (c). As we can see, there is no significant deterioration in the three samples, and the Ion /Ioff ratios at 24 h are 3.3 × 105 (at RT before cycling), 1.65 × 105 (at RT after 2 × 1011 cycles), and 5.83 × 102 (at 85 ◦ C after 2 × 1011 cycles), respectively. The important electrical properties of the MFIS transistors in the literatures are summarized in Table I. Fig. 3(d) shows the WRITE pulsewidth dependence of the drain current of the manufactured device. In this experiment, single pulses with various widths ranging
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Fig. 3. Retention characteristics of the Pt/SBT/HfTaO/Si MFIS FET at (a) RT before cycling (initial condition), (b) RT after 2 × 1011 cycles, and (c) 85 ◦ C after 2 × 1011 cycles. (d) W RITE pulsewidth dependences of the drain currents with the amplitude of +10 or −10 V.
TABLE I P UBLICATION OF THE MFIS T RANSISTORS
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[5]
[6]
[7]
[8]
[9] Fig. 4. Endurance characteristics of the threshold voltage changes of the MFIS FET after 1 MHz ± 4 V writing with different switching cycles.
from 10−7 to 10−4 s and two amplitudes of +10 and −10 V were applied to the sample. The drain current was measured at approximately 100 s after the WRITE operation with a fixed gate-bias voltage of +2.5 V. As observed in Fig. 3(d), the current on/off ratio almost remains unchanged for the WRITE pulsewidth narrower than 10−5 s but starts to increase for those with wider widths. We also found that a WRITE pulsewidth as short as 30 ns is enough to obtain a large drain-current on/off ratio over 102 . The endurance characteristics of the MFIS FET demonstrated by the threshold voltage VT changes at RT are shown in Fig. 4. The ON - and OFF-state VT values before and after switching cycles are determined from the ID –VGS hysteresis loops under a cycle condition of ±4 V at 1 MHz. The memory window exhibits a slight reduction from 1.1 to 0.9 V after 2 × 1011 cycles.
[10]
[11]
[12]
[13]
[14]
[15]
IV. C ONCLUSION In summary, the electrical properties of the p-channel MFIS FET with the Pt/SBT/HfTaO/Si gate structure have been investigated. The observations of a memory window of 0.9 V and a maximum drain-current on/off ratio of approximately 107 as extracted from ID –VGS measurements have been reported. It has been also shown that the fabricated device exhibits excellent endurance characteristics, a high-temperature stability, and a good drain-current on/off ratio of about 105 after a 24-h dataretention test before cycling at RT. These results indicate that HfTaO is probably one of the most promising candidates used as the buffer layer for realizing FET-type ferroelectric random access memories with long data-retention time and high-speed operation.
[16]
[17]
[18] [19]
[20]
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[23] A. Gerber, M. Fitsilis, R. Waser, T. J. Reece, E. Rije, S. Ducharme, and H. Kohlstedt, “Ferroelectric field effect transistors using very thin ferroelectric polyvinylidene fluoride copolymer films as gate dielectrics,” J. Appl. Phys., vol. 107, no. 12, pp. 124 119-1–124 119-4, Jun. 2010. [24] S.-M. Yoon, S.-H. Yang, S.-W. Jung, C.-W. Byun, S.-H. K. Park, C.-S. Hwang, G.-G. Lee, E. Tokumitsu, and H. Ishiwara, “Impact of interface controlling layer of Al2 O3 for improving the retention behaviors of In–Ga–Zn oxide-based ferroelectric memory transistor,” Appl. Phys. Lett., vol. 96, no. 23, pp. 232 903-1–232 903-3, Jun. 2010.
Minghua Tang received the B.S. degree in physics and the Ph.D. degree in materials physics and chemistry from Xiangtan University, Hunan, China, in 1988 and 2007, respectively. He is with the Faculty of Materials, Optoelectronics, and Physics, Xiangtan University, and is currently a Visiting Professor with the Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology, Japan, focusing on the fabrication and the characteristics of ferroelectric thinfilm memory. He is currently supporting a team of 16 postgraduate students to work on ferroelectric thin-film memory and advanced silicon-on-insulator devices. His research interests include integrated-circuit design, ferroelectric thin-film memory, and other advanced complementary metal–oxide–semiconductor devices.
Xiaolei Xu was born in Shandong, China, in 1984. He is currently working toward the M.S. degree in the Faculty of Materials, Optoelectronics, and Physics, and the Key Laboratory of LowDimensional Materials and Application Technology, Xiangtan University, Ministry of Education, Xiangtan, China. His current research interests include ferroelectric thin-film memory devices, and properties and simulation of advanced complementary metal–oxide– semiconductor devices.
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Zhi Ye was born in Hunan, China, in 1982. He received the B.S. degree in measurement and control technology and instrument and the M.S. degree in microelectronic technology from Xiangtan University, Hunan, China, in 2004 and 2007, respectively. He is currently working toward the Ph.D. degree in the Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Kowloon, Hong Kong. His research interests include novel thin-film transistor structure and methods of fabrication.
Yoshihiro Sugiyama received the B.S., M.S., and Ph.D. degrees in electronic engineering from Tohoku University, Sendai, Japan, in 1982, 1985, and 2000, respectively. In 1985, he joined Fujitsu Laboratories Ltd., Atsugi, Japan. From 1985 to 2000, he was engaged in the research of quantum effect devices with III-V materials. Since 1999, he has started to develop Si process technologies including SiGeC, high-k gate dielectrics, and PZT thin films. His recent interests include nonvolatile memories for system-on-a-chip and device modeling of complementary metal–oxide–semiconductor. Dr. Sugiyama is a member of the Japan Society of Applied Physics, and the Institute of Electronics, Information and Communication Engineers (IEICE) of Japan. He was the recipient a Paper Award from the IEICE of Japan in 1993.
Hiroshi Ishiwara (F’01) was born in Yamaguchi, Japan, in 1945. He received the B.S., M.S., and Ph.D. degrees in electronic engineering from Tokyo Institute of Technology, Tokyo, Japan, in 1968, 1970, and 1973, respectively. He was a Research Associate from 1973 to 1976 and an Associate Professor from 1976 to 1989 with the Tokyo Institute of Technology, where he has been a Professor since 1989. In 2004 and 2005, he was the Dean of Professor with the Interdisciplinary Graduate School of Science and Engineering. His research interests are in the areas of device and process technologies in integrated circuits, and at present, he is particularly concerned with ferroelectric memories. Dr. Ishiwara was the recipient of the Purple Ribbon Medal by the Japanese Government in 2003 and the Certificate of Merit by the Deputy Prime Minister and Minister of Science and Technology, Korea, in 2007. He is a Fellow of the Institute of Electronics, Information, and Communication Engineers, and he was the President of the Japan Society of Applied Physics in 2008 and 2009.
