Impact of Inductance on the Performance of Single ... - IEEE Xplore

2013 International Symposium on Electronic System Design

Impact of Inductance on the Performance of Single Walled Carbon Nanotube Bundle Interconnects Manodipan Sahoo

Hafizur Rahaman

Bhargab Bhattacharya

Department of Information Technology Department of Information Technology Advanced Computing and Microelectronics Unit Bengal Engineering & Science University Bengal Engineering & Science University Indian Statistical Institute Shibpur, Howrah-711103, India Shibpur, Howrah-711103, India Kolkata-700108, India Email: [email protected] Email: rahaman [email protected] Email: [email protected]

the model (i.e., distributed RC intead of RLC) and thus reducing the computation time without losing the accuracy severely. Single Walled Carbon Nanotube (SWCNT) bundle interconnects are reported to be one of the potential solutions to conventional Copper (Cu) interconnects [7], [8]. In this work, we investigate the impact of inductive effects in SWCNT bundle interconnects. For the investigation we consider both sparse (metallicity=1/3) and dense (metallicity=1) bundles for all levels of interconnects i.e., local, intermediate and global and technology nodes of 21 nm and 15 nm. Interconnect dimensions are derived from latest ITRS-2011 data [3]. It is shown that for a 100 MHz input square wave with 10 ps rise time, inductive effects are not affecting the interconnect delay. Inductive effects mainly plague the performance for long intermediate and global interconnects. It is quantitatively shown that inductive effects will have severe impact in future nanoscale SWCNT bundle interconnects due to faster (i.e., lower rise time) signals. It is also observed that Elmore based delay estimation leads to only 5.46% error in estimating the actual delay at the worst case. So for the chosen conditions, Elmore based methods can be used to model the delay without degrading the accuracy severely but with tremendous improvement in simulation time. The rest of the paper is organized as follows. In Section II, equivalent electrical parameters have been discussed for SWCNT bundle interconnects. Section III discusses the ABCD parameter matrix based approach for delay modelling of SWCNT bundle interconnects. Section IV focusses on results. In this section, we investigate the impact of inductance on the performance of various types of SWCNT bundle interconnects in various technology nodes and levels of interconnects. Lastly the conclusions are drawn in Section V.

Abstract—In this work, we have studied the inductive properties of interconnects built with Single Walled Carbon Nanotube (SWCNT) bundle. We have used the most recent ITRS-2011 data while estimating the RLC parameters of SWCNT bundle interconnects. In our analysis, we have used the classical ABCD-parameter-matrix based method and a delay allowance of 50%. Simulations are performed for both sparse and dense SWCNT bundle interconnects at 21 nm and 15 nm technology nodes, considering three levels of their application: local, intermediate, and global. It is observed that for a 100 MHz periodic square wave input with a rise time of 10 ps, SWCNT bundle interconnects are not impacted by inductance. It is shown that for the given input signal and SWCNT bundle parameters, the length over which the inductive effects will be more prominent, has little practical significance. It is quantitatively shown that the inductive effects will mostly impact the long-intermediate and global interconnects. With technology scaling, such effects may worsen the performance. It is also observed that the Elmore-based methodology for delay estimation of SWCNT bundle interconnects predicts the actual delay very accurately with a maximum error of only 5.46%. Keywords—Single Walled Carbon Nanotube (SWCNT); Interconnect delay; ABCD-parameter; Technology scaling; Elmore delay model.

I. I NTRODUCTION Modern IC’s performance is severely impacted by interconnects due to the dominance of interconnect delay over gate delay. With the continuous shrinking of feature sizes, the clock frequency increases, separation between adjacent interconnects decreases, signal edge rates become faster. Moreover, because of the higher operational frequencies and lower resistivity copper interconnects, inductive impedance of the on-chip wires become comparable to or larger than the resistive impedance. Due to these reasons, on chip capacitive and inductive effects have enormous effects on the signal integrity and performance of today’s copper (Cu) based nano-interconnects [1], [2]. Again, the resistivity of copper increases in the nanometric regime due to surface and grain boundary scattering [3], which deteriorates the performance of especially long intermediate and global interconnects. So, conventional approaches of the lumped or distributed RC model of the interconnects are not adequate for delay prediction especially in intermediate and global wires in the nanometer regime [4]. The distributed RLC line has been considered in [5] to model the performance of today’s high speed interconnects. This approach is very accurate but also computationally intensive. In [6], authors have defined some Figures of merits (FOMs) which are functions of input signal rise time, bundle RLC parameters and interconnect length, to quantify the impact of inductance on the performance of a distributed RLC line. Basically a range of interconnect lengths will only be impacted by inductive effects thus needing very accurate modeling of the line. So based on these FOMs, it is possible to loosen

II.

INTERCONNECTS

In this section, we model interconnects using Single Walled Carbon Nano Tube (SWCNT) bundles. The equivalent circuit of SWCNT was first proposed in [9]. The circuit parameters are explained below. A. Equivalent RLC Parameters of SWCNT bundle The schematic of a SWCNT bundle interconnect structure is shown in Fig.1, where w and t are width and thickness of the interconnect respectively. The number of SWCNTs along x and z √ and Nh = 2(t−d) + 1. where, axis can be expressed as, Nw = (w−d) x 3x d is the diameter of SWCNT and x is the inter-CNT distance. Here we consider both densely packed (metallicity=1) and sparsely packed (metallicity=1/3) CNT bundle. Total number of CNTs in a bundle is

This work is partially supported by the DIT, Government of West Bengal, India under VLSI Design Project.

978-0-7695-5143-2/13 $26.00 © 2013 IEEE DOI 10.1109/ISED.2013.10

E LECTRICAL EQUIVALENT MODEL OF SWCNT BUNDLE

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Inter CNT distance

Infinitesimal section of a distributed line

=x

Net1

Net2

Vi1

Net3

Isolated CNT

I

net1 I

i1

r.dx

o1

Vo1

l.dx C eq .dx

z y x

s

d

s

t w

w

ht

Fig. 3: Schematic diagram of an infinitesimal section of a SWCNT bundle interconnect system.

w

Ground Plane

Fig. 1: SWCNT Bundle structure.

VIN

TABLE I: RC parameters of the buffer for various technology nodes

hhh hhTechnology hhh node Parameters hh h

Equivalent RC circuit of the Inverting Buffer Distributed Line of length L Lumped Resistance Rf Rf Rs r.dx l.dx Vout C q .dx

Cout

C e .dx

C

Rs (in KΩ) Cout (in fF)

dx : infinitesimal section length Inverting Buffer

Fig. 2: Electrical equivalent model of a typical SWCNT bundle interconnect system.

expressed as follows [8], Nh , if Nh is even 2 (Nh − 1) , if Nh is odd = Nw N h − 2

(1a)

NSW CN T

(1b)

15 nm

34.45 0.049

47.4 0.03

I. Distributed RLC parameters for both sparse and dense SWCNT bundles for 21 nm and 15 nm technology nodes and various levels of interconnects are tabulated in Table II-IV. The infinitesimal section of the distributed RLC line is shown in Fig. 3. Here, dx is the length of the infinitesimal section and Ceq is the p.u.l series equivalent capacitance of the bundle and it is expressed C C as, Ceq = (Cqq+Cee ) . The Kirchhoff equation for an infinitesimally small segment of this interconnect is given as φi = P φo where, φi = [Vi1 , Ii1 ]T and φo = [Vo1 , Io1 ]T . Matrix P is shown in (2), – » 1 (r + sl)dx (2) P = 1 sCeq dx

L

NSW CN T = Nw Nh −

21 nm

The matrix P can be diagonalized as P=V W V −1 , where, » – Z −Z V = 1 1

A SWCNT bundle consists of parallel combination of a number of CNTs. Electrical equivalent model of a typical SWCNT bundle interconnect system is shown in Fig. 2. Here, the driver is implemented using inverting buffers and load is capacitive, denoted by CL . The buffers can be modeled as an equivalent RC circuit with a high degree of accuracy [5]. Rs and Cout are the equivalent switching resistance and the equivalent diffusion capacitance of a minimum sized inverter buffer. Rf is the lumped resistance consisting of both metal-nanotube imperfect contact resistance (RC ) and quantum resistance (RQ ) and (RC +RQ ) . The per unit length (p.u.l) it is represented as, Rf = 2 resistance (r) and inductance (l) of the SWCNT bundle as shown RCN T LCN T and l = NSW . in the figure are expressed as, r = NSW CN T CN T Where, RCN T consists of only the distributed Ohmic resistance component (RO ) and LCN T consists of both the kinetic inductance (LK ) and magnetic inductance (LM ) component. Cq and Ce are the p.u.l quantum and electrostatic capacitances of the SWCNT bundle. Cq is denoted as Cq = CQ .NSW CN T [8]. Where, CQ is the quantum capacitance of an isolated SWCNT. We use an online field solver CNIA (Carbon Nanotube Interconnect Analyzer) [10] to estimate the p.u.l electrostatic ground capacitance of the bundle, Ce .

and, W is a diagonal matrix shown as in (3), » – (1 + θdx) 0 W = 0 (1 − θdx)

(3)

Here, θ is the propagation constant and Z is the characteristic impedances of the bundle interconnect. These parameters are qdefined p (r+sl) . as follows, dx = L/n, θ = s(Ceq )(r + sl) and Z = s(Ceq ) Here, n is the number of infinitesimal sections. Using, P n = (V W V −1 )n = (V W n V −1 ) and the identity, limn→+∞ (1+ nx )n → ex , P n can be written as shown in (4), – » ta Z.tb (4) P n = tb ta Z where, ta is cosh(Lθ) and tb is sinh(Lθ). Here, Pdr , Pdc are the ABCD matrices of the driving buffer and PRf , Pload are that of the lumped resistance (Rf ) and capacitive load respectively. The final Kirchoff equation for the coupled interconnects can be written as, Φi = Pdr Pdc PRf P n PRf Pload Φo . By solving this equation, the final output voltage Vo1 (s) can be represented in terms of the input Vi1 (s) in matrix form as, [Vo1 (s)] = [H1 (s)][Vi1 (s)]. The exact expression of H1 (s) is shown in (6), where, A = (1 + sRs Cout ) e expansion and B = (Rs + ARf ). We consider a seventh-order Pad´ for approximating hyperbolic functions in (6) with high degree of accuracy [5]. So the transfer function H(s) will be of the form given

III. ABCD PARAMETER BASED D ELAY MODEL A typical SWCNT bundle interconnect system of length L with the distributed RLC parameters r, l, Cq and Ce are shown in Fig.2. Rs and Cout for various technology nodes are shown in Table

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H1 (s)

=

1 (A(1 + sCL Rf ) + sCL B) cosh(θL) + ( B (1 + sCL Rf ) + AsCL Z) sinh(θL) Z

TABLE II: Bundle RLC parameters for local and intermediate level interconnects

```

``` Technology node ``(Bundle Type) ``` RLC parameters ` ` Lumped Resistance (in Ω) Kinetic inductance(in μH/m) Quantum capacitance(in nF/m) Electrostatic capacitance(in pF/m)

21 nm (sparse) 348.7 13.63 57.32 31.1

21 nm (dense) 115.1 4.5 173.7 55.4

15 nm (sparse) 661.7 25.86 30.21 28.9

TABLE IV: Bundle distributed Resistance parameter (in MΩ/m) for various levels of interconnects

XXX

15 nm (dense) 218.24 8.53 91.6 54.8

Length

``` Technology node ``(Bundle Type) ``` RLC parameters ` ` Lumped Resistance (in Ω) Kinetic inductance(in μH/m) Quantum capacitance(in nF/m) Electrostatic capacitance(in pF/m)

21 nm (sparse) 67.73 2.647 295.1 34.2

21 nm (dense) 22.36 0.874 894.1 57.4

15 nm (sparse) 135.4 5.294 147.6 30.5

Technology node

XXX (Bundle XXType) XX

1 μm (Local) 10 μm (Intermediate) 100 μm (Global)

15 nm (dense) 44.71 1.747 447.2 55.7

Performance parameters

Length

50 % delay(in ns)

1 μm 3 μm 5 μm 8 μm 10 μm 1 μm 3 μm 5 μm 8 μm 10 μm 1 μm 3 μm 5 μm 8 μm 10 μm

50 % Elmore Delay(in ns)

in (5) after the Pad´ e expansion:

% error = Delay 100×(1- Elmore ) Delay

1 1 + sb1 + s2 b2 + s3 b3 + s4 b4 + s5 b5 + s5 b5 + s6 b6 + s7 b7 (5) where, the coefficients are shown below,

H(s) =

2 r2 Ceq L4 lCeq L2 + ) + L(Rs Rf Ceq Cout + Rf Ceq CL (Rs + Rf ) 2 24 rCeq L3 (rCL + Ceq (Rs + Rf )) + rRs CL Cout + lCL ) + 6

(

+ 2Rf CL ) +

2 r2 Ceq L4 lCeq L2 + )(Rs Cout + Rs CL 2 24

rCeq L3 (Rs Rf Ceq Cout + Rf Ceq CL (Rs + Rf ) + rRs CL Cout 6 2 r2 Ceq L5 lCeq L3 + )(rCL + Ceq (Rs + Rf )) + lCL ) + ( 6 120 2 Ceq L4

b7 =

r lCeq L + 2 24

)(2Rs Rf Cout CL ) + 2

21 nm (dense) 0.255 0.256 0.257 0.258 0.258 0.255 0.256 0.257 0.258 0.258 0 0 0 0 0

15 nm (sparse) 0.422 0.425 0.427 0.431 0.433 0.422 0.425 0.427 0.431 0.433 0 0 0 0 0

15 nm (dense) 0.36 0.361 0.362 0.364 0.365 0.36 0.361 0.362 0.364 0.365 0 0 0 0 0

2 L5 l2 Ceq (Rs Ceq CL Rf2 Cout + lRs Cout CL ) 120

IV. R ESULTS AND D ISCUSSIONS The proposed analytical model is implemented using MATLAB 7.1 under standard desktop environment running an Intel Core 2 Duo Chip at 3.0 GHz with 4.0 GB of physical memory. The simulation is performed in various technology nodes namely 21 nm and 15 nm and various interconnect levels. The inverter buffer size chosen here is 100 times and 50 times the minimum sized buffer for global and intermediate interconnects respectively. The capacitive load considered is 100 fF for all the simulations. SWCNT bundles considered are consisting of 1 nm fixed diameter sparse SWCNTs (with metallicity=1/3) and dense SWCNTs (with metallicity=1) with

2 rlCeq L4

) 12 3 l rCeq L (Rs Cout + Rs CL + 2Rf CL ) + )+ 24 6 2 r2 Ceq L5 lCeq L3 2 + ) (Rs Ceq CL Rf Cout + lRs Cout CL ) + ( 6 120 (Rs Rf Ceq Cout + Rf Ceq CL (Rs + Rf ) + rRs CL Cout + lCL )+

b4 = (

21 nm (sparse) 0.289 0.29 0.291 0.293 0.295 0.288 0.29 0.291 0.293 0.294 0.346 0 0 0 0.339

2 2 L4 L5 rlCeq l2 Ceq )(Rs Rf Cout CL ) + (Rs Ceq CL Rf2 Cout + 12 60 2 L5 l2 Ceq (Rs Rf Ceq Cout + Rf Ceq CL (Rs + Rf )+ lRs Cout CL ) + 120 rRs CL Cout + lCL )

2 L4 rlCeq ) + L(Rs Ceq CL Rf2 Cout + lRs Cout CL ) 24

2

15 nm (dense) 9.503 5.673 1.081

b6 =

+

2

15 nm (sparse) 28.81 17.2 3.275

2 2 rlCeq L4 L4 l2 Ceq (Rs Rf Cout CL ) + )(Rs Cout + 6 24 2 2 3 r Ceq L5 lCeq L + )(Rs Ceq CL Rf2 Cout + Rs CL + 2Rf CL ) + ( 6 120 2 L5 rlCeq lRs Cout CL ) + (Rs Rf Ceq Cout + Rf Ceq CL (Rs + Rf )+ 60 2 2 l Ceq L5 (rCL + Ceq (Rs + Rf )) rRs CL Cout + lCL ) + 120

rCeq L2 (Rs Cout + Rs CL + 2Rf CL )+ 2

b3 = rCeq L2 (Rs Rf Cout CL ) + (

21 nm (dense) 5.011 2.992 0.541

b5 =

L2 rCeq +(Rs Cout +Rs CL +2Rf CL )+L(rCL +Ceq (Rs +Rf )) b1 = 2 b2 = 2Rs Rf Cout CL +

21 nm (sparse) 15.19 9.066 1.6376

TABLE V: SWCNT bundle performance parameters for Local level interconnects (With inductance)

TABLE III: Bundle RLC parameters for global level interconnects

```

(6)

2 Ceq L4

2 rlCeq L5 (rCL + Ceq (Rs + Rf )) 60

18

TABLE VI: SWCNT bundle performance parameters for Local level interconnects (Without inductance) Performance parameters

Length

50 % delay(in ns)

1 μm 3 μm 5 μm 8 μm 10 μm 1 μm 3 μm 5 μm 8 μm 10 μm 1 μm 3 μm 5 μm 8 μm 10 μm



21 nm (sparse) 0.289 0.29 0.291 0.293 0.295 0.288 0.29 0.291 0.293 0.294 0.346 0 0 0 0.339

21 nm (dense) 0.255 0.256 0.257 0.258 0.258 0.255 0.256 0.257 0.258 0.258 0 0 0 0 0

15 nm (sparse) 0.422 0.425 0.427 0.431 0.433 0.422 0.425 0.427 0.431 0.433 0 0 0 0 0

TABLE VIII: SWCNT bundle performance parameters for Intermediate level interconnects (Without inductance)

15 nm (dense) 0.36 0.361 0.362 0.364 0.365 0.36 0.361 0.362 0.364 0.365 0 0 0 0 0

Length

50 % delay(in ns)

10 μm 50 μm 100 μm 500 μm 1 mm 10 μm 50 μm 100 μm 500 μm 1 mm 10 μm 50 μm 100 μm 500 μm 1 mm



21 nm (sparse) 0.103 0.128 0.159 0.426 0.807 0.103 0.127 0.158 0.42 0.789 0 0.781 0.629 1.41 2.23

21 nm (dense) 0.066 0.076 0.087 0.193 0.352 0.066 0.075 0.087 0.188 0.339 0 1.32 0 2.59 3.69

15 nm (sparse) 0.17 0.216 0.274 0.774 1.48 0.17 0.215 0.273 0.764 1.45 0 0.463 0.365 1.29 2.09

Length

50 % delay(in ns)

10 μm 50 μm 100 μm 500 μm 1 mm 10 μm 50 μm 100 μm 500 μm 1 mm 10 μm 50 μm 100 μm 500 μm 1 mm



21 nm (sparse) 0.103 0.128 0.159 0.426 0.807 0.103 0.127 0.158 0.42 0.789 0 0.781 0.629 1.41 2.23

21 nm (dense) 0.066 0.076 0.087 0.193 0.351 0.066 0.075 0.087 0.188 0.339 0 1.32 0 2.59 3.42

15 nm (sparse) 0.17 0.216 0.274 0.774 1.48 0.17 0.215 0.273 0.764 1.45 0 0.463 0.365 1.29 2.09

15 nm (dense) 0.101 0.117 0.139 0.332 0.624 0.1 0.117 0.138 0.325 0.603 0.99 0 0.719 2.11 3.37

TABLE IX: SWCNT bundle performance parameters for Global level interconnects (With inductance)

TABLE VII: SWCNT bundle performance parameters for Intermediate level interconnects (With inductance) Performance parameters


15 nm (dense) 0.101 0.117 0.139 0.332 0.624 0.1 0.117 0.138 0.325 0.603 0.99 0 0.719 2.11 3.37


Length

50 % delay(in ns)

100 μm 500 μm 1 mm 1.5 mm 2 mm 100 μm 500 μm 1 mm 1.5 mm 2 mm 100 μm 500 μm 1 mm 1.5 mm 2 mm



21 nm (sparse) 0.046 0.102 0.18 0.27 0.37 0.046 0.1 0.175 0.26 0.355 0 1.96 2.78 3.7 4.05

21 nm (dense) 0.033 0.057 0.093 0.135 0.183 0.033 0.056 0.09 0.129 0.173 0 1.75 3.23 4.44 5.46

15 nm (sparse) 0.077 0.182 0.332 0.501 0.69 0.076 0.179 0.324 0.486 0.665 1.3 1.65 2.41 2.99 3.62

15 nm (dense) 0.049 0.094 0.16 0.238 0.327 0.049 0.091 0.154 0.227 0.31 0 3.19 3.75 4.62 5.2

interconnects. For 21 nm technology node, maximum of 5.46% error is observed for a dense 2 mm long SWCNT bundle, whereas, the error reduces to 5.2% for the same type of bundle in 15 nm node. Thus we may conclude that for the applied input signal, Elmore based methodology very accurately estimates the delay of a SWCNT bundle interconnect. To understand the impact of inductance for delay estimation, we have tabulated various parameters in Table XI-XIII. These parameters are used to define the range of interconnect lengths over which inductance affects the performance severely [6]. The inequality showing the range of lengths over which the inductance effects will be prominent is shown as below, s l 2 tr p 4l r ´ ` observed . From from the tables that tr is always greater than the parameter 4l r the tables it is seen that, longer interconnects for any level is more prone to inductive effects than shorter ones. Also global interconnects are more impacted by inductance than intermediate and local ones. Interestingly we observe that the impact of inductance is independent

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TABLE X: SWCNT bundle performance parameters for Global level interconnects (Without inductance) Performance parameters 50 % delay(in ns)



Length

21 nm (sparse) 0.046 0.101 0.18 0.269 0.37 0.046 0.1 0.175 0.26 0.355 0 0.99 2.78 3.35 4.05

100 μm 500 μm 1 mm 1.5 mm 2 mm 100 μm 500 μm 1 mm 1.5 mm 2 mm 100 μm 500 μm 1 mm 1.5 mm 2 mm

21 nm (dense) 0.033 0.057 0.093 0.135 0.183 0.033 0.056 0.09 0.129 0.173 0 1.75 3.23 4.44 5.46

15 nm (sparse) 0.076 0.182 0.332 0.501 0.69 0.076 0.179 0.324 0.486 0.665 0 1.65 2.41 2.99 3.62

TABLE XII: Parameters to investigate the importance of inductance for Intermediate level interconnects Technology node

15 nm (dense) 0.049 0.093 0.16 0.237 0.327 0.049 0.091 0.154 0.227 0.31 0 2.15 3.75 4.22 5.2

(Bundle type) 21 nm (Sparse) 21 nm (Dense) 15 nm (Sparse) 15 nm (Dense)

(Bundle type) 21 nm (Sparse)

TABLE XI: Parameters to investigate the importance of inductance for Local level interconnects Technology node (Bundle type) 21 nm (Sparse) 21 nm (Dense) 15 nm (Sparse) 15 nm (Dense)

Length 1 μm 10 μm 1 μm 10 μm 1 μm 10 μm 1 μm 10 μm

2

lCeq

(in μm) 243 243 317 317 183 183 231 231

2 r

q

l Ceq

(in μm) 87.2 146 114 190 65.7 110 83 139

10 μm 1 mm 10 μm 1 mm 10 μm 1 mm 10 μm 1 mm

√tr

2

lCeq

(in μm) 243 243 317 317 183 183 231 231

2 r

q

l Ceq

(in μm) 146 158 190 206 110 119 139 151

4l r

(in ps) 6.01 6.51 6.01 6.52 6.01 6.51 6.01 6.51

TABLE XIII: Parameters to investigate the importance of inductance for Global level interconnects Technology node

√tr

Length

21 nm (Dense)

4l r

15 nm (Sparse)

(in ps) 3.59 6.01 3.59 6.01 3.59 6.01 3.59 6.01

15 nm (Dense)

Length 100 μm 2 mm 100 μm 2 mm 100 μm 2 mm 100 μm 2 mm

√tr

2

lCeq

(in μm) 526 526 706 706 393 393 507 507

2 r

q

l Ceq

(in μm) 340 342 456 460 254 256 328 330

4l r

(in ps) 6.46 6.52 6.46 6.52 6.47 6.52 6.46 6.52

actual delay more accurately and the error in delay estimation is only 5.46% at the worst case. R EFERENCES [1]

E. E. Davidson, B. D. McCredie, and W. V. Vilkelis, ”Long lossy lines (L3 ) and their impact upon large chip performance,” IEEE Trans. Components, Packaging and Manufacturing Technology, Part B: Advanced Packaging, vol. 20, pp. 361-375, Nov. 1998. [2] C. K. Cheng, J. Lillis, S. Lin, and N. Chang, Interconnect Analysis and Synthesis. New York: Wiley, 1999. [3] International Technology Roadmap for Semiconductors (ITRS-2011) Reports, [Online]. Available: http://www.itrs.net/reports.html. [4] Deutsch, A. et. al., “When are transmission line effects important for on-chip interconnections”, IEEE Trans. Microwave Theory Tech., vol. 45, pp. 1836-1846, Oct. 1997. [5] Banerjee, K. et. al., “Analysis of On-Chip Inductance Effects for Distributed RLC Interconnects”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, pp. 904-915, Aug. 2002. [6] Y. I. Ismail, E. G. Friedman and J. L. Neves, “Figures of merit to characterize the importance of on-chip inductance”, IEEE Trans. on VLSI Systems, vol. 7, no. 4, pp. 442-449, Dec. 1999. [7] A. Naeemi and J. D. Meindl, “Design and performance modeling for single-walled carbon nanotubes as local, semiglobal, and global interconnects in gigascale integrated systems,” IEEE Trans. Electron Devices, vol. 54, no. 1, pp. 26-37, Jan. 2007. [8] N. Srivastava and K. Banerjee, “Performance analysis of carbon nanotube interconnects for VLSI applications”, Proc. IEEE/ACM ICCAD, pp. 383390, Nov. 2005. [9] P. J. Burke, “Luttinger Liquid Theory as a Model of the Gigahertz Electrical Properties of Carbon Nanotubes”, IEEE Trans. Nanotechnology, vol. 1, No. 3, pp. 129-144, Mar. 2002. [10] Carbon Nanotube Interconnect Analyzer tool[Online]. Available:http://www.nanohub.org/tools/

of bundle type and technology node here. The reason behind this is because the bundle inductance and resistance are equally impacted by bundle type and technology node. It is observed from the tables that for the input signal rise time of less than 6.52 ps, 2 mm long global ` ´ interconnects will be severely impacted by inductance. The ratio rl for a SWCNT bundle is independent of feature size because p.u.l resistance is a feature size independent quantity for a fixed diameter and temperature and also the dominant inductance here being the kinetic inductance, it is also a feature size independent quantity. Thus with scaling signal rise times become lesser and it may be concluded that the inductive effects will become more prominent for SWCNT bundle interconnects in future IC technology nodes. V. C ONCLUSIONS In this work, we have studied the impact of inductance on the performance of Single Walled Carbon Nanotube (SWCNT) bundle interconnects. ABCD parameter matrix based method is used to analytically model the performance of a SWCNT bundle based interconnect system. Simulations have been performed for both sparse and dense SWCNT bundles at 21 nm and 15 nm technology nodes and all levels of interconnects viz. local, intermediate and global. It has been observed that for a 100 MHz periodic square wave input with a rise time of 10 ps, SWCNT bundle interconnects are not impacted by inductance. It has been shown that for the chosen input signal and SWCNT bundle parameters, the region of length over which the inductive effects are more prominent does’nt exist at all. It has been quantitatively shown that the inductive effects would impact long intermediate and global interconnects the most. With technology scaling, the inductance is expected to have more impact on the performance. Also it has been observed that Elmore based methodology for delay estimation of SWCNT bundle predicts the

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