2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
Impact of Synthesis Constraints on Error Propagation Probability of Digital Circuits Daniel B. Limbrick1 , Student Member, IEEE, Suge Yue2 , William H. Robinson1 , Senior Member, IEEE, and Bharat L. Bhuva1 , Senior Member, IEEE 1
Department of Electrical Engineering and Computer Science Vanderbilt University, Nashville, TN {daniel.b.limbrick, william.h.robinson, bharat.l.bhuva}@vanderbilt.edu 2
Bejing Microelectronics Technology Institute, Beijing, China suge
[email protected] Abstract
Optimization algorithms for the synthesis of digital logic circuits have been used to automate the process of meeting design constraints like area and timing. These algorithms affect a circuit’s topology and therefore its vulnerability to soft errors. This paper investigates the impact that these optimizations have on the error propagation probability of various circuit benchmarks. Results indicate that a decrease in delay and area corresponds with an increase in error propagation probability. Additionally, an increase in mapping effort corresponds to an increase in error propagation probability. Keywords logic synthesis, constraint optimization, logical masking, error propagation probability, combinational logic, soft error.
I. I NTRODUCTION Radiation-induced soft errors are becoming a dominant reliability-failure mechanism in modern CMOS technologies [1]. In nanometer technologies, the effects are not limited to the storage elements of a digital system, but also include vulnerabilities in the combinational logic [2]. The overall soft error rate (SER) of the circuit is based upon the formulations described in [3]: (1) the nominal SER for individual library cells under static conditions (i.e., electrical masking), (2) the timing vulnerability factor (TVF) for logic paths between sequential elements (i.e., latch-window masking), and (3) the architectural vulnerability factor (AVF) for the functionality of the circuit block (i.e., logical masking). Ultimately, designers are concerned with meeting the overall SER for the digital system while minimizing the impact of radiation-hardening techniques. Several methods that incorporate the various masking factors have been proposed to model and evaluate SER, such as the SERA tool [4], the SEAT-LA tool [5], the SERD algorithm [6], the MARS-C tool [7], and the MARS-S tool [8]. Each method essentially examines a synthesized circuit described as a netlist. Although the circuit parameters of the netlist (e.g., gate sizes [9]) could be modified to reduce SER, the original topology of the circuit can have inherent vulnerabilities from the cascading of different library cells. Also, circuit-level techniques can impose drastic area, power, or delay penalties if used throughout the design without regard to the circuits functionality. A reliability-aware logic synthesis is needed to choose among the various library cells to leverage the circuit-level mitigation strategies for soft errors [10]. Mitigation during logic synthesis can reduce the baseline SER of the design and does not preclude the use of other techniques [11], such as radiation-hardened latches and gates, temporal or spatial redundancy, error detection and correction (EDAC) circuitry, or triple modular redundancy (TMR). This paper analyzes the approach of combining both logic synthesis and SER evaluation to mitigate the effects of radiation events on high-level designs. Using various circuit benchmarks, we show that a given circuit has a characteristic distribution of logical sensitivity which remains relatively unchanged for different synthesis constraints. However, different synthesis constraints will map the logical sensitivity onto different circuit topologies. Our analysis also shows that tightly constrained timing optimizations will impact the error propagation probability for a given circuit. Contributions of this work include: (1) comparative analysis of the impact of area-constrained vs. timing-constrained synthesis implementations on error propagation probability, (2) analysis of the impact on error propagation probability of varying the map effort setting of a synthesis tool, (3) analysis of the impact on error propagation probability of incrementally increasing delay constraints, (4) analysis of the impact on error propagation probability of removing cells from the cell library, and (5) extension of the set of error propagation probability equations presented by Asadi and Tahoori [12]. Extensions of this work include: (1) error rate predictions of standard cells and common cell chains and (2) methods for standard cell library construction (i.e., cell inclusion, cell removal, or cell enhancement) that incorporate soft error considerations. 1550-5774/11 $26.00 © 2011 IEEE DOI 10.1109/DFT.2011.46
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The remainder of this paper is organized as follows. A survey of related work is provided in Section II. The calculation of error propagation probability is explained in Section III. Section IV describes the details of the study. The simulation and synthesis results are presented and discussed in Section V. Section VI provides a summary of this work. II. R ELATED W ORK Several methods that incorporate the various masking factors have been proposed to model and evaluate SER for an individual node [4-8]. Once the vulnerable nodes of a circuit are identified, the impact of soft errors can be mitigated using techniques during synthesis. The majority of existing techniques modify optimization steps that are traditionally used to reduce area, power, or delay of a circuit, in order to reduce circuit SER. A survey of common techniques are discussed in this section. Rewiring is an optimization technique that involves removing a wire from a circuit design that violates a constraint and transforming the remaining logic to be functionally equivalent to the original circuit. Almukhaizim et al. employed a rewiring method based on Automatic Test Pattern Generation (ATPG) to generate functionally-equivalent yet structurally-different implementations of a logic circuit based on simple transformation rules [13]. The results showed that the SER of a circuit could be reduced through topological transformations without impacting area, power, or timing constraints. This method only dealt with the logic level and does not take advantage of technology-specific design characteristics. Krishnaswamy et al. [14] improved circuit SER by using two circuit modification techniques: don’t-care-based re-synthesis and local rewriting. Observability-don’t-cares (ODCs) are logical input values that do not impact the output node. The study uses the ODC information to characterize the vulnerability of nodes, then uses pre-existing redundant logic (as identified by the ODCs) to harden highly vulnerable nodes. Logic rewriting is a synthesis optimization technique that involves replacing subcircuits in a design with smaller subcircuits that are functionally equivalent [15]. Krishnaswamy et al. modified this technique to replace subcircuits that optimize for area and reliability simultaneously. Both techniques were limited to the solution that produced the most logical masking and did not account for electrical or latch-window masking. Rao et al. [16] showed that cells with higher drive strengths increase attenuation of SET pulses. By optimizing combinational logic for reliability through selective gate-sizing, Rao et al. show that the overall SER of a circuit can be reduced up to 30.1X while accruing an area overhead of 46% and no delay penalties. This result is significant in showing that in addition to gate-sizing as an effective method in reducing SER, it can be automated to consider pre-existing cells in a library to accomplish this reduction. However, the study provided an algorithm that optimized reliability separately from and following other optimizations and therefore did not consider the impact that previous optimizations had on reliability. III. C ALCULATING E RROR P ROPAGATION P ROBABILITY Error Propagation Probability (EPP) is the likelihood that an error in one component propagates to output of the circuit. This metric represents the logical masking that occurs when an error on a logic gate does not have a direct path to an output node. EPP can be calculated empirically or statistically. It can be calculated empirically by running fault injection simulations to determine the number of input combinations that result in an error by using Equation 1: EP P =
Σ
input combinations that allow an erroneous value from an error site to reach an output node Σ all possible input combinations
(1)
In this method, a bit flip is simulated by using the output fault node with a fault-injection enable bit as inputs to an XOR gate. The output of the XOR gate replaces the fault injection node as the input to the next stage. The output of the circuit is compared to the expected output to see if an error occurred. Exhaustive fault injection using this method becomes an intractable problem for large circuit designs. In this paper, we use the method proposed in [12] to estimate EPP for the ISCAS85 benchmark circuits. This method, which uses system failure probability equations for the AND, OR, and INV logical functions, was tested on ISCAS benchmark circuits with 95% accuracy and was 4 to 5 orders of magnitude faster than random fault injection simulation. The equations for the signal probabilities at the output of the gate in terms of its inputs from [12] are presented in Table I. An expansion of the study by Asadi and Tahoori [12] is necessary to investigate a larger set of cells, including complex functions like “exclusive-or”. The equations for the additional cells used in this study were derived using the basic probabilities of gates [17] and the notion of an signed error signal [12]. An example of this derivation is shown in Fig. 1. With each output case of a logic gate specified, the probability can be calculated by summing the input equations of the cases that produce a particular output. For instance, the probability that the output of an XOR gate is 0 is equal to the probability that both inputs have an error (Case 3) plus the probability that both inputs have the inversion of the original error (Case 7) plus the probability that both inputs equal 0 plus the probability that both inputs equal 1. The extended set of probability equations for each cell in this study has been derived and is provided in Table III. Identifying the corresponding signal
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Table I E QUATIONS FOR COMPUTING PROBABILITY AT THE OUTPUT OF A GATE IN TERMS OF ITS INPUTS [12]
probability for each cell in a cell library should provide an accurate view of the impact on EPP from restricting the use of cells.
Figure 1. Output cases for inputs involving an error (a) or the inverse of an error (¯ a) that was propagated from a previous gate. The inputs of Cases 1, 2, 4, 5, and 6 can be mirrored to produce equivalent cases (not shown).
IV. L OGIC S YNTHESIS AND E VALUATION This section provides an overview of the synthesis tools, cell library, and circuit benchmarks used for this study. The mitigation techniques investigated in this paper are also described. A. Synthesis Using the Cadence RTL Compiler, the ISCAS85 benchmark circuits [18] were synthesized for area and timing information. We used the FreePDK45 [19] cell library developed by the Oklahoma State University VLSI Computer Architecture Group; it consists of 33 cells with a 45-nm transistor size. This library was developed based on the official scalable CMOS (SCMOS) design rules of the Metal Oxide Semiconductor Implementation Service (MOSIS). The FreePDK45 library was chosen because it was an open-source implementation of a current fabrication technology. B. Error Propagation Probability Calculation Tool The tool used to calculate the EPP of each circuit was written in Java. Given a Verilog netlist, the tool recreates the circuit as a directed acyclic graph using the JGraphT library [21]. With this graph, the tool uses the propagation probability equations for the and (AND), or (OR), and inverter (INV) logic gates described in [12] and the equations for the nand
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Table II P ROBABILITY EQUATIONS FOR ADDITIONAL CMOS CELLS
P0 (out) =
n Y
P1 (Xi )
i=1 n
NAND
Pa¯ (out) =
Y
[P1 (Xi ) + Pa (Xi )] − P0 (out)
i=1 n
Pa (out) =
Y
[P1 (Xi ) + Pa¯ (Xi )] − P0 (out)
i=1
P1 (out) = 1 − [P0 (out) + Pa (out) + Pa¯ (out)] P1 (out) =
n Y
P0 (Xi )
i=1 n
NOR
Pa¯ (out) =
Y
[P0 (Xi ) + Pa (Xi )] − P1 (out)
i=1 n
Pa (out) =
Y
[P0 (Xi ) + Pa¯ (Xi )] − P1 (out)
i=1
P0 (out) = 1 − [P1 (out) + Pa (out) + Pa¯ (out)] P0 (out) = P0 (a) × P0 (b) + P1 (a) × P1 (b) + Pa (a) × Pa (b) + Pa¯ (a) × Pa¯ (b) XOR
Pa (out) = Pa (a) × P0 (b) + P0 (a) × Pa (b) + Pa¯ (a) × P1 (b) + P1 (a) × Pa¯ (b) Pa¯ (out) = Pa (a) × P1 (b) + P1 (a) × Pa (b) + Pa¯ (a) × P0 (b) + P0 (a) × Pa¯ (b) P1 (out) = 1 − [P0 (out) + Pa (out) + Pa¯ (out)] P1 (out) = P0 (a) × P0 (b) + P1 (a) × P1 (b) + Pa (a) × Pa (b) + Pa¯ (a) × Pa¯ (b)
XNOR
Pa (out) = Pa (a) × P1 (b) + P1 (a) × Pa (b) + Pa¯ (a) × P0 (b) + P0 (a) × Pa¯ (b) Pa¯ (out) = Pa (a) × P0 (b) + P0 (a) × Pa (b) + Pa¯ (a) × P1 (b) + P1 (a) × Pa¯ (b) P0 (out) = 1 − [P1 (out) + Pa (out) + Pa¯ (out)]
(NAND), nor (NOR), exclusive-or (XOR) and exclusive-nor (XNOR) logic gates described in this paper to calculate the EPP as it traverses the paths. C. Mitigation Techniques In order to determine if certain logic cells have an inherent impact on the EPP of a circuit, multiple benchmark circuits were synthesized with restrictions on the use of certain cells within the cell library. Then, the netlists from these synthesized designs were used as input to the EPP tool. These data enabled an investigation to determine the impact on EPP of: (1) area-constrained vs. timing-constrained implementations, (2) map effort, (3) incrementally increasing delay, and (4) removing cells from the cell library. The mapping effort setting of the Cadence Encounter RTL compiler was studied. This setting allows for circuit designs to be synthesized with low, medium (default) and high map efforts. This attribute corresponds to the exhaustiveness of the search for the optimal circuit implementation. A high map effort configures the compiler to perform the most exhaustive search and consequently, takes the longest to compile. By varying this setting, the impact of mapping effort can be observed. The impact of area-constrained optimizations vs. timing-constrained optimizations was investigated by synthesizing the minimum-area implementation and the minimum delay implementation for each circuit. Optimizations occur through repetitive algorithmic steps which affect the topology of a circuit with uniformity. The optimizations for minimum area differ from those for minimum delay and therefore create different topological patterns. The impact of these patterns can be identified through this investigation. The impact of timing-constrained optimizations was analyzed by synthesizing a circuit with the maximum (i.e., unconstrained) delay, the minimum possible delay, and three intermediate delay values. The step size was determined by dividing the slack between the minimum and maximum delay by four.
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90 80 INV AND OR NAND NOR XOR XNOR
70 60 50 40 30 20
Frequency of Cell Usage (%)
Frequency of Cell Usage (%)
100
10 0
100 90 80 INV AND OR NAND NOR XOR XNOR
70 60 50 40 30 20 10
c432
0
c499 c1355 c1908 c2670 c3540 c5315 c7552
c432
c499 c1355 c1908 c2670 c3540 c5315 c7552
Circuit (a) Area-constrained Figure 2.
Circuit (b) Timing-constrained
Frequency of cell usage for the selected ISCAS85 benchmark circuits.
The impact on EPP of removing cells from a cell library was studied by synthesizing the minimum-area implementation of each circuit while restricting the use of one cell per synthesis. For example, the c432 circuit was synthesized seven times. One implementation was the minimum-area implementation using all cells in the library. The remaining six implementations were synthesized with one of six possible cells (AND, OR, NAND, NOR, XOR, XNOR) removed. The Cadence RTL compiler restricts the use of a cell library that does not contain at least one inverter, therefore the inverter could not be removed. V. A NALYSIS OF B ENCHMARK C IRCUITS The EPP formulas discussed in Section III imply that the overall EPP of the circuit is impacted by the frequency of usage of each gate. For instance, as shown in Fig. 1, a fault on one input bit of a 2-input XOR gate (cases 1, 2, 5, and 6) always results in an error at the output of the XOR gate. However, a fault on one input bit of an 2-input AND gate results in an error at the output of the AND gate in only 50% of cases (when the input bit without the fault is 1). The frequency of usage of each cell is affected by synthesis constraints and optimizations. Fig. 2 shows the frequency of cell usage for the ISCAS85 benchmark circuits when optimized for area and timing. Despite differences in topology among the benchmark circuits studied, clear synthesis trends can be identified. The area-constrained implementations use NAND and NOR cells infrequently while the timing-constrained implementations have a more balanced distribution of cells. Additionally, the area-constrained implementations have a greater frequency of XOR/XNOR cells than the timing-constrained implementations.
Average Error Propagation Probability
0.5
Area Timing
0.4
0.3
0.2
0.1
0
c432
c499 c1355 c1908 c2670 c3540 c5315 c7552
Circuit Figure 3. Error propagation probability average for the selected ISCAS85 benchmark circuits separated by area-constrained and timing-constrained implementations.
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# of Cells with Error Propagation Probability > 0.5
Area Timing
450 400 350 300 250 200 150 100 50 0
c432
c499 c1355 c1908 c2670 c3540 c5315 c7552
Circuit
Figure 4. Number of cells with EPP greater than 0.5 for the ISCAS85 benchmark circuits separated by area-constrained and timing-constrained implementations.
The area-constrained implementations have a higher average EPP than the timing-constrained implementations (Fig. 3). This result is consistent with the frequency of XOR and XNOR cells previously discussed. However the number of cells of the timing-constrained implementations with EPP greater than 0.5 are consistently greater than the number of cells of the area-constrained implementations with EPP greater than 0.5. This result, shown in Fig. 4, implies that timing-constrained implementations contain more high-EPP cells than area-constrained implementations, even when the average EPP is lower. This result is probably due to timing optimizations that create shorter paths throughout the circuit, which increases the probability of an error reaching the output. Additionally, the timing-constrained implementations have nearly twice the frequency of inverters as the area-constrained implementations. Since inverters along a highly-vulnerable path do not logically mask errors, the higher frequency of inverters in timing-constrained implementations could skew both the average EPP and the number of cells with EPP greater than 0.5. Fig. 5 shows the effect of varying map effort during synthesis. For most of the circuits used in this study, the “medium” and “high” map effort produced identical results. The average EPP increases as the map effort increases. The frequency of cell usage does not provide insight because the distribution of cells for the same optimization (in this case, area) does not vary significantly. The increase in EPP could be caused by smaller implementations of a circuit having more vulnerability due to greater fanouts of each gate. Average Error Propagation Probability
0.5
Low Medium High
0.4
0.3
0.2
0.1
0
c432
c499 c1355 c1908 c2670 c3540 c5315 c7552
Circuit Figure 5.
EPP for the selected ISCAS85 benchmark circuits separated by map effort.
Table III shows the results from varying the delay-optimization incrementally from minimum constraint (Timing 1) to maximum constraint (Timing 5). The step size was determined by dividing the slack between the minimum and maximum constraint by 4. The results show that a decrease in delay does not always correspond with an increase in average EPP. It is
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also worth noting that the number of cells with an EPP greater than 0.5 increases steadily with decreasing delay, meaning that even if the average does not increase, the number of highly vulnerable cells is increasing. The trend in the number of cells with an EPP greater than 0.5 differing from the average EPP trend is consistent with the analysis of area-constrained implementations versus timing-constrained implementations. This trend was expected since a design with minimum delay will have shorter paths and therefore less gates for an error to propagate to reach an output. Table III EPP OF C 432 FOR VARYING CIRCUIT DELAY OPTIMIZATIONS
Implementation Timing 1 Timing 2 Timing 3 Timing 4 Timing 5
Cell Count 833 1773 2713 3653 4593
Delay (ns) 268 196 196 181 172
Avg EPP 0.15 0.14 0.14 0.15 0.20
# EPPs above 0.5 25 21 21 18 19
When restricting the cell selection, there was not an identifiable trend in average EPP, however, cell-restricted circuits more often showed an increase in the EPP compared to the original implementation (Fig. 6). The absence of an identifiable trend could be due to the removal of one cell causing an increase in use of the cell’s complement. For instance, removal of the XOR gate caused greater than 30% average increase in XNOR gates used. Since XOR and XNOR have a similar logical vulnerability, the removal of one of these cells should have a marginal impact on EPP.
Average Error Propagation Probability
0.35
None AND OR NAND NOR XOR XNOR
0.3
0.25
0.2
0.15
0.1 c432
c499
c1355
c1908
c2670
c3540
c5315
c7552
Circuit Figure 6. EPP for the selected ISCAS85 benchmark circuits separated by implementations that have one cell restricted during synthesis. There is not a cell that consistently increases or decreases the EPP of a circuit. Additionally, the impact of removing cells is negligible in some circuits (e.g. c5315) and noticeable in other circuits (e.g. c2670).
VI. S UMMARY Modern EDA tools have standard optimizations for area, power, and delay constraints, but incorporating reliability information during synthesis remains a challenge. This paper analyzed the synthesized netlists for several logic circuits to determine their inherent sensitivity to radiation-induced transients. Depending upon the reduction and transformation of the design logic, the synthesis engine will use certain library cells and certain cell chains with a higher frequency. The placement of these cells along the logically sensitive paths influences the overall vulnerability of the design. Timing-constrained implementations contain more highly vulnerable cells than area-constrained implementations. Further analysis is needed to determine if this effect only occurs because of shortened delay paths or if other factors can be identified. Additionally, the increase in map effort correlates to an increase in average EPP. The change in fanout of each gate should
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be analyzed to determine if the increase in average EPP is caused by the increased impact of each gate as the circuit gets smaller. The results for removing a cell from the library indicate that the EPP may increase when removing cells from the library but currently do not reflect a definite trend. Finally, the results for varying a timing-constrained implementation from minimum constraint to maximum constraint show that EPP increases with tighter delay constraints which could be caused by the shortened delay paths. ACKNOWLEDGMENT This work was supported in part by NSF CAREER Award CCF-0747042.
R EFERENCES [1] R. C. Baumann, “Radiation-induced soft errors in advanced semiconductor technologies,” IEEE Transactions on Device and Materials Reliability, vol. 5, pp. 305-316, 2005. [2] M. Santarini, “Cosmic radiation comes to ASIC and SOC design,” in EDN, 2005. [3] S. Mitra, N. Seifert, M. Zhang, Q. Shi, and K. S. Kim, “Robust system design with built-in soft-error resilience,” Computer, vol. 38, pp. 43-52, 2005. [4] M. Zhang and N. R. Shanbhag, “A soft error rate analysis (SERA) methodology,” IEEE/ACM International Conference on Computer Aided Design (ICCAD-2004), San Jose, CA, 2004. [5] R. Rajaraman, J. S. Kim, N. Vijaykrishnan, Y. Xie, and M. J. Irwin, “SEAT-LA: a soft error analysis tool for combinational logic,” 19th International Conference on VLSI Design, Hyderabad, India, 2006. [6] R. Rao, K. Chopra, D. Blaauw, “Computing the soft error rate of a combinational logic circuit using parameterized descriptors,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 3, 468-479, March, 2007 [7] N. Miskov-Zivanov and D. Marculescu, “MARS-C: modeling and reduction of soft errors in combinational circuits,” in 43rd ACM/IEEE Design Automation Conference, pp. 767-772, 2006. [8] N. Miskov-Zivanov and D. Marculescu, “MARS-S: Modeling and Reduction of Soft Errors in Sequential Circuits,” in 8th International Symposium on Quality Electronic Design (ISQED 2007), pp. 893-898, 2007. [9] Q. Zhou and K. Mohanram, “Gate sizing to radiation harden combinational logic,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, pp. 155-166, 2006. [10] S. Tosun, N. Mansouri, E. Arvas, M. Kandemir, and Y. Xie, “Reliability-centric high-level synthesis,” 2005 Design, Automation, and Test in Europe (DATE 2005), Munich, Germany, 2005. [11] M. Nicolaidis, Design for soft error mitigation,” IEEE Transactions on Device and Materials Reliability, vol. 5, no. 3, pp. 405-418, 2005. [12] G. Asadi and M. Tahoori, “An analytical approach for soft error rate estimation in digital circuits,” in IEEE International Symposium on Circuits and Systems, 2005, pp. 2991-2994 Vol. 3, 2005. [13] Sobeeh Almukhaizim, Yiorgos Makris, Yu-Shen Yang, and Andreas Veneris, “Seamless Integration of SER in Rewiring-Based Design Space Exploration,” in IEEE International Test Conference (ITC 2006), pp. 1-9, 2006. [14] S. Krishnaswamy, S. M. Plaza, I. L. Markov, and J. P. Hayes, “Enhancing design robustness with reliability-aware resynthesis and logic simulation,” in IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2007), pp. 149-154, 2007. [15] A. Mishchenko, S. Chatterjee, and R. Brayton, “DAG-aware AIG rewriting: a fresh look at combinational logic synthesis,” in 43rd ACM/IEEE Design Automation Conference, pp. 532-535, 2006. [16] R. R. Rao, V. Joshi, D. Blaauw, and D. Sylvester, “Circuit optimization techniques to mitigate the effects of soft errors in combinational logic,” ACM Transactions on Design Automation of Electronic Systems, vol. 15, no. 1, pp. 1-27, 2009. [17] K. P. Parker and E. J. McCluskey, “Probabilistic Treatment of General Combinational Networks,” IEEE Transactions on Computers, vol. 24, no. 6, pp. 668-670, 1975. [18] ISCAS85 High Level Models, http://www.eecs.umich.edu/ jhayes/iscas/
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[19] J. E. Stine, I. Castellanos, M. Wood, J. Henson, F. Love, W. R. Davis, P. D. Franzon, M. Bucher, S. Basavarajaiah, J. Oh, R. Jenkal, “FreePDK: An open-source variation-aware design kit,” IEEE International Conference on Microelectronic Systems Education, pp.173-174, 3-4 June 2007. [20] Q. Zhou and K. Mohanram, “Cost-effective radiation hardening technique for combinational logic,” IEEE/ACM International Conference on Computer Aided Design, 2004, pp. 100-106. [21] B. Naveh. Jgrapht. http://jgrapht.sourceforge.net/.
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