Implementation and test results of a wide-area measurement-based controller for damping interarea oscillations considering signal-transmission delay R. Majumder, B. Chaudhuri and B.C. Pal Abstract: The paper describes the implementation of a centralised control-design scheme in a real-time laboratory-based dynamic simulator. A centralised multivariable-control algorithm is designed employing remote feedback signals considering delay in signal transmission. The transmitted signals can be used for multiple-swing-mode damping using a single controller. Such an algorithm is numerically intensive owing to the high controller size and the predictor that takes care of the delay in signal transmission. The performance of the proposed controller is demonstrated by practical implementation using a rapid-prototyping controller mounted on a PC-ATX. Results of the experimental tests are shown for a detailed model of the power system implemented using Linux PC-based multiprocessor technology.
1
Introduction
Interarea oscillations [1] are inherent in large interconnected power systems. These oscillations often suffer from poor damping. In a practical power system, the number of dominant interarea modes is often larger than the number of controllable devices available to control them. Research attention has therefore been focussed on designing new control structures to improve the damping of multiple swing modes. With rapid advancements in wide-area-measurement systems (WAMS) technology, the transmission of measured signals to a remote control centre has become relatively simpler. Employing phasor-measurement units (PMU), it is possible to deliver the signals at a speed of as high as 30 Hz sampling rate [2, 3]. It is possible to deploy the PMUs at strategic locations of the grid and obtain a coherent picture of the entire network in real time [3]. Notable work from Kamwa [5] suggests that wide-area control can be 10–12 times more effective than local decentralised control of wide-area oscillations. However, the cost and associated complexities restrict the use of such sophisticated signal-transmission hardware on a large commercial scale. As a more viable alternative, the existing communication channels are often used to transmit signals from remote locations. The major problem is the delay involved between the instant of measurement and that of the signal being available to the controller. This delay can typically be in the range of few hundreds of milliseconds r The Institution of Engineering and Technology 2007 doi:10.1049/iet-gtd:20050493 Paper first received 8th November 2005 and in final revised form 15th February 2006 B. Chaudhuri and B.C. Pal are with Department of Electrical and Electronic Engineering, Imperial College London, Exhibition Road, London SW7 2BT, UK R. Majumder is with the School of Information Technology and Electrical Engineering, The University of Queensland, St. Lucia, Qld 4072, Brisbane, Australia E-mail:
[email protected]
depending on the distance, protocol of transmission and several other factors. Therefore, a predictor approach is adopted in this work to formulate the damping-controldesign problem for a power system having a signaltransmission delay of 0.75 s. A H1 controller is designed by solving the problem using linear-matrix inequalities (LMIs) with additional pole-placement constraints [5]. Once the designs and simulations have been performed, the next credible step would be to implement the control scheme and verify the closed-loop behaviour of the entire power system in real time. One concern, however, is the accessibility to the actual system for validating the performance of the controllers in real time. It is extremely difficult to build even a prototype of an actual power system in the laboratory or a manufacturing site. For obvious reasons, it is rarely permissible to perform such validation tests in the field. From technical as well as economic prospective, it is thus desirable to have a dynamic-system emulator which can emulate physically the dynamic behaviour of the power system in real time. Several projects reported in [5–7] described simulation results. A serious bottleneck, which often hampers effective real-time implementation of controllers designed by H1 optimisation techniques is that they tend to have a large size and possibly stiff state equations. This is more so for time-delayed systems as the resulting controller is the feedback combination of the designed controller and the predictor [5]. Therefore before the controllers in actual plants are commissioned, the experimental verification of the designed control algorithm is very important. First implementation and experimental verification of a robust flexible ACtransmission-systems (FACTS) controller is described in this paper. The dynamic behaviour of the power system is emulated in real time in a real-time station (RTS) on which the designed control algorithm is tested using a rapidprototyping controller (RPC). The hardware interface between the two platforms is in the analogue domain through digital-to-analogue and analogue-to-digital converter (DAC/ADC) modules, so that it is virtually
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impossible for the controller to distinguish between the actual plant, and the emulated plant, and same holds for the plant as well. In this way, the costly proposition of building a large prototype power system in the laboratory for testing purpose can be avoided. 2 Predictor-based control design for dead-time system In dead-time systems, measured feedback signals take a certain amount of time to reach the controller. Controlling such time-delayed systems is difficult. Figure 1 shows the generalised control-design setup. The delayed system is modelled as Ph ðsÞ ¼ P ðsÞesh , where e sh is the block to represent the delay in feedback measurement with a dead time h 4 0. The general control setup for a system having an output delay is shown in Fig. 1, where P11 ðsÞ P12 ðsÞ ð1Þ PðsÞ ¼ P21 ðsÞ P22 ðsÞ
z
uncontrollable response that is likely to govern the H1 performance index. One possible way of achieving this is to introduce a uniform delay in both the paths (path 1 and path 2), as shown in Fig. 4. There are two steps in achieving this. First, the delay blocks (e sh) at points 1 and 2 need to be shifted to point 3 by introducing a suitable predictor block in parallel with K. Secondly, a delay block needs to be introduced in path 1. The first step is achieved by introducing a Smith predictor block Z(s) ¼ P22(s) P22(s)e sh, as shown by the dotted box in Fig. 3. The second task of bringing a delay in path 1 is achieved while forming the generalised plant prior to control design. The presence of the predictor block Z and the delay in path 1 ensures that the responses (through path 1 and path 2) governing the performance index is delayed uniformly, as shown in Fig. 4. Path 1
P11
e-sh
Z= P22 -P22 e-sh
d Z
P 1
z
S 3
y
y
P12
K
u P22
K
e Fig. 1
d
Path 2
ym
-sh
P21
e-sh
S
Fig. 3
-sh
e
2
Introduction of Smith predictor and delay block
Control setup for dead-time systems
Path 1
The closed-loop transfer-matrix from d to z is: T zd ðsÞ ¼ P11 þ P12 Kesh ðI P22 Kesh Þ1 P21 . This suggests that there exists an instantaneous response through the path P11 (path 1 in Fig. 2) without any delay. An equivalent structure is shown in Fig. 2.
P11
e-sh
z
S
e-sh
P12
y K
Path 1
3
y
P12
K
S
-sh
Fig. 4
e
P21
Fig. 2
-sh
e
2
Equivalent representation of dead-time systems
It can be seen that, during the period t ¼ 0–h after d is applied, the output z is not controllable, since it is determined only by P11 and d with no response coming through the controlled path (path 2 in Fig. 2). This means that the H1 performance index kTzd k1 is likely to be dominated by a response that cannot be controlled, and this is not desirable. Designing a controller for such systems is rather difficult [8]. Smith predictor is the first effective tool for tackling such control problems [9]. The primary idea is to eliminate any 2
Uniform delay in both paths
d
Path 2
P22
d
P22 1
S
P21 Path 2
P11
z
S
A predictor-based controller for the dead-time plant Ph(s) ¼ P22(s)e sh consists of a predictor Z ¼ P22 P22e sh, and a stabilising compensator K, as shown in Fig. 5. The predictor Z is an exponentially stable system such that Ph+Z is rational, i.e. it does not involve any uncontrollable response governing the H1 performance index. Let us consider a generalised delay-free plant given by 2 3 A B1 B2 ð2Þ PðsÞ ¼ 4 C1 D11 D12 5 C2 D21 D22 ~ can be formulated using the unified The generalised plant P Smith predictor method. The steps for arriving at the final ~ are detailed in [5]. The final form of the expression for P IET Gener. Transm. Distrib., Vol. 1, No. 1, January 2007
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z
revealed that the system had three critical interarea modes i h si ffi and (li ¼ si 7 joi). The damping ratio zi ¼ pffiffiffiffiffiffiffiffiffiffiffi 2 2
d
-sh
e
-sh
ðsi þoi
oi ðHzÞ are shown in Table 1. frequency ½fi ¼ 2p The objective is to damp these modes by designing a supplementary damping controller for the TCSC. Appropriate feedback stabilising signals were chosen for each mode using the modal observability analysis, see [7] for details. The open-loop plant is constructed using the linearised system matrix A, the input matrix B corresponding to the output of the TCSC and the output matrix C corresponding to the measured signals.
P(s)
y
e
ym +
v +
Z(s) P
u
aug
(s)
yp
4
K(s) Fig. 5
Robustness validation by linear analysis
The damping action of the designed controller was examined under different types of disturbances in the system. These include changes in power flow levels over key transmission corridors, change of type of loads etc. The damping ratios of the critical interarea modes under these operating conditions are summarised in Fig. 7. Note that in Fig. 7 CI, CP and CC stand for constant-impedance-, constant-power- and constant-current-type loads. The damping is found to be highly satisfactory in all the cases.
Smith-predictor formulation
generalised plant is as follows: 3 2 B2 Eh1 B1 A 0 7 6 A h 6 0 Anc 0 e nc Inc V 1 B1 0 7 7 6 7 6 ~ ¼6 7 P 7 6 0 7 6 C1 0 D 12 C V 1 7 6 Inc 5 4 D12 0 C 2 Eh 0
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Implementation in real-time platform
The related H1 problem as stated in (3) considering the generalised plant formulated above, was solved in Matlab using the LMI approach with pole placement as additional constraints [5] for ensuring minimum damping. The LMI Control Toolbox available with Matlab has been used to perform the necessary computations. In a large power-system model P22 is of large order, making it difficult to construct Z. It will be easy to carry out design with the reduced plant model and then validate the performance against the full model.
Simulation has long been recognised as an important and necessary step in development, design and testing of FACTS controllers for mitigation of interarea oscillation. Recent advances in both computing hardware and sophisticated power-system-component modelling techniques have significantly increased the application of real-time digital simulation in the power-system industry. Testing controllers with such hardware-in-the-loop (HIL) digital simulators is demonstrated in this paper. Historically the method of performing dynamic studies utilises simulators made up of scaled-down power-system components. Each component is physically connected to
3
Table 1: Interarea modes of the study system
ð3Þ
Study system
The control design and simplification exercise are carried out on a 16-machine, 5-area study system, shown in Fig. 6. A thyristor-controlled series capacitor (TCSC) is installed in the system to strengthen the transmission corridor between New York power systems (NYPS) and area 5. An eigenvalue analysis of the linearised model of the system
Dumping ratio z
Frequency (Hz)
0.0626
0.3913
0.0435
0.5080
0.0554
0.6232
AREA#5
New England Test System
G16
New York power system
G3 G7 G5
62
07 G4
23
02 63
05
G13
19
60
50
56
51
35
34
49
61
37
33
55
32
27
30
38
46
11 G11
09
28 25 08
54
G8
G10
47 48
01
40
41 14
G1
G14
remote signal links
Fig. 6
15
42
10
53 26
G15
31
24
G9
29
45
G12 12 36
17 57 52
21
18
AREA#4
06 68
39
43
66 67
K u TCSC
13
64
G6
y
59
58
20 65
04
22
16 G2
03
AREA#3
16-machine five-area study with TCSC
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3
0.3
0.2
0.25 Open Loop Close Loop
0.15 0.1
Damping ratio
Damping ratio
0.25
0.05 0
0.2
Mode 1
0.15
Mode 2
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CI
CC + CI CP + CI Dynamic
0
Line outage
Real time station Ethernet connection to command station
Network algebraic equation
Shared memory CPU1
of generators, excitation system and TCSC
task#1 Opal FPGA (digital I/O) Opal FPGA (D/A)
bus PCI
RT-LAB real-time station Fig. 8
1
control input
measured signals from system
Signal Conditioning
6 RT-LAB real-time station and rapid-prototyping controller A schematic overview of the RT-LAB real-time station, used for the real-time simulation of the study system, is depicted in Fig. 8. The RTS is a PC running on the realtime operating system RedHawk RT-Linux. It has a dual Xeon processor of 3.2 GHz. Both the processors share a common memory, as shown in Fig. 8. The separation of the tasks involved in simulating the power-system dynamic behaviour is depicted in Fig. 8. The computational tasks are distributed as follows: CPUl of the dual-CPU computer handles the differential equations describing the dynamic behaviour of the generators, associated excitation systems and the FACTS device (TCSC in this case). CPU2 simultaneously solves the network equations to connect the generators with the network. It has been noticed that the most computationally expensive task is to solve the set of network equations to calculate the complex bus voltages from the admittance matrix and the set
task#2
CPU2
3
4
27-53
53-54
60-61
Robustness validation through damping ratio
the next in a manner similar to that in real system. This analogue-simulation technique forms the basis of transientnetwork analysers (TNA) and high-voltage DC (HVDC) simulators. However, owing to the size and the cost constraints, it is difficult to build even a prototype of an interconnected power system in the laboratory. An alternative method, which could be applied to test the designed controller, is based on the mathematical representation of the dynamics of the system rather than a scaled-down version of the physical components. The algorithms necessary for software-based electromagnetic-transient simulation were first described by H. Dommel in 1969 [10] and have been utilised in several well known programs suchas EMTP and EMTDC [11, 12]. One of the most significant disadvantages of software simulations relates to the speed at which they operate. Unlike analogue simulators which operate in real time, most digital-simulation systems operate in nonreal time. Real-time operation implies that an event in the system which lasts for 1 s can be simulated on the simulator in exactly 1 s. Any external hardware could be connected with a system simulated in real time with in-built DAC/ADC modules. Therefore, the controller under test, whether implemented in a low-cost dedicated microcontroller or in analogue circuitry, could be interfaced with the real-time digital simulator.
6.1
900
0.12
Types of load
Fig. 7
100
Power flow from NETS to NYPS (MW)
Damping ratio
Damping ratio
Inter-area modes
0
Mode 3
0.1
Schematic diagram of RTS with system-task separation
of complex bus currents. The inversion of the admittance matrix is avoided by using LU factorisation. The LU factors of the admittance matrix is precomputed and stored. Owing to the change in series compensation of the TCSC, the admittance matrix must be updated dynamically. An optimal ordering of the TCSC bus is done to keep the computational burden or updates of admittance-matrix to a minimum. In the current HIL application, the CPU in charge of solving the differential equations associated with the generators, excitation system and TCSC also controls the FPGA I/O card that sends the measured signals from the plant and reads the control signal generated by the rapid-prototyping controller. The digital signal generation and sampling are both obtained using 10 ns resolution. The FPGA card, built around the Xilinx Virtex-II Pro, also IET Gener. Transm. Distrib., Vol. 1, No. 1, January 2007
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controls fast 16-bit D/A and A/D converters. The sampling time used in the real-time simulation is 1 ms. CPU1 takes around 300–450 ms to solve the differential equations as stated above, and the computational time for CPU2, which solves the algebraic equations simultaneously, is almost 800 ms. Therefore no overruns are detected during the realtime operation. The RTS is a multiapplication real-time platform suitable for hosting a wide variety of dynamic applications and, unlike other realtime environments, is not confined only to power systems. Bearing in mind the cost associated with this state-of-the-art technology, and its ability to support a wide variety of dynamical-systems applications, over a variety of disciplines, it makes the facility a very cost-effective technology.
RT-LAB rapid-prototyping controller
6.3
HIL configuration of RTS and RPC
A Windows host command station is used to set up various test, scenarios or evaluate controller performance for different system disturbances, operating conditions and system/ controller parameters. The host command station and both the real-time digital simulators interact between themselves through a 100 Mbit/s ethernet connection. The schematic diagram of the RTS and the RPC is shown in Fig. 9. If necessary, the computational tasks can be distributed across several PCs to decrease the simulation time step or to simulate more complex systems. Intercomputer communication systems supported by RT-LAB are FireWire 800 Mbits/s as well as SignalWire, which is an FPGA-based fast serial communication link capable of delivering up to 1.25 Gbit/s transfer rates, with a latency of 200 ns. In the RTS platform, the input model is developed in MATLAB Simulink. A graphical user interface, called
ADC
TCSC
Fig. 9
RT-lab main control, is available for managing the communication between the RTS and the command station. Real-time workshop (RTW) of Matlab interfaces Simulink and this hardware platform. The RT-lab main control could be used to build real-time code, and to download and execute this code on a Xeon processor of the RTS through the Ethernet link. Any signal from the model can be bought outside through a built-in DAC and any physical signal can be fed back to the system using a built-in ADC. A robust FACTS controller is a three-input, one-output controller which has been implemented using RPC. The same RT-lab main control is used to generate code for the controller and to download it to RPC, for real-time execution, through the Ethernet link. The inputs to this controller are deviation in the active power flow through the transmission line connecting bus 51–45, 18–16 and 13–17. These signals are generated in the RTS and are interfaced with the controller through on-board DACs of RTS, as shown in Fig. 10. All three measured signals are delayed. These delays are implemented by using transport-delay blocks in the RTS. The control signal is computed by the RPC at every sampling instant and fed back to the simulated power system by a DAC–ADC combination, as shown in Fig. 10.
Power system 16 machine 68 bus inter-connected system
Dual Xeon 3.2 GHz processor real time station (RTS)
Control input
Schematic diagram of RTS and RPC
Transport delay
DAC
Transport delay
DAC
Transport delay
DAC
flows
A rapid-prototyping controller (RPC) is a PC having a Pentium 4 processor running at 3.2 GHz under the RedHawk RT-Linux operating system with the capability of handling I/O interactions in real time. Once the controller is designed and realised in its state–space form, it can be implemented in the RPC. The computational time for the RPC to calculate the control signal is about 60 ms, which is well within the sampling period. In practical situations, the controller could also be implemented in any dedicated lowcost microcontroller. The internal architecture and the I/O interfacing of the RPC and the RTS are almost identical. The efficacy of the designed robust controller is proved in real time by implementing it on RPC.
Measured signals
6.2
Hardware coupling between two platforms
ADC DAC
Robust FACTS controller
ADC ADC
Pentium 4 3.2GHz Processor rapid prototyping controller (RPC)
Fig. 10
Closed-loop configuration of RTS and RPC
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Experimental results
The performance of the designed controller implemented on RPC has been evaluated under various operating conditions, using the emulated power systems on RTS. The
deviations in active power flow through the transmission line from RTS were sampled and fed to the controller. The cotrol signal is fed back to the TCSC control input.
7.1 1.5
1
0.5
0
0
5
10
15
20
25
time, s
Fig. 11 Dynamic response of the system, Matlab Simulink environment
Fig. 12 Dynamic response of the system, real-time station, dual Xeon Processor in real time
Fig. 13
Validity check
The validity of implementation of the nonlinear-powersystem model on the RTS is first established by a number of identical tests performed on the RTS-implemented power system and the same system modelled using MATLABSimulik on a PC. A representative set of results is shown in Fig. 11 and Fig. 12. A three-phase to-earth fault is created at 1 s at bus 27 and the fault is cleared after 80 ms followed by opening of one of the tieline connecting buses 29 and 53. Figure 11 shows deviation in active power flow in the transmission line connecting bus 51 and 45 in MatlabSimulink and Fig. 12 shows the same parameters with the system implemented in RTS. The dynamic behaviour of the study system in thus emulated in real time with reasonable accuracy using the RTS.
7.2
Case studies
One of the most severe disturbance stimulating poorly damped interarea oscillations is a three-phase fault in one of the key transmission corridors. For temporary faults, the circuit breaker ‘autorecloses’ and normal operation is restored; otherwise, the faulted section would be taken out. There might be other types of disturbance in the system suchas change of load characteristics, sudden change in power flow etc. which are less severe than faults and are not considered here. To evaluate the performance and robustness of the designed controller, simulations were carried out corresponding to some of the probable fault scenarios in the New England Test System (NETS) and New York Power Systems (NYPS) interconnection. There are three transmission corridors between NETS and NYPS connecting buses 60 and 61, 53 and 54 and 27 and 53, respectively. Each of the corridors connecting buses 60 and 61 and 53 and 54 consists of two tielines and the corridor connecting buses 27 and 53 consists of one tieline. The outage of one of these lines considerably weakens the transfer capacity of the
Dynamic response of the system
a G1G15 fault at bus 60 with autoreclosing b G1G15 fault at bus 27 followed by opening of one of the lines connecting buses 27 and 43 c G1G15 fault at bus 63 followed by opening of one of the lines connecting buses 63 and 64 d G1G15 fault at bus 60 followed by opening of one of the lines connecting buses 60 and 61 6
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lies the potentiality of a unified Smith-predictor approach (USP) for power-system-damping control design involving finite delay in signal transmission. 8
Conclusions
This paper has demonstrated the implementation and test results of the unified Smith-predictor technique. Because of structural complexity of such predictor-based control, the validation of the control algorithm in real time is an important issue. A key feature of this paper is the realisation of a multimachine power-system model which is capable of providing results in real time on a commercially available real-time simulator (RTS). The designed control algorithm is implemented in a rapid-prototyping controller and the coupling between RTS and RPC is done through a DAC/ ADC module in the analogue domain. The real-time multimachine model has opened the door to many possible application areas, including the provision of a flexible test bench for the development and testing of physical controllers and network compensators. 9 Fig. 14
Dynamic response of the system without considering delay
a G1G15 fault at bus 60 with autoreclosing, without control b G1G15 fault at bus 60 with autoreclosing, with control
corridor. The following disturbances were considered for simulation. A three-phase solid fault for 80 ms (5 cycles): (i) at bus 60 followed by autoreclosing of the circuit breaker; (ii) at bus 53 followed by outage of one of the tielines connecting buses 53 and 54; (iii) at bus 53 followed by outage of the tieline connecting buses 27 and 53; and (iv) at bus 60 followed by outage of one of the tielines connecting buses 60 and 61. The response of the relative angular separation of G1 with respect to G15 is shown in Fig. 13. To demonstrate the drawback of the conventional H1 design with a delay-free plant, a separate controller was designed for the TCSC without considering delay in the design stage. The design was carried out as described in [7]. The controller was found to be acceptable both in time and frequency domain for a delay of up to 0.1 s. For larger time delays, the performance began to deteriorate. The simulation results following the same disturbance with a delay of 0.75 s was carried out and are shown in Fig. 14. It is clear that the controller performance deteriorates considerably if the delay is more than the time period corresponding to the dominant interarea modes and is not taken into account in the design stage. Therefore, inclusion of the delay in the control synthesis is significant and there
Acknowledgment
The authors thank Corporate Research Center ABB, Switzerland and EPSRC, UK for funding this research. 10
References
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