Implementation of a software defined FM mixed demodulator on FPGA

23rd Telecommunications forum TELFOR 2015

Serbia, Belgrade, November 24-26, 2015. 

Implementation of a Software Defined FM Mixed Demodulator on FPGA A. Oguz Kislal, Arda Demiray, Osman Ceylan, Member, IEEE, and H. Bulent Yagci

Abstract — Software defined radio (SDR) applications are usually preferred in low power flexible communication systems. In this paper, a software defined Frequency Modulation (FM) demodulator is presented. Mixed demodulation technique is used to build a digital FM demodulator which has 16 MHz sampling rate. Proposed system was implemented successfully on a Field Programmable Gate Array (FPGA). The system uses 1247 logic elements. FPGA’s power consumption is 113.56 mW. The system was tested and verified with a test bed including Analog Digital Converter (ADC) and Digital Analog Converter (DAC). Keywords —CORDIC, Digital FM, FPGA, SDR.

I. INTRODUCTION RADIOS are widely used for audio signals such as FM broadcasting. Additionally, they are available for narrow bandwidth digital communication systems which requires lower receiver sensitivity [1]. Instead of traditional analog modems, Software defined modems have been getting popularity because of some important benefits such as re-programmability, flexibility and cost [2]. Implementing FM with analog circuits have some handicaps like non-linearity because of voltage controlled oscillator (VCO) and stability performance [3]. Upon the developments in recent years, the spread of low-cost digital signal processing integrated circuits have gained significant importance for the design of digital FM. Also, they have remarkable noise figure performance and superior voice clarity. Field programmable gate arrays (FPGA) have the capability to realize digital Numerically Controlled Oscillator (NCO) and high order filters for software defined FM modulation and demodulation. There are two popular techniques for digital FM demodulation: Phase locked loop based (PLL) and mixed the type. References [3-6] were prepared with PLL based demodulator technique and a reference [7] was prepared with mixed type demodulator. Even though PLL based architecture requires low area usage, mixed type demodulator may be preferred because it has better harmonic distortion performance at low deviations and message frequency. In this study, the mixed type FM demodulator, which

FM

has 16 MHz sampling rate, is implemented on Altera DE0 Nano Board. For implementation, Quatrus II is used. As Digital Analog Converter (DAC) DAC902E, and for Analog Digital Converter (ADC) ADS830 are employed. The system is tested and verified by FM signals that have 1 MHz carrier with different frequency deviations. The present paper is organized as follows: Section II describes the structure of the system, section III covers implementation of FM demodulator, and finally, section IV draws the conclusion. II. STRUCTURE OF THE DESIGNED SYSTEM A. Frequency Modulation Frequency modulation is basically, the frequency change of the carrier signal which depends on the message signal’s amplitude. If the message signal’s amplitude increases, then the frequency of the carrier signal also increases too. The opposite condition is also true for this modulation. The FM signal with the amplitude A, angular frequency Ȧc and modulation index k FM are given in equation (1). Relation between the message signal and φ FM is given in equation (2). (1) S FM ( t ) = A . cos( ω c . t + φ FM ( t ))

φ FM ( t ) = k FM . ³ S N ( t ). dt

At frequency demodulation, message signal SN is obtained from frequency modulated signal SFM. In the following sections, the theory of mix type digital FM demodulator is given. B. Quadrature Mixer After sampling of baseband analog input signal, to obtain a complex baseband signal, quadrature mixer is used. There are two methods in implementation of quadrature mixer. The first method is multiplying the input signal with e j wT n , and the other one is multiplying the input signal with real sinusoidal signals. Since real signals are easier to synthesis on FPGAs, the second option is preferred. The block diagram of quadrature mixer is shown in Fig. 1. The angular frequency of sinusoidal signal equals to modulation angular frequency. Input and outputs of the mixer is given in the equations (1), (3) and (4) respectively.

Corresponding A. Oguz Kislal, Arda Demiray, Osman Ceylan and H. Bulent Yagci are with the Faculty of Electrics and Electronics, Istanbul Technical University, Istanbul, 34469 (phone: +90-212-2853641; e-mails: kislal, demirayar, ceylanos, [email protected]).

978-1-5090-0055-5/15/$31.00 ©2015 IEEE

(2)

333

S real ( n ) = g r 1 ( n ) * g TP ( n ) =

A cos( φ FM ( n )) 2

(3)

S imag ( n ) = ( − 1). g i1 ( n ) * g TP ( n ) =

A sin( φ FM ( n )) 2 Sreal(n)

A. Quadrature Mixer The block diagram of the quadrature mixer is given in Fig. 1. In order to synthesize sinusoidal function, direct digital synthesis method is preferred and its block diagram is submitted in Fig. 3.

Low Pass Filter

SFM(n)

cos(ʘcn) sin(ʘcn) gi1(n)

Low Pass Filter

Inverter

III. IMPLEMENTATION OF MIXED DEMODULATOR

(4)

Z-1

Simag(n) y(n-1)

y(n)

x(n)

Fig. 1. Quadrature Mixer block diagram. C. Mixed Demodulator Mixed demodulator is a combination of two different FM demodulator algorithms, phase-adapter and baseband delay demodulator. The inputs of the system, Sreal(n) and Simag(n) are given at the (3) and (4). Mathematical equations of this technique are submitted in (5), (6), (7), (8), (9) and its block diagram is given in Fig. 2 [8].

Z-1

After multiplication, the first order loop filter is used as a low pass filter. Its transfer function is given in equation (10) and its block diagram is given in Fig. 4. H (z ) =

Y (z ) 1 = X (z ) z − 0.9375

Register

(10) Output

Ssin(n)

+ Sreal(n-1)

Sinusoidal output

Fig. 3. Direct Digital Synthesizer

input Sreal(n)

LUT

-

g1(n)

Arctan

g2(n)

1/(T.kFM)

SD(n)

(15/16)

Fig. 4. Loop filter structure. Simag(n)

Z-1

Simag(n-1)

+ +

Scos(n)

Fig. 2. Mix demodulator structure ssin ( n) = S imag (n).S real (n − 1) − S real (n).S imag ( n − 1)

(5)

= sin(φFM (n)). cos(φFM (n − 1)) − cos(φ FM ( n)). sin(φFM (n − 1)) = sin(φFM (n) − φ FM ( n − 1))

scos (n) = Sreal (n).Simag (n − 1) + Simag (n).Simag (n − 1) = cos(φFM (n)).cos(φFM (n − 1)) + sin(φFM (n)).sin(φFM (n − 1))

(6)

= cos(φFM (n) − φFM (n − 1)) g1 (n) =

ssin (n) sin(φFM (n) − φFM (n − 1)) = = tan(φFM (n) − φFM (n − 1)) scos (n) cos(φFM (n) − φFM (n − 1))

g 2 ( n ) = arctan( g 1 ( n )) = φ FM ( n ) − φ FM ( n − 1) S D (n) =

g 2 ( n) φFM (n ) − φ FM ( n − 1) φ (n ) = = = S N ( n) T .k FM T .k FM k FM ' FM

(7)

B. Mixed Demodulator In this structure multiplication, addition, division and inverse tangent function are required. To implement inverse tangent function, Coordinate Rotation Digital Computer (CORDIC) algorithm is preferred, hence, division and inverse tangent functions are handled by CORDIC itself. Since multiplication and addition may be implemented easily on an FPGA, only CORDIC architecture is argued. CORDIC is a high level algorithm that aims to implement trigonometric, inverse trigonometric or hyperbolic functions in real time [9]. CORDIC algorithm of inverse tangent function is given in Fig. 5.

(8) Den

(9)

Cordic Inverter

Full adder

Barrel Shifter

Y(11)

Den(11)

While T is the period of the carrier and k FM is the modulation index. Because of the inverse tangent function, g2(n) signal should be limited between –ʌ/2 and ʌ/2. Frequency deviation is only related with sampling frequency. Due to this demodulator having a diversion and inverse tangent operations, there is a special condition that should be considered. Dividing any number by zero results in infinity and arctan(’) is not defined. In equation (7) the denomunator signal is given, which equals to zero only for గ φ FM = ±ଶ Ǥ ݅ when ‘i’ is an integer. To overcome this obstacle, a special condition is defined in the source code.

Num

Cordic Inverter

Cordic Inverter

Full adder

Y

Barrel Shifter

Cordic Inverter Y(11)

Den(11) Counter

ROM

Cordic Inverter

Full adder

Output

Y(11)

Fig. 5. CORDIC inverse tangent algorithm structure (in permission of Daniele Giannotti) Since CORDIC algorithm offers an iterative solution, this structure should be repeated. In this project, iteration number is determined as eight. CORDIC is the last component of the mixed

334

demodulator, however, to acquire better result, a Finite Impulse Response (FIR) filter is utilized. Its block diagram is shown in Fig. 6. x15 FIRinput

x14

Z-1

Z-1

x13

Z-1

x12

....

x1

Z-1

x0

Fig. 12. Demodulated FM signal with 75 KHz deviation. x(1/16)

FIROutput

Fig. 6. FIR filter structure. Simulation of the system is demonstrated in Fig 7. The structure and installed test system is given in Fig, 8, Fig. 9 and Fig. 10 respectively. The system is tested with 10 kHz sinusoidal message signal, with 25, 75 and 175 kHz deviation. All of these results are given in Fig. 11, Fig. 12 and Fig. 13. Modulator

ADC

1 MHz carrier

FPGA 8 Bit

DAC

Oscillator

Message signal

Fig. 8. Measurement system overview

Fig. 9. DE0 Nano board ADC and DAC

Fig. 13. Demodulated FM signal with 175 KHz deviation. As expected, at 175 KHz deviation demodulated signal starts to deteriorate. Therefore, mixed demodulator is suitable for low and middle deviation. Comparison of the results between other FPGA implementations of FM demodulator [3], [4], [7] and the proposed system is given in Table 1. Moreover, implementation of [3], [4] and [7] utilizes Xlinx model FPGA, and its resource usage is stated as slices. However, Altera uses logic elements (LE) instead of slices; therefore, when comparing them, the difference between those two measurements should be considered. Since Xlinx’s slice contains 2 flip flops (FF), 2 look up tables (LUT) and Altera’s LE has 1 FF and 1 LUT, it may be stated that 2 LEs roughly equal to 1 slice. PLL based demodulator has better performance in terms of resource usage. Proposed system has better performance than PLL based demodulator in terms of delay time and its resource usage is less than the reference [7]. IV. CONCLUSION In this paper, a digital FM demodulator has been suggested. The proposed design has 3 main parts: quadrature modulation, mixed demodulator and FIR filter. The demodulator has been successfully implemented for FM signal with 1 MHz carrier. It requires only 113.56 mW power at 16 MHz clock frequency. Modelsim is used for simulation and for implementation, Quatrus II is used. It is resulted that the design may be used areas where, power consumption and delay performance are main concerns. REFERENCES

Fig. 10. Test and measurement.

[1]

[2] [3]

Fig. 11. Demodulated FM signal with 25 KHz deviation. [4] [5]

335

N.H. Sephus, A.D. Lanterman and D.V. Anderson, "Exploring frequency modulation features and resolution in the modulation spectrum," in Digital Signal Processing and Signal Processing Education Meeting (DSP/SPE), 2013 IEEE , vol., no., pp.169-174, 11-14 Aug. 2013 D.V I. Vitas, D. Šimuniü and P. Kneževiü “Evaluation of software defined radio systems for smart home Environments,” in MIPRO, Opatija, Croatia, 2015, p 562. I. Hatai and I. Chakrabarti “A new high performance digital FM modulator and demodulator for software defined radio and its FPGA implementation,” International Journal of Reconfigurable Computing, New York, United States, 2011. I. Hatai and I. Chakrabarti “FPGA Implemantation of a Digital FM Modem,” International Conference on Information and Multimedia Technology, 2009, pp 1-4. M. Rice, M. Padilla, B. Nelson, "On FM demodulators in software defined radios using FPGAs," in Military Communications

[6] [7]

[8] [9]

Conference, 2009. MILCOM 2009. IEEE , vol., no., pp.1-7, 18-21 Oct. 2009 J. P. M. Brito and S. Bampi "Design of a Digital FM Demodulator based on a 2nd Order All-Digital Phase-Locked Loop," in SBCCI’07, Rio de Janeiro, Brazil. 2007. Fubing Yu, "FPGA implementation of a fully digital FM demodulator," in Communications Systems, 2004. ICCS 2004. The Ninth International Conference on , vol., no., pp.446-450, 7-7 Sept. 2004 F. Schnyder and C. Haller. "Implementation of FM Demodulator Algorithms on a High Performance Digital Signal Processor," in Diploma Thesis, Nanyang Technological University. R. Andraka. "A survey of CORDIC Algorithms for FPGA Based Computers," 1998.

TABLE 1: FPGA RESOURCE AND TIMING COMPARISON RESULT.

PLL based demodulator [3] PLL based demodulator [4] Mixed demodulator [7] This study (Mixed demodulator)

Resource usage 234 slices 349 slices 2427 slices 1247 Logic elements

Fig. 7. System simulation

336

Power dissipation 108.67 mW 129.27 mW NA 113.56 mW

Delay Time 12.948 ns 12.453 ns NA 9.773 ns