International Journal of Urban Design for Ubiquitous Computing Vol. 2, No.1 (2014), pp.1-6 http://dx.doi.org/10.21742/ijuduc.2014.2.1.01
Implementation of Low Power Digital Clock Design Using Capacitance Scaling On FPGA Shubham Gargrish, Harsimran Kaur and Payal Tanwar Department of Electronics and Communication , Chitkara University, Rajpura, India
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[email protected] Abstract In this paper, we are designing digital clock using Xilinx ISE 14.2 and implementing it on high performance virtex-6 FPGA; Verilog HDL is used to synthesize the clock on FPGA; FPGA is taken as target device. The power consumption of FPGA based digital clock has been verified using Xilinx 12.1 tool. A 7-Segment LCD display has been used for displaying the output. Further power consumption has been reduced by efficiently scaling the capacitance value. When device is in use on 50MHz, 100MHz and 300MHz frequency the diminution is achieved by mapping the value of capacitance. Keywords: Xilinx; Power Consumption; Energy Efficiency; Efficient Capacitance Scaling; Mapping
1. Introduction Time is such a concept which is very difficult to define manually. The earlier way for the measurement of time was by the help of movement of moon and sun. But now we are to use something which can repeat itself after regular interval of time. Digital clock is used to represent the time digitally. There are two kinds clocks analog and digital clock. But now-a-days digital clocks are more widely used which has predominately replaced mechanical working in the clock. Digital clocks typically use the 50 or 60 Hz oscillation of AC Power. A Field Programmable Gate Array is an incorporated circuit that can be involuntary in the field after fabricate. FPGAs are similar in principle to, but have vastly wider potential application than, programmable read-only memory chips. FPGAs are used by Engineers for propose of dedicated Integrated Circuits (ICs) that can be created hardwired in hefty quantities for provision to computer manufacturers as well as end users. We have made a digital clock design which is capable of working on the lowest frequency and is consuming a very low power [1-4].By changing the value of capacitance we are having with different power outputs because of the relation. Power consumption and Capacitance relationshipP = C * V ^ 2 * F. P = Power Consumed, C = switched capacitance (S.C), V = Provided Voltage, and F = Clock Frequency.
ISSN: 2205-8605 IJUDUC Copyright ⓒ 2014 GV School Publication
International Journal of Urban Design for Ubiquitous Computing Vol. 2, No. 1 (2014)
Figure 1. Comparison between the Different Frequencies
In Figure-1. we can easily understand the Power Consumption by different capacitance. By changing the value of capacitance used in designing of digital clock we have successfully achieved our target of low power consumption.
2. Related Work Capacitance scaling is an energy efficient design techniques. Earlier, it was used in design of low power ROM [1], and low power FIR Filter [2] design on 28nm Kintex-7 FPGA. With capacitance scaling, there is no change in clock power (C.P), logic power, signal power and Digital Signal Processing (DSP) power [2] but, there is significant reduction in IOs power, leakage power (L.P) and total power of FIR filter on 28nm Kintex-7 FPGA [2]. There is approx 44.74% reduction in IOs power when FIR filter operating frequency is 5GHz, 50GHz, 500GHz and 1THz and capacitance is scaled down from 25pF to 5pF [2]. Propagation delays are presented in a non-linear format and are calculated. With a cell's output load (wire and fan-out loads) and slew rate [3]. We propose a technique to reduce the effective parasitic capacitance of interconnect routing conductors in a bid to simultaneously reduce power consumption and improve delay [4]. We have selected Xilinx platform as implementation of digital clock goes through HDL, is quite simpler and takes less time. Moreover unlike other methods there is no need to make a unique program set for FPGA. Statement can directly be implemented on FPGA. Whereas others tools like matlab can only be used for simulation and modeling, schematics is not practical in the situation where the circuit becomes complex because of the reason that it needs long timeframe.
3. Methodology While designing the clock we are using a count phenomenon which is playing a very important role in this code implementation. Count is used to increment till set maximum limit before the next stage. As shown in Table 1. In the digital clock coding we used count statement. Table 1. Coding Used in Count Statement Hours count If (outh!= 6’d23) Begin Outh
