Implementation of Mandelbrot Set and Julia Set On SOPC Platform Xin Zhang
Zhiqiang Xu
School of Information Engineering Wuhan University of Technology Wuhan, China
[email protected]
School of Information Engineering Wuhan University of Technology Wuhan, China
[email protected]
Abstract—The method of fractal-geometry is widely applied in researches of computer graphics and simulation. Presented here is a study of the Escape-time fractals that generate Mandelbrot (M) Set and Julia (J) Set in hardware platform. The paper simulates M Set and J Set via MATLAB and implements complex calculations, large amounts of data storage and output based on System-on-a-ProgrammableChip (SOPC) embedded in Altera FPGA device. It is revealed that the fractal graphics appear differently at different iterations and complex parameters but identical at different scales. The results indicated that fractal algorithms and computer graphics can be implemented based on a smaller hardware platform. Keywords-component; Fractals; Mandelbrot Set; Julia Set; MATLAB; FPGA; SOPC;
I.
Figure 1. Koch snowflake
INTRODUCTION
The term fractal was coined by Benoît Mandelbrot in 1975 and was derived from the Latin fractus meaning “broken” or “fractured”. It describes a rough or fragmented geometric shape that can be split into parts, each of which is a reduced-size copy of the whole, a property called self-similarity [1]. Look from whole, fractal graphics are irregular shapes everywhere, such as coastline, mountains. They do not adhere to the typical mathematical dimensions commonly used, such as 1-D, 2-D, 3-D [2]. It can be characterized as having a non-integer dimension. They consist of repetitive patterns of self-similar shapes and can be quite beautiful. A mathematical fractal is based on an equation that undergoes recursion and iteration. While fractals are a mathematical construct, they truly exist in our life. There are much natural sceneries like fractal graphics. The Koch snowflake [3] best exemplifies the iteration process as Figure 1 shows. Although the fractal has just been proposed for 30 years, it has been widely used in many fields as a new branch of science especially in medicine [4], signal and image compression [5] and technical analysis [6]. Unlike the implementation of fractals on PC platform previously, this paper introduced a new approach to the verification of fractals using NIOS II processor system implements data input, data processing, data storage and data output based on System-on-a-Programmable-Chip (SOPC).
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II.
MANDELBROT AND JULIA SETS
A fractal study is not complete without discussing one of the most important and powerful applications of fractal geometry developed – Mandelbrot and Julia Sets [2]. These sets were generated from the escape-time fractals. Considering the nonlinear function on complex field F( z ) = z + c (z and c all belong to a complex field) constitute an iterative sequence: [7] 2
2
z n +1 = z n + c
(1)
The original starting point is added to the square of the previous point at each iteration. If this new point has a magnitude greater than a real number, it must eventually 'escape' to infinity and is thus not part of the set. So the point was given a color and mapped onto the complex plane; otherwise the iteration process continued. Definition 1: The Mandelbrot Set is the collection of point z in the complex plane for which the sequence as follows fails to diverge in absolute value of z.
z0 = z
(2) 2
z n +1 = z n + z
(3)
Definition 2: The Julia Set is a fractal closely related to the Mandelbrot Set. Rather than adding the point z under consideration when checking for set membership, a fixed complex constant c is added. The series used to define the Julia set is based on the sequence: [7]
z0 = z
(4)
2
z n +1 = z n + c
(5)
The paper has accomplished simulation parts of fractals generating by MATLAB on PC platform. The simulation obtains two kinds of fractal graphics as follows:
Figure 5. Julia Set, c=-0.7017+0.3842i
Figure 6. Julia Set, c=0.2850+0.0100i Figure 2.
Mandelbrot Set
Figure 7. Julia Set, c=-0.7322-0.2628i Figure 3. Julia Set, c=-0.81000-0.17950i
III.
SYSTEM OVERVIEW
The whole system consist of three parts: Nios II processor system based on SOPC, customized logic modules, VGA monitor. The block diagram of system is presented in Figure 8. The main control cell adopts NIOS II processor, which completes many times iterative computations and offers the control signals. The design of peripheral modules and synthesis based on FPGA by using Verilog can be realized on sram controller and VGA controller, which can store data and display the graphics.
Figure 4. Julia Set,c=-0.4000+0.6000i
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System Reset Module
SDRAM_CLK
VGA_CLK
JTAG Debug Module
Nios II Processor Core SDRAM Memory
EPCS Serial Configuration Device
At 640x400 resolution and 60 frames per second, we need to output fully-computed pixels at 25MHz. The software arithmetic flow diagram is shown in Figure 9.
PLL
Nios II Processor System System ID Core
VGA Controller
Monitor 640*400
SDRAM Controller
EPCS Controller Core
PIO Core (Output)
Sram Controller IS61LV25616AL
Figure 8. System Block Diagram
IV.
HARDWARE DESCRIPTION
A Nios II processor system is equivalent to a microcontroller or “computer on a chip” that includes a Nios II processor core, a combination of peripherals, onchip memory, and interfaces to off-chip memory, all implemented on a single Altera device. The Nios II architecture is a 32-bit RISC softcore architecture which is implemented entirely in the programmable logic and memory blocks of Altera FPGAs. The soft-core nature of the Nios II processor lets the system designer specify and generate a custom Nios II core, tailored for his or her specific application requirements. System designers can extend the NiosII's basic functionality by adding a predefined memory management unit, or defining custom instructions and custom peripherals. Nios II uses the Avalon switch fabric as the interface to its embedded peripherals. Compared to a traditional bus in a processor-based system, which lets only one bus master access the bus at a time, the Avalon switch fabric, using a slave-side arbitration scheme, lets multiple masters operate simultaneously. The IS61LV25616AL is a high-speed, 4,194,304-bit static RAM organized as 262,144 words by 16 bits. It is fabricated using high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. VGA (video graphics array) is a video display standard introduced in the late 1980s in IBM PCs. We discuss the design of a basic 4096-color 640-by-400 resolution interface for LCD monitor in this paper. V.
Figure 9. Software Arithmetic Flow Diagram
VI.
RESULTS AND DISCUSSION
In order to verify and observe Mandelbrot Set better, we choose different iterations such as 30, 60, 100 and different amplification factor such as 5, 10, 20 in this experiment. There are some figures as follows.
SOFTWARE DESCRIPTION
Take the Mandelbrot Set as an example. Its real part values from -2 to 1 and its imaginary part values from -1 to 1. Choose the point (-2, 1) as the vertex in the upper left corner and the point (1, -1) as the vertex lower right corner of a rectangle. So this is a relatively rectangle including the whole Mandelbrot Set. It is of length 3 coordinate units and width 2 coordinate units. Then map this rectangle to LCD monitor. According to the resolution of LCD monitor is 640-by-400, the original scaling factor is about 200. Because then we can color the pixel based on fractal algorithms.
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Figure 10. Mandelbrot Set without any amplification
As is illustrated in Figure 10, for the specified real number R and iterations N beforehand, if the distance between Zn+1 and Z n is not more than R after repeated iterative operation, the point set belongs to Mandelbrot Set, we put a certain color on these pixels. If not, it is not belongs to Mandelbrot Set, we put different colors on these pixels according to the iterations. After computed and graphed on the complex plane, the Mandelbrot Set is seen to have a white connected area which is surround by a complex and elaborate boundary. This qualifies the boundary as a fractal.
Examining Figures 11-13, if we choose a local to zoom in, it is clear that the graphic is very rich in detail as the increase of iteration times. We can find some edge parts are similar to the whole set. It is an example of a selfsimilarity set from the whole to part. Like Mandelbrot Set, we choose different parameters especially c value to study Julia Set. There are some figures as follows.
Figure 14. Julia Set, c=-0.745429
Figure 11. Mandelbrot Set after different iterations, amplification factor=5
(a)
(b)
Figure 15. Julia Set, c=0.27334-0.00742i (a) Iterations=30 (b) Iterations=100
(a)
Figure 12. Mandelbrot Set after different iterations, amplification factor=10
(b)
Figure 16. Julia Set, c=0.285+0.01i (a) Iterations=30 (b) Iterations=100
(a)
(b)
Figure 17. Julia Set, c=-0.8+0.156i (a) Iterations=30 (b) Iterations=100
Figure 13. Mandelbrot Set after different iterations, amplification factor=20
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[3]
[4]
[5]
(a)
(b)
Figure 18. Julia Set, c=-0.488679-0.56790i (a) Iterations=30 (b) Iterations=100
[6]
Looking at Figures 14-18, it is obviously that Julia Set graphics are much different with different c value. Also, they are different with different iterations. Both Mandelbrot Set and Julia Set have become popular outside mathematics both for their aesthetic appeal and for being a complicated structure arising from the application of simple rules. It is a good illustration of complexity in simplicity. VII. CONCLUSION This paper has successfully studied Mandelbrot Set and Julia Set. The fractal algorithm was introduced and simulated in MATLAB. Furthermore, the generation of beautiful fractal graphics based on this algorithm is implemented with Altera FPGA device. Implementation results also suggest that complex algorithms can be achieved based on a smaller hardware platform. VIII. NEXT STEPS In order to make full use of Nios II embedded development platform, we can improve processing speed and system performance from following several aspects: 1) Custom instructions With the Altera Nios II embedded processor, we can accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. Using custom instructions, we can reduce a complex sequence of standard instructions to a single instruction implemented in hardware. 2) Using the C2H Compiler The Nios II C-to-Hardware Acceleration (C2H) Compiler is a tool that allows designers to create custom hardware accelerators directly from ANSI C source code. Using the C2H Compiler, we can develop and debug an algorithm in C targeting an Altera Nios II processor, and then quickly convert the C code to a hardware accelerator implemented in a field programmable gate array (FPGA). 3) Creating Multi-core Designs Multi-core designs combine multiple processor cores in a single FPGA to create a higher performance computing system. ACKNOWLEDGMENTS The authors would like to thank the associate professor Jun Ruan for his support of this research. REFERENCE [1] [2]
Benoît B. Mandelbrot, “The Fractal Geometry of Nature,” W.H.Freeman, New York, 1983. L. Lazareck, G. Verch, and J. F. Peters, “Fractals In Circuits,” Canadian Conference on Electrical and Computer Engineering, v1, p589-594, 2001.
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[7]
M. L. Lapidus and M. M. H. Pang, “Eigenfunctions on the Koch Snowflake domain,” Commun. Math. Phys. 172 (1995) (2), pp. 359–376. P. Paramanathan, R. Uthayakumar, “Application of fractal theory in analysis of human electroencephalographic signals,” Computers in Biology and Medicine, v 38, n 3, p 372-378, March 2008. A. Selim, M. M. Hadhoud, M. I. Dessouky, and F. E. Abd ElSamie, “A simplified fractal image compression algorithm,” 2008 International Conference on Computer Engineering and Systems, ICCES 2008, p 53-58, 2008. P. Bakucz, R. Krüger-Sehm, “A new wavelet filtering for analysis of fractal engineering surfaces,” Wear, v 266, n 5-6, p 539-542, February 15, 2009. Daniel Ashlock, “Evolutionary Exploration of the Mandelbrot Set,” 2006 IEEE Congress on Evolutionary Computation, CEC 2006, p 2079-2086, 2006.
