Implementation of Programmable Logic Devices in Fuzzy Controlled Electrical Drive C. Pavlitov, Y. Gorbounov, L. Spirov, N. Stefanov The article is provoked by the development of a speed controlled electrical drive for a two-chain mobile robot. Special attention is paid to the dynamics of the movement processes. For this purpose a speed fuzzy controller has been built, implemented on the basis of CPLD (Complex Programmable Logic Device – Xilinx CoolRunner-II XC2C256). The usage of CPLD is determined by the necessity of parallel running algorithms, such as speed measurement, speed error calculation, fuzzy controller output computation, regulator output integration, generation of PWM (Pulse Width Modulation). Besides, in this circuit parallel running algorithms for processing of incremental detector pulses and motor reverse error correction is considered [5]. Two driving circuits can be implemented in a single CPLD device. That makes the controller flexible, compact and cheap. The algorithms used in control circuits are implemented by the aid of a hardware description language – Verilog HDL in the environment of Xilinx ISE. Приложение на програмируемите логически устройства в системите за електрозадвижване с размито управление (К. Павлитов, Я. Горбунов, Л. Спиров, Н. Стефанов). Работата е провокирана от разработката на управляемо по скорост електрозадвижване за двуверижен мобилен робот. Специално внимание е отделено на динамиката на процеса на движение. За тази цел е построен размит контролер на скорост, реализиран на базата на CPLD (Complex Programmable Logic Device – Xilinx CoolRunner-II XC2C256). Използването на CPLD е продиктувано от необходимостта от паралелно изпълняващи се алгоритми, такива като измерването на скорост, изчисляването на грешката на скоростта, изхода на размития регулатор, интегриране на изхода на регулатора, генериране на ШИМ (Широчинно Импулсна Модулация). Освен това, в тази схема са предвидени паралелно работещи алгоритми за обработване на импулсите от инкрементален детектор и коригиране на грешката от реверсиране на мотора [5]. В едно CPLD устройство могат да бъдат вградени две управляващи схеми. Това прави контролера гъвкав, компактен и евтин. Алгоритмите, използвани в управляващите схеми са реализирани с помощта на език за хардуерно описание – Verilog HDL в средата на Xilinx ISE.
Introduction The programmable logic devices (CPLD – Complex Programmable Logic Devices and FPGA – Field Programmable Gate Arrays) become very popular nowadays due to the opportunity of parallel algorithms implementation. In a lot of cases, comparing them to the ordinary processors, they appear to be much more productive in speed and sometimes in simplicity of the algorithms realization. The following statement is valid for their practical application: Resources have been adapted to the algorithm instead algorithm to be adapted to the resources. The article for parallel processing in electrical drives has been provoked by a scientific project
realization sponsored by Technical University of Sofia which main task has been to create a two chains robot. The two drives of each chain have to be driven by speed controlled direct current electrical drive. The main requirements have been the following: • The device should be reliable and compact. • The speed range should be wide enough (from 0.01 to 0.5 m/s) and speed should be kept on a constant level no matter the torque of the load is changed. • The motors speed transitional processes should be near to critical aperiodic behavior. The above mentioned requirements prompted out, that there is need of speed regulator, the regulator should be reliable - that means digital for sure. The regulator should be simple, compact and behavior
adjustable. Fuzzy regulator would fit best for the case, since it doesn’t require high computational power and it is easy for practical realization. The regulator or so called control device unit is implemented on the basis of CPLD (Xilinx Cool Runner - II XC2C256). The application of CPLD circuit is determined by the necessity of parallel running algorithms, such as speed measurement, speed error calculation, fuzzy controller output computation, regulator output integration, generation of PWM (Pulse Width Modulation) pulses. Besides, in this circuit parallel running algorithms for processing of incremental detector pulses and motor reverse error correction are considered [5]. Plant-Controller System Mathematical Model The two chains of the robot are controlled by two RE 36-MAXON direct current motors. Every one of them is supplied with encoder which generates 400 pulses per a rotation. The data sheet for the motors is given below in Table 1. Table 1
The general DC motor structure schema is given in fig.1(a), where UA is the anchor voltage. In fig.1(b) the virtual plant (motor) Simulink model is shown. It has been derived after substitution of the Table 1 values. The electromagnetic time constant TE has been calculated by the equation (1): L (1) TE R The regulation of the speed in general, supposes two feedback loops: current internal loop and speed external loop. The strategy of the suggested device will be a little bit different than the classical ones. The current loop which main purpose is to limit the anchor current is changed to current limited power supply. That is why only the speed feedback will be implemented. This speed control device will be developed on a fuzzy logic principle [1]. The angular speed error membership functions are pointed out in fig.2.
DC motors parameters name
parameter
value
dimension
Power Nominal Anchor Voltage Nominal Current Nominal Angular Speed Nominal Torque Efficiency Coefficient Electromagnetic TimeConstant Motor Constant Anchor Inductance Active Anchor Resistance Unloaded Motor Inertial Moment
P
70
W
UN
18
V
IN
3.18
A
ωN
6610
rot/min
MN
0.081
N.m
Η
84
%
TE
6
mS
C
25.10-3
N.m/A
L
0.1
mH
R
0.628
Ω
J
0.6.104
N.m2
Figure 2. Angular Speed Error Membership Functions
As it is seen from it, membership functions are classified in five groups which are as follows: Positive Big Angular Error (WPosBig), Positive Middle Angular Error (WPosMid), Zero Angular Error (WZero), Negative Big Angular Error (WNegBig), Negative Middle Angular Error (WNegMid). These membership functions are chosen on an expert level by the simulation designer. The classification which has been made above is called fuzzification. It concerns the input signal of the regulator. The control algorithm is embedded in fuzzy control rules. Their if- then structure is shown below: • If (DeltaSpeed is WPosBig) then (U.DCM is UPosBig) • If (DeltaSpeed is WNegBig) then (U.DCM is
Figure 1. Model of MAXON RE36 DC motor with permanent magnets: transfer function(a) and virtual plant(b)
UNegBig) • If (DeltaSpeed is WZero) then (U.DCM is UZero) • If (DeltaSpeed is WPosMid) then (U.DCM is UPosMid) • If (DeltaSpeed is WNegMid) then (U.DCM is UNegMid) What one can see from these rules is that at first glance they look like a proportional regulator. But it is not the truth. As it will be seen further the regulator is strongly non-linear and as the majority of the fuzzy regulators are, it has integral component inside. The output signals of the regulator are obtained by fuzzy control rules. In fact these outputs are linguistic and they do not have fixed values. In order to be fixed, a defuzzification has been made by Sugeno defuzzification style [6]. The value of defuzzification singletons are given below: UPosBig=0.8V, UNegBig=-0.8V, UPosMid=0.2V, UNegMid=-0.2V, UZero=0V. After all has been done successfully the Control Transfer Function has been generated by the MATLAB Control Fuzzy Toolbox [1]. It is pictured in fig.3.
The fuzzy control transfer function is embedded in the MATLAB Simulink Model which is given in fig.4. The corresponding block inside is named Fuzzy Comparator. As it is seen from the Simulink model, the next block that follows the Fuzzy Comparator is the Discrete Time Integrator. The purpose of this block is to accumulate the output control signal from the fuzzy comparator and at the same time to determine the step of discretisation of the whole simulated module. The mathematical model of the motor shown in fig.1(b) is substituted with the block Maxon 18/3. The limitation opportunities of the power supply block are demonstrated with the block called Power Supply Current Limiter. This block is intended to limit the maximal motor current that is realized by
Figure 5. Graphical representation of the speed [rad/s]
Figure 3. Fuzzy Control Transfer Function
limiting the output current of the power supply source. Because the current decrease in current limiting mode is relatively fast, a block named SpeedCurrentLimiter is used. This block actually acts as a low-pass filter for the current fluctuations that emerge when exceeding the current maximum value. The goal is to obtain lower frequency fluctuations that create stability in control in general. The Taho Filter Block reflects the encoder transfer function.
Figure 4. MATLAB Simulink Model of the plant - fuzzy controller system
The load assignment is implemented by the block dI, shown in fig.4. It changes the static current Ic from 0 to 1,2A. By the block W_Assignment in the same figure, the speed is given values of +350 rad/sec for the first 10 sec, 0 rad/sec for the next 10 sec and -350 rad/sec for the last 10 sec. Having supplied a threelevel speed assignment on the input of the model, the following graphical output: speed and current functions are generated (fig.5, fig.6). The two graphics must be treated as results of one and the same experiment where fig.6 depicts the current variation when changing the speed assignment (fig.5) in positive, zero and negative direction.
obtained from it are the levels of comparison and the step of the discretisation. These parameters are taken in one condition – the system should have the desired behavior visualized in fig.5 and fig.6. Device Basic Block Diagram The main block diagram of the speed controller device is depicted in fig.7. The motor is driven by full bridge power module L6203 using the so called soft chopping pulse width modulation, which means while left channel is grounded the right channel is modulated and vice versa. The accumulator is very important part of the device. As it determines the step of regulator discretisation it is convenient to be clocked with its own clock, equal to discretisation a0
start
yes
cnt_load = 1 cnt_in = POS
mono_start = 1
cnt_enable = 1
Figure 6. Graphical representation of the anchor current [A] mono_not_ready ?= 1
As it is seen from the pictures above, the first one (in fig.5) shows small oscillations in the speed dynamic behavior, but it can be said that the transitional process is critical aperiodic near to aperiodical and the supply current, on the second, doesn’t exceed 5A which limitation comes from the hardware. This mathematical model will serve as a fundamental base for the further development of the fuzzy control system. The main parameter values
strob
assignement
clock 1,8432MHz
R E G I S T E R
S U B T R A C T O R
fuzzy controller
speed measurement clock 1,8432MHz
DirA DirB direction
no
direction ?= 1
a1
a4
a2
a5
a3
a6
no
no
yes
yes
cnt_load = 1 cnt_in = NEG
mono_start = 1
cnt_enable = 1
mono_not_ready ?= 1
yes
no
ovfPOS ?= 1 (cnt_out ?= h7F)
load_speed = 1
ovfNEG ?= 1 (cnt_out ?= h80)
no
a7
Figure 8. Speed Measurement Algorithm
time. The feedback signals are coming from the incremental detector. Their two phases pass through optical block (OPT), and then they are supplied to clock 20Hz
clock 1,8432MHz
A C C U M U L A T O R integrator
encoder logic
PWM M O D U L A T O R
A B
+18V
chA
chB
M chB
chA
GND
OPT
clock 1,8432MHz
Figure 7. Basic Block Diagram of the Speed Controller Device
incremental detector
Encoder Logic, which multiplies their frequencies by factor of four and makes corrections of the errors emerging during the reverse cycles (if any) [5]. The separated phases of the encoder named DirA and DirB are supplied to the speed measuring device. The number generated by speed measurement device is proportional to the angular speed of the motor. This number is subtracted from the assignment which comes from outside and the result of subtraction is the error of the speed that is entered into the fuzzy control block. All of the calculations are made in fixed point eight bit arithmetic, which means 256 levels of speed discretisation. That is quite enough for the two chains robot requirements. The numbers are signed and they are transferred into negate code. The most important issue here is that all these blocks are running simultaneously, every one with its own specific clock frequency. The modules (programs) are written on the Verilog hardware description language [2], [3], [8]. The state machines are developed on a data flow way of programming, the rest of the programs are written in a behavior programming style. Speed Measurement Algorithm The block diagram of the speed measurement algorithm is given in the fig.8. The main operating part in this algorithm is an updown counter. If the motor is rotating in positive direction (direction=1) then the counter is loaded by POS=00 but if it is rotating in negative direction it is loaded by NEG=FF. In the first case the counter counts incrementing its content and on the second start
no
enable yes x1 cnt_load = 1 load_sign = 1
pulse _out ?= 0
y1 y2 yes x2
no pulse_enable = 1
pause_out ?= 0
y3
yes
no pause_enable = 1
y4
Figure 9. Main algorithm for PWM
occasion it decrements its content. The counting happens when enable occurs (a3, a6) but beforehand monovibrator start is provided (a2, a5). When the time of the monovibrator has expired the content of the counter is transferred to the output register (a7). This transfer can be executed earlier if event of overflow has been found. The left part of the algorithm is for positive rotating speeds and the right is for negative. Pulse Width Modulation Algorithm As it was mentioned before the Pulse Width Modulation is implemented in a Soft Chopping algorithm which main idea is revealed in the following: when motor rotates in positive direction then side A of the full bridge is active (modulated) and side B is passive (grounded) and on the contrary, when motor rotates in negative direction then side B of the full bridge is active (modulated) and side A is passive (grounded). This soft chopping regime has been chosen due to the motor temperature relive conditions. sign y3
chA
chA y 3 sign sign chB y 3 sign sign
chB
Figure 10. Determination of the motor direction rotation
The actual work of the module is performed by two parallel running algorithms. The first one implements the pulse and pause time duration of the soft chopping regime and the second one determines which phase is active and which is passive. These two simultaneously working algorithms are depicted in fig.9 and fig.10 correspondingly. The main algorithm operating parts are two countdown counters; the first is for the pulse duration and second is for the pause duration. The counters are loaded (y1) by different numbers. The first counter is loaded by the 7 bit unsigned number coming from the accumulator. This number corresponds to the control voltage generated by the integrator unit. The second counter is loaded by a number which is equal to the complement code of the first one. So the sum of the contents of the two counters should be equal to hex80. During that time (the time of loading) of the state machine condition, a (y2) signal which remembers the most significant sign bit of the control voltage has been issued. The question (x2) waits for pulse counter expiration. During this time signal (y3) for active pulse on a phase is generated. Finishing with (y3) the
start
out = h00
yes
reset no enable = 0
no
in > WPosBig
yes
in > h7F
out = UPosBig enable = 1
yes out = UnegBig enable = 1
yes
no
in < WNegBig no
in > WPosMid
yes
out = UPosMid enable = 1
out = UnegMid enable = 1
no
yes
in < WNegMid no
out = UZero enable = 1
out = UZero enable = 1
Figure 11. Fuzzy Speed Control Algorithm
next pause phase is started, it is declared by (y4) output signal. The second simultaneously running algorithm determines which phase to be passive and which active. The left input channel of the power module is marked as phA and right as phB. The equations and corresponding logical circuit are given in the fig.10. Fuzzy Speed Control Algorithm The Fuzzy Speed Control Algorithm is shown in fig.11. In fact, this algorithm is nothing else but one dimensional look up table which in this case is easier to be treated as a multilevel comparator unit. The names in this algorithm are thoroughly explained in the beginning and the exact values of comparison and the output signals are given below. WPosBig = h10 WPosMid = h01 WNegMid = hFF WNegBig = hF0
UPosBig = h04 UPosMid = h01 UNegMid = hFF UNegBig = hFC UZero = h00
The levels of comparison WPosBig, WPosMid, WNegMid, WNegBig divide the input space in five zones of sensitivity and the output signals UPosBig, UPosMid, UNegMid, UNegBig, UZero ensure five corresponding reactions. Conclusions CPLD and FPGA circuits are highly effective for parallel algorithms implementation. The adaptive architecture of them strongly increases the effectiveness of their resources usage. There is a huge reduction of the execution time due to the parallel algorithms performance.
Despite of the difficulties during the process of the first digital design of the circuit, design time is significantly reduced when there are a number of pre designed module libraries. For instance, if the fuzzy speed controller has to be redesign from 8 to 10 or 12 bit controller, the transformation of the Verilog program will be only the matter of array dimension change. The capacity of the Xilinx - XC2C256 CoolRunner-II is 256 macrocells [8]. The Xilinx ISE translator program indicates that only 65% of the chip resources are in use. If proper optimization is going to be made or the next XC2C384 is used, it would be possible the two speed controllers to be allocated into a single chip [8]. The practical implementation of this fuzzy speed controller unit shows that the results obtained from the mathematical model are almost fully overlapped (10% error) by the real ones. The real results are obtained by the aid of a tachogenerator in laboratory environments. Further more, without the model, it is almost impossible to find the proper discretisation time, consequently the work point of stability. It wouldn’t be an exaggeration if we claim that the programmable logic devices (CPLD & FPGA) are a key point to the contemporary digital design. References [1] Jang, R. (1997) MATLAB Fuzzy Logic Toolbox - User’s Guide, MathWorks Inc. [2] Mano, M. M. (2002) Digital Design, Los Angeles, USA, Prentice Hall. [3] Palnitkar, S. (1996) Verilog HDL. USA, SunSoft Press. [4] Pavlitov, C.N. (2003) Fuzzy Position Control of Induction Motor. 5-th International AECV
Conference, organized by the ministry of defense of France, Angers, France. [5] Pavlitov, C.N., Gorbunov, Y.V. (2005) Precise Encoding Method and Device. 13-th International Conference on Electrical Drives and Power Electronics – EDPE 2005, Dubrovnik, Croatia. [6] Pavlitov, C.N., Gorbunov, Y.V. (2005) Nonlinear TanSig Converter Based on Spartan II Xilinx FPGA. (in Bulgarian) Е+Е journal (ISSN 0861-4717) 3-4, 45-48. [7] Pavlitov, C.N., Siderov S., Andasarov S. (2001) Mathematical Model of Neuro-fuzzy Power Factor Control System. IEEE, International Aegean Conference on Electrical Machines and Power Electronics, Kushadasi, Turkey. [8] Xilinx DataSource CD-ROM, Rev.8 Q1-2003. Constantin Pavlitov is an associate professor in the Department of Electrical Drives Automation at Faculty of Automation in the Technical University of Sofia. He delivers lectures in “Logical Control of Electromechanical Systems”, “Computer Monitoring and Control of Electromechanical Systems” and “Microprocessor Control of Electrical Drives”. He gives also lectures in the English language department of Engineering in the area of Computer Architecture included in the subject “Computing II”. His scientific interests are in the field of fuzzy and neuro-fuzzy control of electrical drives and their identification with the aid of artificial neural networks. tel.: +359 2 965 35 18 e-mail:
[email protected]
Yassen Gorbounov has received his M. Sc. degree in Faculty of Automation at Technical University of Sofia in 2004. Currently he is a PhD student in the Department of Electrical Drives Automation in the same university. His research interests include automatic control of electrical drives, application of neural networks and fuzzy logic for their control, parallel processing algorithms with programmable logic devices. tel.: +359 887 93 25 43 e-mail:
[email protected] Lyudmil Spirov is an assistant professor in the Department of Electrical Drives Automation at Faculty of Automation in the Technical University of Sofia. He is a lecturer in “Diagnosis and Reliable Design of Robot Systems” and “Robot System Diagnostics”. tel.: +359 887 22 63 58 e-mail:
[email protected] Nikolay Stefanov has received his M. Sc. degree in Faculty of Automation at Technical University of Sofia in 2006. Currently he works in the field of power electronics development and control of electro machinery in the laboratory of Computer Monitoring and Control of Electromechanical Systems in the same university. He also works for a service company related to medical equipment support. e-mail:
[email protected] 
