Implementing Root Raised Cosine (RRC) Filter for WCDMA using Xilinx

2011

International Conference on Electronic Devices, Systems and Applications (lCEDSA)

Implementing Root Raised Cosine (RRC) Filter for WCDMA using Xilinx *N.Khairudin, M.F.Md Idros, N.A.N Hassan, A.H.A Razak, M.A Haron, S.A.M Al-Junid Faculty of Electrical Engineering Universiti Teknologi MARA 40450 Shah Alam Selangor, Malaysia *[email protected]

Abstract-This paper presents implementation of Root Raised Cosine (RRC) filter at transmitter of 3G-WCOMA wireless communication by using VHOL programming language on Field Programmable Logic Array (FPGA). The main objective of this project is to reduce the inter-symbol interference (lSI) which will affect the bandwidth required for transmission the data. MATLAB 7.0 is used to design RRC filter for generating filter coefficient and checking its functionality in WOCMA transmitter. Then RRC filter coding is generated by VHOL in XILINX application and being verified in Model Sim SE 6.3f before it being synthesized using Xilinx ISE Simulator. All the results produced will be verified for make a comparison. Ktywords-Pulse

Shaping,

Inter-symbol

Interference,

RRC

Filter, Roll off Factor.

1.

INTRODUCTION

HE need to enhance an efficient communication is one of Tthe prime necessities of people today. Third generation

(3G) wireless communications using WCDMA will offer wideband data and voice services that will enable applications such as wireless video conferencing and Internet. The WCDMA standard has two modes for the duplex method Frequency Division Duplex (FDD) and Time Division Duplex (TOO). The frequency bands allocated for WCDMA are shown in Figure 1 [2]. In WCDMA there is one pair frequency band in the range 1920 -1980 MHz and 2110 -2170 MHz to be used for WCDMA FDD. There are two unpaired bands from 1900 -1920 MHz and 2010 - 2025 MHz intended for the operation of WCDMA TOO. 0

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consumption. Root Raised Cosine (RRC) pulse shaping filters are one of the hardware requirements for 3G wireless communication. The implementation of RRC filters using FPGA can yield significant hardware saving and greater clock rate. This paper will examine RRC pulse shaping filter in mobile baseband processing unit of the transmitter for WCDMA. Traditionally, transmitter architectures are almost exclusively analog in all front-end parts. Digital blocks are only found in baseband and digital-to-analog conversion is made with baseband DACs at low sample rates. The term baseband refers to a signal whose spectrum extends from (or near) dc up to some finite value, usually less than a few megahertz [1]. To understand the behavior of RRC filter, let considered first a simple baseband transmitter for digital system as shown in Figure 2 below. The data signal is first modulated and for WCOMA, the modulation scheme used for uplink is binary phase shift keying (BPSK) where the baseband signal (bitstream) is modulated into new binary set of symbols. The modulated signal is then upsampled by factor of 4 that satisfy the Nyquist criteria which required the upsampled factor must greater than 2, intended to reduce inter-symbol interference (lSI). Root-raised cosine (RRC) filtering is used to limit the spectrum of the coded information and to provide a good shaped signal with preservation of its content. Moreover, inter-symbol interference is reduced by a filter such as a Nyquist filter [1].

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Figure 1: The frequency spectrum allocations for WCOMA Table 1: Standardize parameter for WCOMA The major issue for this high-tech application is the rising cost that including the hardware cost, battery life and power

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The RRC filter are required to reduced the inter-symbol interference (lSI), but it also can limit the bandwidth required for transmission and reduced Co-Channel interference. Two RRCs were required to filter the WCOMA demodulated complex signals (I and Q signal). Intersymbol Interference (lSI) happen when the tail of a pulse can "smear" into adjacent symbol interval, thereby interfering with the detection process and degrading the

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2 error performance [1]. Even in the absent of noise, the effect of filtering and channel-induced distortion lead to lSI. The lSI is illustrated in Figure 3 below.

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reduce the bandwidth of the signal, Inter Symbol Interference also can be countered using the root raised cosine filter. The Fourier transform of the root raised cosine pulse in frequency spectrum is a square which offers a brick wall like spectrum in communication channels which provides an ideal solution for the signal transmission [3].

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Figure 3: lSI interference. (a) Desired input. (b) lSI interference occur. For the baseband system, when G(t) is such a filter with single sided bandwidth lI2T (the ideal Nyquist filter), its impulse response, the inverse Fourier transform of G(t) is of the form get) sinc(tlT), shown in figure 3(a). This sinc(tlT)-shaped pulse is called the ideal Nyquist pulse; its multiple lobes comprise a mainlobe and sidelobes called pre- and post-mainlobe tails that are infinitely long. Nyquist establish that if each pulse of a received sequence is of the form sinc(tiT), the pulse can be detected without lSI [1]. Figure 3(b) illustrates how lSI is avoided.

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There are two successive pulses, get) and h(t - T). Even though get) has long tails, the figure shows a tail passing through zero amplitude at the instant (t T) when get - T) is to be sampled, and likewise all tails pass through zero amplitude when any other pulse of sequence get - kT), k ±1, ±2, ... .is to be sampled. Therefore, assuming that the sample timing is perfect, there will be no lSI degradation introduced [1]. For baseband system, the bandwidth required to detect liT such pulses (symbols) per second is equal to l/2T. a Nyquist pulse is one whose shape can be represented by sinc(tlT) function multiplied by another time function. Hence, there are countless number of Nyquist filters and corresponding pulse shapes. Amongst the class of Nyquist Filters, the most popular ones are the raised cosine and the root raised cosine [1]. =

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Figure 5: Bandwidth of RRC Filter The main features of a root raised cosine filter are as follows [3]: • The bandwidth of the signal is reduced considerably as the filter is implemented as low-pass filter. • Reduces the Inter-symbol interference which is caused due to the propagation medium which is free space or the wire that's the main limitation for the communication. • Can be implemented digitally and can provide high data rates which is very essential for the present day communication systems. • The digital filter can be implemented as both static and dynamic filter which enables its power efficiency as it can be configured dynamically checking the power of the adjacent channels. The Linear Time Invariant (LTI) model of a basic RRC filter is presented in figure. It is describe by the following difference equation [4]: lV - l

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Where x(n) is the current input sample, x(n-j) are discrete input samples delayed by j sample periods, blj) are the filter coefficients or taps and y(n) is the current discrete output sample of the filter [4].

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II. METHODOLOGY A.

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RRC Filter Overview

The raised cosine pulse takes on the shape of a Sinc pulse, which can be implemented as a digital filter which can

Figure 8 illustrates the summary of overall design flow for this paper. First the RRC Filter was designed and simulated in Matlab 7.0 to achieve the required frequency response, impulse response and bandwidth specification in WCDMA.

204

3 Filter coefficient and VHDL coding is then generated from the design filter. This VHDL coding was simulated in Modelsim SE 6.3f for verification before being synthesized. The VHDL coding is then synthesize using Xilinx ISE Simulator to know the gate level circuit, device utilization such as number of slices and flip flops and also the timing report for the RRC Filter. All the result is then being analyzed.

The filter coefficients were generated using the MATLAB FDA Tool which was quantized into fixed-point representation. Figure 10 show some of the 65 generated filter coefficient. These RRC Filter coefficients were required for designing RRC multiply accumulated unit (MAC) later. Quant1zed Numerator: -0.001190185546875 0.00018310546875 0.0015716552734375 0.001800537109375 0.00054931640625 -0.001251220703125 -0.0020751953125 -0.0010833740234375 0.0009765625 0.002288818359375 0.00140380859375 -0.0012359619140625 -0.00335693359375

RRC Filter Design and Simulation in Matlab 7.0

Generate Filter Coefficient

Generate VHDL Coding for RRC Filter

Figure 10: Generated filter coefficients. VHDL Coding Simulation

The RRC Filter is then realized into model as shown in Figure 11 below. This RRC Filter model is inserted in WCDMA transmitter module to rectifY its functionality as to reduce lSI interference.

in Modelsim SE 6.3f

Synthesize using XILINX ISE Simulator

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Result Analysis

The RRC Digital Filter was designed and analyzed in MATLAB Toolbox called Filter Design Toolbox with a finite number of bits for the wordlength. The FDA Tool that can be found in Filter Design Toolbox was executed and the FDA Tool window as shown in Figure 9 will appeared. The specification used to design this digital filter was Sampling Frequency, Fs 15.36 MHz, Cut-off Frequency, Fc l.92 MHz and Roll-off factor 0.22 with 65 tap coefficients and this specification IS accordance to the WCDMA requirements. =

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C. RRC Filter Design in VHDL

RRC Filter Design in Matlab 7.0

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Figure 8: RRC Filter design flow

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The filter design was implemented in Register Transfer Level (RTL) and behavioral style of coding by generating the design filter from Matlab 7.0 into VHDL coding. The RTL style of coding employs by building of small blocks and for this filter are memory and MAC blocks, in behavioral coding and uses these blocks to build the complete circuits. In behavioral style the whole code is coded according to the behavior of the circuit. The MAC block which consists of the multipliers and adders where MAC mean mUltiply accumulate unit the MAC units multiplier is a Booth multiplier which gives less delay than many other multipliers. The MAC structure was design based on equation (1), where blj) is the filter coefficient generated in Matlab 7.0. The structure of the MAC unit is as Figure 12 below, which is implemented using pipelined that can increase system's throughput and hence gave higher speed. _/

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The filter architecture was coded in VHDL coding behavioral and RTL. Figure 13 below show the top module

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Analysis of RRC Filter Architecture

The RTL and behavioral VHDL code where both synthesized for implementation on Xilinx Virtex III Pro FPGA using Xilinx ISE Simulator. The device utilization and timing summary report were analyzed. SIMULATION RESULT AND DISCUSSION

III. A.

Simulation Result in Matlab 7.0

The filter implemented here is a 65 tap Root Raised Cosine Filter with the specifications as follows, sampling frequency (fs) 15.36 MHz, cutoff frequency (fo) l.92 MHz and roll-off factor, a=0.22. The frequency response and impulse response for the RRC Filter shown in Figure 13 below. =

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To verify the stability of the designed RRC Filter, the Pole/Zero plot was used and the Pole/Zero plot for the RRC filter shown in Figure16 below. The Bounded Input Bounded Output (BIBO) stability criterian requires all poles of the transfer funtion to have an absolute value smaller than one. In other words, all poles must be located within a unit circle (radius 1) in z-plane. Since all poles located at the center of the axis, z 0, thefore this designed RRC Filter is stable. =

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Figure 14: Magnitude response(dB) for the RRC Filter. From the Figure 14, the past-bandwith is equal to 2.34MHz which satisfied the equation (2) earlier. While Figure 15 below show the impulse response for the design filter. The chip duration for the impulse response is calculated as Tc 2.3111981ls - 2.083333Ils, which give Tc 0.227865Ils or 227.865ns. This chip duration is approximately equal to chip duration required in UMTS as in equation 2.

Simulation Result in Modelsim SE 6.3f

The filter architecture that has been coded III VHDL coding is simulated in Modelsim SE 6.3f and the result shown in Figure 17 below. The clock period used in this VHDL coding is IOns.

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