Improved acquisition in a phase-locked loop using ...

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Journal of the Franklin Institute 352 (2015) 4188–4204 www.elsevier.com/locate/jfranklin

Improved acquisition in a phase-locked loop using sliding mode control techniques Paul T. Lanza IIa,b,n, Yuri B. Shtesselb,1, John L. Stensbyb,2 a

DESE Research, Huntsville, AL 35805, USA Department of Electrical and Computer Engineering, University of Alabama in Huntsville, Huntsville, AL 35899, USA

b

Received 24 June 2014; received in revised form 20 January 2015; accepted 1 June 2015 Available online 20 June 2015

Abstract In many phase-lock loop (PLL) applications, the naturally occurring pull-in process is too slow and unreliable. Therefore, PLLs use acquisition aids to mitigate the process of locking onto the phase of some input reference signal. Commonly used acquisition aids have deficiencies with limiting effects. For voltagecontrolled oscillator (VCO) sweeping, deficiencies include lock detector requirements and search rate limitations. For a charge-pump subsystem, the operated sequential phase detector (PD) is less resistant to errors than an analog multiplier PD. In order to overcome the deficiencies of common acquisition aids and improve PLL robustness to perturbations, it is proposed to use a conventional or a second order sliding mode controller (SMC/2-SMC) as an acquisition aid to provide robust finite-time phase-lock in the PLL. This improvement is achieved without the use of a lock detector, and the disabling of the acquisition aid is not necessary. The PLL aided by SMC/2-SMC is studied analytically and via simulations. A significant improvement of the PLL’s performance is demonstrated; specifically, the lock time is decreased, and the steady state phase error is reduced for a frequency ramp input. & 2015 The Franklin Institute. Published by Elsevier Ltd. All rights reserved.

Keywords: Phase locked loop; PLL acquisition aid; Sliding mode control; Super-twist control; PLL VCO sweep rate

n

Corresponding author. Tel.: +1 256 656 8148. E-mail addresses: [email protected] (P.T. Lanza II), [email protected] (Y.B. Shtessel), [email protected] (J.L. Stensby). 1 Tel.: þ1 256 824 6164. 2 Tel.: þ1 256 824 6258. http://dx.doi.org/10.1016/j.jfranklin.2015.06.001 0016-0032/& 2015 The Franklin Institute. Published by Elsevier Ltd. All rights reserved.

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1. Introduction A phase-locked loop (PLL) is an important signal tracking device that synchronizes its output signal with an input reference signal. The output signal is synchronized, or phase-locked, when it is in phase quadrature with the input signal. The process of bringing a PLL into phase-lock, which is known as acquisition, and continuously tracking the input reference signal can be achieved with a traditional PLL [1]. A functional diagram of a traditional PLL is shown in Fig. 1. The traditional PLL in Fig. 1 contains a phase detector (PD), a loop filter (LF), and a voltagecontrolled oscillator (VCO) set up in a feedback configuration. Other terms shown in Fig. 1 include the VCO gain K v 40 ðrad=ðsUVÞÞ, the PD gain K d 40 ðV=radÞ, the LF transfer function F ðsÞ, the PD output voltage gðtÞ, and the error control voltage eðtÞ. The input reference signal rðtÞ and the VCO output signal vðtÞ are sinusoidal signals; therefore, a sinusoidal analog multiplier PD is used in this configuration. Traditional PLLs are used in many applications including phase locked receivers, frequency synthesis, and motor speed control. The goal of the traditional PLL is to drive the VCO generated harmonic signal output phase θo ðtÞ to follow the commanded/received, processed harmonic signal input phase θi ðt Þ ði:e:; θo ðt Þ-θi ðt ÞÞ. As a part of this goal, the driving of θo ðt Þ-θi ðt Þ is to occur in finite time, or as time increases in the presence of bounded parametric uncertainties and external disturbances. This goal results in driving the phase error ϕðt Þ-0, where ϕðt Þ ¼ θi ðt Þ  θo ðt Þ. The PLL is said to be phase locked when the modulo-2π value of ϕðt Þ remains acceptably small over time so that the VCO signal leads the reference signal by a quarter of a period, approximately. Since the reference signal is known on-line only, the formulated task is a tracking problem. Although the traditional PLL can achieve its stated goal, multiple deficiencies exist that degrade its performance. The deficiencies of the traditional PLL can be summarized as follows:

 



The traditional PLL is susceptible to external disturbances. For instance, this can be caused by mechanical vibrations. Furthermore, VCO parametric uncertainties yield degradation of the PLL’s performance. First and second order PLLs cannot lock with ϕðt Þ ¼ 0 on the phase of a reference signal with a time varying frequency (i.e. a ramp signal). When a ramp signal variation exists, a first order PLL (a PLL where F ðsÞ ¼ 1) can exhibit an infinite steady state error while a second order PLL (a PLL with a first order LF) exhibits a finite steady state error. The naturally occurring pull-in process of a traditional PLL can be too slow and unreliable. This process may not achieve acceptably agile performance for particular applications, such as where the PLL closed-loop bandwidth is made small in order to limit the detrimental influence

Fig. 1. A functional diagram of a traditional PLL with sinusoidal waves.

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of noise on the reference signal. In order to mitigate the pull-in process, an acquisition aid is used in the PLL; however, each type of acquisition aid has deficiencies and limitations of its own as discussed in the next paragraph.

Popular acquisition aids, such as a VCO sweeping signal or a charge-pump subsystem, are used for mitigating phase-lock [1–3]. The VCO sweeping signal is an external alternating ramp signal that is injected into the VCO to aid the search for the input reference signal [2]. The charge-pump subsystem distributes a fast switching charge into the LF based on the phase error [3]. However, there are some downsides of using these acquisition aids. Sweeping the VCO constrains the PLL to a blind search and a limited search rate; therefore, the expected input frequency range must be known and the maximum search rate must be calculated [2]. Additionally, sweeping the VCO requires the use of an external lock detector circuit to turn off the sweep signal upon phase lock detection. Otherwise, the acquisition aid produces a phase error in the locked PLL [1,3]. The charge-pump PLL uses a memory containing sequential PD, which is less resistant to errors when compared to an analog multiplier PD [3]. This paper proposes the use of a conventional or a second order sliding mode controller (SMC/ 2-SMC) instead of the above-mentioned acquisition aids. The SMC/2-SMC aid is to improve phase acquisition of a PLL by addressing the stated deficiencies above. It is known that SMCs/2SMCs are robust to matched uncertainties and external disturbances while providing finite time convergence [5–13]. Second order sliding mode controllers [9,12,13] retain the robustness property of an SMC while having the capability to generate a continuous control signal. They also achieve the enhanced accuracy of stabilization of the sliding variable that is proportional to ðΔt Þ2 , where Δt is a time increment, when implemented in discrete time. The expected advantages, in using the SMC/2-SMC [4–13] to aid the PLL instead of the mentioned acquisition aids, are listed below:

   

Within a traditional PLL, phase-lock (zero phase error) is achieved in less time. An external lock detector circuit is not required. While the SMC provides a fast switching solution, the 2-SMC allows generation of a continuous control signal that can be beneficial for PLL applications. The implementation of SMC/2-SMC is not complex and is compatible with the analog multiplier phase detector for superior tracking of signals.

The SMC and 2-SMC controller design for the PLL is performed in this paper upon the following assumptions: Assumption 1 A second order PLL (Type II) that uses a proportional plus integral (PI) LF is considered. Assumption 2 Sinusoidal waves are used for input reference and VCO signals. However, other wave types are compatible.

The organization of the paper is as follows. The traditional PLL is modeled and simulated to common input test signals in Section 2. Also in Section 2, the simulation is performed with an acquisition aid of a VCO sweep signal for comparison with the final results. Sliding mode control aid

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techniques are studied and applied to the PLL system in Section 3. Both proposed SMC and 2-SMC implementations are given in Section 4, and their efficiencies are demonstrated via simulations in Section 5. These simulations are performed without the presence of noise for simplicity of analysis. The conclusions are given in Section 6. The proofs of the theorems can be found in Appendices 1 and 2. 2. Traditional PLL configuration: Mathematical model and motivation example The commonly used mathematical model of a PLL (Fig. 1) [1,3], which is used for SMC and 2-SMC acquisition aid design, is studied in this section. The transfer function of the proportional plus integral LF used is F ð sÞ ¼

eðsÞ sþα ¼ ; gðsÞ s

α40:

Equations of the input reference signal rðtÞ and the VCO output signal vðtÞ are pffiffiffi r ðt Þ ¼ 2A sin θi ðt Þ;   Z pffiffiffi pffiffiffi vðt Þ ¼ 2K 1 cos θo ðt Þ ¼ 2K 1 cos ωo t þ K v eðt Þ dt ;

ð1Þ

ð2Þ ð3Þ

pffiffiffi pffiffiffi where 2K 1 and 2A are signal amplitudes, ωo is the R VCO center frequency ðrad=sÞ, θi ðtÞ is the reference signal’s phase ðradÞ, and θo ðt Þ ¼ ωo t þ K v eðtÞdt is the VCO phase ðradÞ. The output of the analog multiplier PD is computed using Eqs. (2), (3), and a trigonometric identity to yield gðt Þ ¼ K d r ðt Þvðt Þ ¼ AK 1 K d ½ sin ðϕðt ÞÞ þ sin ð2ωo t þ θ1 þ θ2 Þ;

ð4Þ

where the variables θ1 and θ2 are defined as θ1 ðt Þ ¼ θi ðt Þ ωo t; θ2 ðt Þ ¼ θo ðt Þ  ωo t:

ð5Þ

Eq. (5) characterizes the relative phase variables θ1 and θ2 with respect to the quiescent phase ωo t [1]. Additionally, the phase error ðradÞ is ϕðt Þ ¼ θi ðt Þ θo ðt Þ ¼ θ1 ðt Þ θ2 ðt Þ:

ð6Þ

The traditional PLL described by Eqs. (1)–(6) is simulated in order to study the phase error ϕðt Þ response to common PLL test signals. The simulation diagram of this PLL is shown in Fig. 2. Multiple simulations are run under specific conditions using Python programming models originally developed in the appendices of [4]. Each simulation is run without noise and without

Fig. 2. The simulation diagram of a traditional second order Type II PLL, where α ¼ 100, K d ¼ K v ¼ 20, and ωo ¼ 20; 000π.

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external disturbances. The parameterization of the PLL in Fig. 2 includes the p chosen phase ffiffiffi detector gain K d ¼ 20, VCO gain K v ¼ 20, and signal amplitudes of A ¼ K 1 ¼ 1= 2 for overall pffiffiffi unity amplitudes. The integrator gain is selected to satisfy the damping ratio ξ ¼ 1= 2. The integrator gain is solved for by the common second order closed loop damping ratio and natural frequency equations [1] pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffi ξ ¼ G=4α; ωn ¼ αG; ð7Þ where G is the closed loop gain defined in [1,3,4] as G ¼ AK 1 K v K d . As a result, the desired integrator gain is α ¼ 100. The signal values of the simulated PLL in Fig. 2 are given. A constant VCO center frequency is selected as ωo ¼ 20; 000π rad=s ð10 kHzÞ. The input test signals used in the simulations are a frequency step of  400π rad=s ð 200 HzÞ and a frequency ramp with the rate of 200π rad=s2 ð100 Hz=sÞ. These test  signals are represented as r ðt Þ ¼ sin ððωo  400π Þt Þus ðtÞ for the frequency step and r ðt Þ ¼ sin ωo t þ 200πt 2 us ðt Þ for the frequency ramp, where us ðtÞ is the unit step function. In order to reconstruct the phase error ϕðtÞ, the following assumptions are made: Assumption 3 The double frequency term sin ð2ωo t þ θ1 þ θ2 Þ in the PD output gðtÞ, as defined in Eq. (4), is significantly attenuated by the LF and VCO dynamics. Therefore, gðtÞ is approximately estimated as gðt Þ ¼ AK 1 K d sin ϕðtÞ:

ð8Þ   Assumption 4 The feasible set of the phase error ϕðtÞ is limited by ϕðtÞ r π=6. As a result, the PD output in Eq. (8) can be linearized, which takes the form ð9Þ g^ ðt Þ ¼ AK 1 K d ϕðtÞ: Note that if g^ ðt Þ-0, then ϕðtÞ also converges to zero thus achieving phase lock. As a result, gðt Þ-0. Therefore, g^ ðt Þ defined in Eq. (9) will be used in the control model of the PLL, while gðt Þ defined in Eq. (4) is used in the simulation model. The simulation results of the PLL in Fig. 2 are presented in Fig. 3(a) and (b). Specifically, the demonstrated response is gðtÞ passed through a low-pass filter with the transfer function H ðsÞ ¼ 1=ðτs þ 1Þ, where τ ¼ 0:001, to filter out the double frequency term in Eq. (4). The filtered gðt Þ response to the given frequency step is shown in Fig. 3(a), and it converges to zero asymptotically with a settling time of approximately 0.45 s. The filtered gðt Þ response to the given frequency ramp is shown in Fig. 3(b), and it converges to a non-zero amplitude that is proportional to the rate of the frequency ramp as verified in [1,3]. In order to mitigate phase-lock in response to a frequency step input, the popular acquisition aid of sweeping the VCO is implemented into the simulation. Sweeping the VCO is achieved by inserting an alternating ramp signal into the VCO [2]. However, the sweep signal can be modeled as a continuous ramp signal without any loss of generality [2]. Therefore, a ramp signal modeled  as Rt=K v ðV Þ, where R=K v ðV=sÞ is the slope of the signal and R rad=s2 is the sweep rate, is summed with the VCO control voltage eðtÞ in Fig. 2. This sum becomes the new VCO input [2,4]. The VCO output signal in Eq. (3) can now be written with the ramp term as   Z pffiffiffi  eðt Þ þ Rt=K v dt : vðt Þ ¼ 2K 1 cos ωo t þ K v ð10Þ

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Fig. 3. Error response (rad) of the traditional second order Type II PLL to (a) a frequency step, (b) a frequency ramp, and (c) a frequency step with a sweep signal injected into the VCO. Each graph on the right shows a zoomed in portion of the graph to its left from t ¼ 0:8 s to t ¼ 0:8003 s.

The simulation result using Eq. (10) is presented in Fig. 3(c) for the input frequency step signal r ðt Þ ¼ sin ððωo  400π Þt Þus ðtÞ.  The maximum sweep rate that guarantees phase-lock is calculated in [4] as R ¼  10; 044 rad=s2 , or R=K v ¼  502:2 V=s . The sweep rate is set to a negative value since the frequency step is known to be a negative value; however, input signals are not typically known resulting in a blind search. The result of this simulation in Fig. 3(c) shows that the filtered output of the PD gðt Þ does not converge to zero, but that the PLL locks with a non-zero steady state error. However, it shows that phase lock is acquired in a faster time as it crosses zero phase error at approximately 0.10 s and settles at approximately 0.15 s. It is noted that this PLL is not simulated with a frequency ramp input signal. An input frequency ramp only adds to the VCO sweep rate. Since this PLL is implemented with its maximum sweep rate, a frequency ramp input signal may cause the PLL to sweep past its lock point. Due to this reason, this simulation is omitted. From the simulation results in Fig. 3(c), the deficiencies of aiding the PLL by a VCO sweep signal are noted. The second

order Type II PLL(Fig. 2) can achieve phase-lock asymptotically with zero steady state error ϕss ðt Þ ¼ lim ϕðt Þ ¼ 0 , computed in accordance with Eq. (8) or (9), only in t-1 response to a frequency step or phase step [1]. Therefore, inserting a ramp signal into the VCO to mitigate the gðt Þ convergence results in a non-zero steady state value in response to an input frequency step. From this observation, the VCO sweep signal can only be implemented with zero steady state phase error in this PLL with a lock detector [1]. The absence of a lock detector to turn off the sweeping (ramp) signal, as soon as ϕðtÞ becomes equal to zero, results in a non-zero steady state phase error. This produces lower accuracy and additional stress on the system after lock is acquired [3]. Using a lock detector adds complexity to the system and increases the system’s cost. Additional to the lock detector requirement, the sweep rate is limited [2], and thus limits the PLL’s system improvement capability.

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In this work, it is proposed to augment the existing input of the LF in Eq. (4) by aiding it with a conventional or a second order sliding mode control (SMC/2-SMC) function. These controls are expected to eliminate the steady state phase error and guarantee the desired convergence time in PLL systems in the presence of parametric uncertainties and external disturbances. They are also expected to eliminate the need for a lock detector when mitigating phase error response in a second order Type II PLL. Remark 1. Note that the SMC/2-SMC function results in an automatic control of a VCO sweeping signal. Consider an output segment of the SMC/2-SMC function as a constant signal with non-zero amplitudes. The integrator in the LF (see Fig. 2) integrates the additive constant signal into an additive ramp signal, which is summed with the error control voltage eðt Þ [3,4]. Since a conventional SMC alternates about zero (as shown in later sections), the integrated signal yields an alternating ramp signal. Therefore, this technique is similar to VCO sweeping, except that the resulting ramp signal is controlled by the SMC/2-SMC function, which is a function of gðt Þ. 3. Problem formulation Before designing the SMC/2-SMC control law, the system given by Eqs. (1)–(9) is presented in a state variable format [4]. The state variable format is formed by setting x1 ðt Þ ¼ θo ðtÞ to get ( x_ 1 ¼ K v ðαx2 þ uðx1 ; x2 ; t ÞÞ þ ωo þ φðx1 ; x2 ; t Þ ; ð11Þ x_ 2 ¼ uðx1 ; x2 ; t Þ where uðx1 ; x2 ; t Þ is the   system control  to be designed and φðx1 ; x2 ; t Þ describes the unknown bounded perturbation φðx1 ; x2 ; t Þ r L . The unknown bounded perturbation may occur due to parametric uncertainties of the LF and VCO, mechanical vibrations, temperature, power supply switching, and external signal noise. Note that the system control uðx1 ; x2 ; t Þ in the traditional PLL is the phase detector output gðt Þ in Eq. (4), i.e. uðx1 ; x2 ; t Þ ¼ gðt Þ. The problem is to redesign the control law u ¼ uðx1 ; x2 ; t Þ that drives ϕðt Þ ¼ θi ðt Þ  x1 ðt Þ-0

ð12Þ

in finite time in the system described by Eq. (11). Holding Eq. (12) means that the PLL system locks on the phase θi ðt Þ of the input signal rðtÞ. The measurement available in the system described by Eq. (11) is the output of the PD gðtÞ. In accordance with Assumption A3, gðtÞ is replaced by its approximation g^ ðtÞ from Eq. (9) for the control law design. Eq. (9) can be rewritten as g^ ðt Þ ¼ AK 1 K d ðθi ðt Þ x1 ðt ÞÞ

ð13Þ

by substituting Eq. (12). From Eq. (13), the PLL system is locked if g^ ðt Þ ¼ 0. Therefore, the problem is reduced to designing a control law u ¼ uðx1 ; x2 ; t Þ that drives g^ ðt Þ-0 in finite time. 4. Sliding mode control of PLL The development of the SMC and 2-SMC implementations for the PLL is presented in this section. Section 4.1 presents a fast-switching conventional SMC for aiding the PLL. The continuous supertwisting 2-SMC, which is more suitable for aiding in PLL applications, is studied in Section 4.2. Remark 2. For both SMC and 2-SMC implementations, the original PLL is completely in-tact. In other words, if the SMC/2-SMC is removed from the loop, the original PLL still remains. Therefore, the SMC and 2-SMC implementations are acquisition aids.

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4.1. Conventional sliding mode control The conventional SMC used for aiding the system described by Eq. (11) is presented. This system is of relative degree one with the internal dynamics x_ 2 ¼ uðx1 ; x2 ; t Þ, which are proven to be stable in Theorem 1 presented below. The properties of the PLL aided by conventional SMC are formulated in the following theorem. Theorem 1. Assume that

    

the PLL dynamics are given by Eq. (11);   the perturbation φðx1 ; x2 ; t Þ is bounded: φðx1 ; x2 ; t Þ r L1 ;  the derivative of the input signal phase θi ðt Þ is bounded: θ_ i ðt Þ r L2 ; the state variable x2 is bounded in a reasonable performance domain of the PLL: jx2 j rL3 ; the variable g^ ðt Þ in Eq. (9) or (13) is measured;

  then the PLL locks on the input signal phase in finite time t F r g^ ð0Þ=ρ; ρ40 and stays locked afterwards (i.e. g^ ðt Þ ¼ 0 8 t Z t F ) via conventional sliding mode control uðt Þ ¼ cp g^ ðt Þ þ

ðρ þ L4 Þ signðg^ ðt ÞÞ; cp 40; G ¼ AK 1 K d K v ; G

ð14Þ

where L4 ¼ AK 1 K d ðL2 þ K v αL3 þ ω0 þ L1 Þ:

ð15Þ

Proof of the theorem is given in Appendix 1. 4.2. Super-twisting 2-SMC The continuous second order super-twisting controller (2-SMC) [9,12,13] used for aiding the system described by Eq. (11) is presented. When it is applied to systems of relative degree one, it drives the sliding variable and its derivative to zero in finite time. One of the most important features of the supertwisting control is its continuity. Therefore, it is beneficial to apply the super-twisting control law to the PLL system controller in order to mitigate chattering of the aided control signal. The properties of the PLL aided by the super-twisting controller are formulated in the following theorem. Theorem 2. Assume that

  

the PLL dynamics are given by Eq. (11); the  following conditionholds in a reasonable performance domain of the PLL _   _  cp Gg^ ðt Þ þ ξðx1 ; x2 ; t Þ r H; c p 40; H40; where ξðx1 ; x2 ; t Þ ¼ AK 1 K d θ_ i ðt Þ K v αx2  ω0  φðx1 ; x2 ; t Þ and g^ ðt Þ is defined in Eq. (9) or (13); the variable g^ ðt Þ in Eq. (9) or (13) is measured;

then the PLL locks on the input signal phase in finite time and stays locked afterwards (i.e. g^ ðt Þ ¼ 0 for all consecutive time) via super-twisting control i 1 h  1=2 λ g^ ðt Þ signðg^ ðt ÞÞ þ v2 ðtÞ ; cp 40; G ¼ AK 1 K d K v uðt Þ ¼ cp g^ ðt Þ þ G

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v_ 2 ðt Þ ¼ βsignðg^ ðt ÞÞ

ð16Þ

with λ ¼ 1:5H 1=2 , β ¼ 1:1H. Proof of the theorem is given in Appendix 2. It is worth noting that the presented choice of the values for the coefficients λ; β [7,8,12] is viable but not unique. Furthermore, they can be selected based on conditions derived using Lyapunov function techniques [14]. 5. Case study The studied unperturbed, φðx1 ; x2 ; t Þ ¼ 0, second order Type II PLL aided by the proposed SMC/2-SMC (from Section 4) is simulated. All simulations are performed using the Euler method with the step size 10  6 s. Multiple sets of simulations are presented in order to show the performance of the PLL with the SMC/2-SMC aid. Each simulation set shows the phase error responses to an input frequency step and an input frequency ramp. Each set uses the same signals and gains as the simulated traditional PLL in Section 2 in order to show the effectiveness of the SMC/2-SMC implementation. The VCO center frequency ωo is set equal to 20,000π, as in Section 2, and remains unchanged for all simulations. The reference signals, both frequency step and frequency ramp, in each simulation set are described by the same equations for r ðt Þ in Section 2. Additionally, the SMC/2-SMC aid response is shown for each simulation. Therefore, the term u1 ðt Þ is introduced where uðt Þ ¼ cp g^ ðt Þ þ u1 ðt Þ;

ð17Þ

such that u1 ðt Þ represents the SMC/2-SMC aid output. The SMC/2-SMC aid output helps show the characteristics of the aid being used as well as the disturbance compensation. The gain magnitudes of the SMC/2-SMC implementation are another important element of the simulated phase error response. Eq. (14) shows that there are two components of the conventional SMC gain, ρ and L4 . The component ρ is used to determine the maximum reaching time, whereas L4 is calculated directly from Eq. (15). The component L4 is a very large magnitude, which makes ðρ þ L4 Þ=G a large magnitude. A gain with a large magnitude is not desired in a practical sense due to the presence of noise. Therefore, smaller gain magnitudes are used within the simulations presented in this section.

Fig. 4. The configuration diagram of the second order Type II PLL with SMC implementation shown with the optional low-pass filter.

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5.1. Simulations of PLL aided by conventional SMC The configuration diagram of the second order Type II PLL aided by conventional SMC is presented in Fig. 4. Fig. 4 presents an optional low-pass filter (LPF), which is explained in more detail later in this section. In the first set of simulations, the SMC gain magnitude ρ þ L4 is selected such that u1 ðt Þ yields a ramp signal, after the LF integration, with a rate equal to the PLL maximum   sweep rate. Recall that the maximum sweep rate given in Section 2 is R=K v ¼  502:2 V=s .  Therefore, the total gain magnitude of the conventional SMC is calculated by R=K v =α, which yields ρ þ L4 ¼ 5:022. This gain value is used in the first set of simulations along with cp ¼ 1. The first set of simulations is also performed without the optional LPF. The phase error and SMC aid responses to each test signal are presented in Fig. 5, and they are compared with the traditional PLL simulation results. The phase error response to the frequency

Fig. 5. Simulation results for the second order Type II PLL with conventional SMC implementation, without the optional LPF, and with gain value ρ þ L4 ¼ 5:022. The graphs on the left show the error (rad) and the SMC aid responses to the frequency step and frequency ramp input signals. Each graph on the right shows a zoomed in portion of the graph to its left from t ¼ 0:4 s to t ¼ 0:4003 s.

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step input shows that it converges to zero asymptotically with a settling time near 0.25 s. The phase error converges to zero in less time than the PLL without any aid (see Fig. 3(a)). The phase error response to the frequency ramp input converges to a non-zero value asymptotically. This gðt Þ response is less than the gðt Þ response of the traditional PLL with frequency ramp input (Fig. 3(b)). The SMC aid response u1 ðt Þ shows high frequency switching, and its average should follow the disturbance. The disturbance at the SMC input includes the double frequency term, thus the response u1 ðt Þ in Fig. 5 shows an average close to zero. The results in Fig. 5 are also compared with the simulation results from sweeping the VCO in Section 2. From the results of the frequency step input, sweeping the VCO with an implemented lock detector may still converge to zero in a faster time by comparison of Fig. 3(c). From Fig. 3(c), an implemented lock detector should turn off the sweep signal around 0.1 s, and additional time may be required to allow the phase error signal to settle. The conventional SMC aid follows the

Fig. 6. Simulation results for the second order Type II PLL with conventional SMC implementation, with the optional LPF, and with gain value ρ þ L4 ¼ 5:022. The graphs on the left show the error (rad) and SMC aid responses to the frequency step and frequency ramp input signals. Each graph on the right shows a zoomed in portion of the graph to its left from t ¼ 0:4 s to t ¼ 0:4003 s.

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non-linear input and disturbances. This causes the phase error to alternate about zero multiple times as shown in Fig. 5. The alternating accounts for the slower acquisition time with the equivalent maximum sweep rate. Although this seems to put the PLL with the SMC aid at a disadvantage, later simulations show the advantage of the SMC aid. Furthermore, phase-lock is guaranteed when the SMC aided PLL has an input frequency ramp signal. The PLL with a VCO sweep signal at its maximum sweep rate cannot guarantee phase-lock with an input frequency ramp signal. For the second set of simulations, Fig. 4 is simulated under the same conditions as the first set of simulations, except the optional LPF included. The LPF is described by the transfer function H ðsÞ ¼ 1=ðτs þ 1Þ, where τ ¼ 0:001. The LPF further attenuates the double frequency term at the SMC input to provide a smoother input. The simulated phase error and control responses to each test signal are presented in Fig. 6. Adding the LPF improves the phase error response to both the frequency step and frequency ramp inputs as shown in Fig. 6.

Fig. 7. Simulation results for the second order Type II PLL with conventional SMC implementation, with the optional LPF, and with an increased gain value ρ þ L4 ¼ 20. The graphs on the left show the error (rad) and SMC aid responses to the frequency step and frequency ramp input signals. Each graph on the right shows a zoomed in portion of the graph to its left from t ¼ 0:4 s to t ¼ 0:4003 s.

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Remark 3. The added optional LPF can be considered as unmodeled/parasitic dynamics for the proposed sliding mode controllers that increases system’s relative degree. A rigorous analysis of SMC and 2-SMC systems with unmodeled/parasitic dynamics is presented in quite a few works. A good coverage of these techniques can be found in the work [13]. The simulation results in Fig. 6 are analyzed. The phase error response to the frequency ramp input, shown in Fig. 6, immediately converges to zero asymptotically. The phase error response to the frequency step input converges to zero in a faster time, compared to Fig. 5, of approximately 0.16 s. This settling time is also closer to the phase error settling time of the PLL aided by the VCO sweep signal at the maximum sweep rate (Fig. 3(c)). However, since the PLL aided by the VCO sweep signal must implement a lock detector that implements a decision rule, the phase error settle time may further increase. The SMC aid does not have to implement a lock detector. The third set of simulations shows another advantage of the SMC aid by increasing the SMC gain. Because the SMC gain is not confined to a limit, unlike the rate of sweeping the VCO, the gain can be raised above ρ þ L4 ¼ 5:022. This set is simulated under the same conditions as the previous set of simulations, except the gain is increased arbitrarily to ρ þ L4 ¼ 20. The simulated phase error and control responses to each test signal are presented in Fig. 7. The phase error response to the frequency ramp input continues to immediately converge to zero. The phase error response to the frequency step input converges to zero around 0.03 s. The larger SMC gain allows the PLL to lock in a faster time. This convergence time is significantly faster than sweeping the VCO at the maximum sweep rate. Therefore, the conventional SMC aid can provide faster convergence times without the need to implement a lock detector. 5.2. Simulations of PLL aided by super-twisting 2-SMC The last set of simulations shows the results of the second order Type II PLL aided by a supertwisting 2-SMC. The super-twisting 2-SMC is more suitable for applications due to its continuous nature. The configuration diagram of the second order Type II PLL aided by a super-twisting

Fig. 8. The configuration diagram of the second order Type II PLL with super-twisting 2-SMC implementation shown with the optional low-pass filter.

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Fig. 9. Simulation results for the second order Type II PLL with super-twisting 2-SMC implementation, with the optional LPF, and with a gain value H ¼ 80. The graphs on the left show the error (rad) and 2-SMC aid responses to the frequency step and frequency ramp input signals. Each graph on the right shows a zoomed in portion of the graph to its left from t ¼ 0:4 s to t ¼ 0:4003 s.

2-SMC is presented in Fig. 8. This implementation is simulated with the same test signals, with the optional LPF, and an arbitrary gain value of H ¼ 80, which gives λ ¼ 13:42 and β ¼ 88. The phase error and 2-SMC aid responses are shown in Fig. 9. The phase error response to the frequency step input converges to zero at around 0.02 s. The phase error response to the frequency ramp input converges quickly to an extremely small non-zero amplitude. With this particular gain value used, the simulated phase error responses to the frequency step and frequency ramp inputs are better than all of the previous simulations. Furthermore, the 2-SMC aid response shows that it has smaller amplitude after phase-lock is acquired and has a continuous signal that compensates for disturbances. The smaller amplitude of the aid response yields less stress on the system after phaselock. Therefore, the super-twisting 2-SMC is a suitable and superior aid providing fast convergence times for many PLL applications.

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6. Conclusion The improvement of the acquisition aid for a phase-locked loop (PLL) system is considered. Currently used acquisition aids, in which the goal is to mitigate the locking of the VCO output phase onto the phase of the input signal, have some deficiencies, including lock detector requirements and search rate limitations. The conventional sliding mode and second order sliding mode control (SMC/2-SMC) based acquisition aids are proposed and studied in this work both analytically and via simulations. Both acquisition aids provide robust, faster finite-time phaselock in the PLL. This improvement is achieved without the use of a lock detector, which requires consecutive disabling of the acquisition aid. Each implemented SMC and 2-SMC based acquisition aid has its advantages. The traditional fast-switching SMC provides a robust response and is the easiest acquisition aid to implement. Also, by knowing the maximum absolute value of the phase error or the cumulative disturbance, the reaching time can be easily calculated. The super-twisting 2-SMC acquisition aid provides a robust continuous action, but is more complicated in implementation. Both SMC/2-SMC acquisition aids have the ability to precisely follow the input signal and compensate for the bounded cumulative disturbance, which the other acquisition aids cannot provide. The simulations confirm a significant improvement of the PLL’s performance; specifically, the lock time is decreased, and the steady state phase error is reduced for a frequency ramp input. The proposed SMC/2-SMC aids can be used in PLLs incorporating other types of input signals, including logic level binary signals. They may be also beneficial in other types of PLLs. Appendix 1. Proof of Theorem 1 The g^ ðt Þ—input–output dynamics are derived taking into account Eq. (11) g_^ ðtÞ ¼  v1 ðt Þ þ ξðx1 ; x2 ; t Þ

ðA1Þ

where v1 ðt Þ ¼ Guðx1 ; x2 ; t Þ; G ¼ AK 1 K d K v ;

ðA2Þ

 ξðx1 ; x2 ; t Þ ¼ AK 1 K d θ_ i ðt Þ  K v αx2  ωo  φðx1 ; x2 ; t Þ :

ðA3Þ

The term ξðx1 ; x2 ; t Þ is assumed bounded in a reasonable performance domain of the PLL:   ξðx1 ; x2 ; t Þ r AK 1 K d ½L2 þ K v αL3 þ ωo þ L1  ¼ L4 : A candidate to the Lyapunov function is introduced V ðt Þ ¼

1 2 g^ ðt Þ; 2

ðA4Þ

and its derivative is computed as V_ ðt Þ ¼ g^ ðt Þg_^ ðt Þ ¼ g^ ðt Þð  v1 ðt Þ þ ξðx1 ; x2 ; t ÞÞ:

ðA5Þ

Substituting the control law uðt Þ ¼ cp g^ ðt Þ þ

ð ρ þ L4 Þ signðg^ ðt ÞÞ; cp 40; G

ρ40;

ðA6Þ

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into Eq. (A5) obtains

pffiffiffi       V_ ðt Þ ¼ g^ ðt Þg_^ ðt Þr  cp G^g2 ðt Þ ðρ þ L4 Þg^ ðt Þ þ L4 g^ ðt Þ r  ρg^ ðt Þ ¼  ρ 2V 1=2 :

ðA7Þ

Eq. (A7) means that the g^ ðtÞ—dynamics in Eq. (A1) are asymptotically stable with the finite convergence time. The convergence time is calculated via integration of Eq. (A7) from 0 r τ r t F , and desiring V ðt F Þ ¼ 0, yielding   g^ ð0Þ 2V 1=2 ð0Þ p ffiffi ffi ¼ : ðA8Þ tF r ρ 2ρ Therefore, the PLL in Eq. (11) locks onto the input signal phase in finite time, i.e. g^ ðt Þ ¼ 0-ϕðt Þ ¼ 0 8 t Z t F . If the estimated value g^ ð0Þ is known, then the parameter ρ can be selected to achieve the desired reaching time using Eq. (A8). The parameter cp in Eq. (A6) also effects the convergence   time and can be tuned up to mitigate the convergence time, especially for large values of g^ ð0Þ. The stability (input–output boundedness) of the internal/zero dynamics x_ 2 ¼ uðx1 ; x2 ; t Þ

ðA9Þ

is verified in the sliding mode, when g^ ðt Þ ¼ 0. It is verified by substituting v1eq ðtÞ, which is computed based on g_^ ðt Þ ¼ 0 as  v1eq ðt Þ ¼ AK 1 K d θ_ i ðt Þ  K v αx2  ωo  φðx1 ; x2 ; t Þ ; ðA10Þ into Eq. (A2) along with Eq. (A9). As a result, Eq. (A9) becomes in the sliding mode when 1 _ ðA11Þ θi ðt Þ ωo  φðx1 ; x2 ; t Þ ; α40: x_ 2 ¼  αx2 þ Kv The unperturbed Eq. (A11) is asymptotically stable. Since the terms θ_ i ðt Þ and ωo are bounded and the term φðx1 ; x2 ; t Þ is assumed bounded, a solution of Eq. (A11) x2 is also bounded. This analysis of the internal/zero dynamics guarantees that the conventional SMC in Eq. (14) is implementable, thus Theorem 1 is proven. Appendix 2. Proof of the Theorem 2. The g^ ðt Þ—input–output dynamics are considered as in Eq. (A1), where the bounded disturbance ξðx1 ; x2 ; t Þ and the control function v1 ðt Þ are defined in Eqs. (A2) and (A3). The super-twisting control uðt Þ that drives g^ ðt Þ, g_^ ðt Þ-0 in finite time is derived as follows [12,13]: i 1 h  1=2 λ g^ ðt Þ signðg^ ðt ÞÞ þ v2 ðtÞ ; G ¼ AK 1 K d K v uðt Þ ¼ cp g^ ðt Þ þ G ðA12Þ v_ 2 ðt Þ ¼ βsignðg^ ðt ÞÞ; λ; β; cp 40: Substituting Eq. (A12) into (A1) obtains  1=2 g_^ ðt Þ ¼  λg^ ðt Þ signðg^ ðt ÞÞ  v2 ðt Þ þ ψ ðx1 ; x2 ; t Þ; v_ 2 ðt Þ ¼ βsignðg^ ðt ÞÞ; λ; β; cp 40;

ðA13Þ

where the derivative of ψ ðx1 ; x2 ; t Þ ¼  cp G^gðt Þ þ ξðx1 ; x2 ; t Þ is assumed bounded in the reasonable performance domain of the PLL as ψ_ ðx1 ; x2 ; t Þ r H; H40. It is known [10,12] that the sufficient conditions for selecting the coefficients λ and β that guarantee the finite time convergent dynamics in Eq. (A13), i.e. g^ ðt Þ; g_^ ðt Þ-0, are as follows:

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β4H; sffiffiffiffiffiffiffiffiffiffiffi 2 ðβ þ H Þð1 þ qÞ ; λ4 βH 1 q

ðA14Þ

    where HoqU m ; 0oqo1 and v1 ðt Þ r U m . In order to enforce inequality v1 ðt Þ r U m , the control law in Eq. (A13) can be modified as [10,12]   ( β signðϕðt ÞÞ; if v2 ðt Þ r U m   v_ 2 ðt Þ ¼ : ðA15Þ  v2 ðt Þ; if v2 ðt Þ4U m The simplified condition for selecting the coefficients λ and β are [10,12] pffiffiffiffi λ ¼ 1:5 H ; β ¼ 1:1H:

ðA16Þ

Finally, the control law uðt Þ in Eq. (15) is defined in accordance with Eqs. (A2) and (A12). The stability (input–output boundedness) of the internal/zero dynamics is proven by analogy with the proof of Theorem 1, thus Theorem 2 is proven.

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