Improved ESD Protection in Advanced FDSOI by Using Hybrid SOI/Bulk Co-integration Thomas Benoist1,2,3, Claire Fenouillet-Beranger1,2, Nicolas Guitard1, Jean-Luc Huguenin1,2, Stéphane Monfray1,2, Philippe Galy1, Christel Buj2, Francois Andrieu2, Pierre Perreau1,2, David Marin-Cudraz1, Olivier Faynot2, Sorin Cristoloveanu3, Pierre Gentil3 (1) STMicroelectronics Crolles, 850 rue Jean Monnet F-38926 Crolles Cedex, France Tel : + 33 4 76 92 57 24, e-mail :
[email protected] (2) CEA-Leti Minatec, 17 rue des Martyrs 38054 Grenoble cedex 9, France (3) IMEP-LAHC, Grenoble INP, Minatec, 3 parvis Louis Néel, BP 257, 38016 Grenoble Cedex 1, France
Abstract - We investigate the influence of different technological parameters on ESD robustness in advanced FDSOI devices. From Transmission Line Pulse (TLP) measurements, a comparison with other technologies enables us to evaluate the impact of ultrathin film and buried oxide. A solution based on hybrid SOI/bulk cointegration by using Silicon-On-Nothing technology is presented in order to improve ultra-thin film ESD performance.
I-Introduction The FDSOI (Fully Depleted Silicon On Insulator) technology lies among the most promising approaches for the next CMOS generations. Its beneficial properties, such as the leakage current reduction, good control of short channel effects [1], no latch-up and high immunity to the Vt variability [2], offer an interesting alternative to bulk technologies. Furthermore, the introduction of high-k dielectrics and midgap metal gate stack results in an additional reduction of the gate leakage current and provides symmetrical threshold voltage for NMOS and PMOS, around 0.45V, without requiring any channel doping. However, in ultra-thin SOI technologies, the thicknesses of the active silicon layer and buried oxide (BOX) limit the integration of ESD protections. Indeed, the presence of the BOX layer reduces leakage currents but also prevents the thermal dissipation. In addition, the reduction of the active silicon layer thickness (TSi), necessary for controlling the short-channel effect, also acts on the device mechanisms in the strong injection regime, such as ESD events. The inclusion of the high-k metal gate (HKMG) stack can change the device behavior and its conductivity characteristics by modifying the electrostatic control. For all these reasons, the experimental evaluation of the ESD protection robustness in FDSOI technology is essential.
Regarding the protection strategies, gated diodes constitute one of the most robust protections for ESD structures and network design. It has been shown that for RF application, a diode strategy protection based on gated diode is the best solution [4]. Due to node shrinking and technology modifications, the performances of gated diode tend to be degraded. Table 1 presents a benchmark of the intrinsic robustness It2 of gated diodes from different technologies. Study [3] [4] [5] [6]
Technology 250nm PDSOI 180nm bulk 130nm PDSOI 32nm PDSOI
It2 robustness (mA/um) 12.6 40 10-12.5 7.5-8.2
Table 1: Benchmark of ESD performance of gated diodes from different studies For comparing [3] and [4], ESD performance for HBM is converted in It2 with the relation: It2(mA/um) = VHBM(V/um) /1.5kΩ.
In this paper, we focus on TLP tests on 45nm node high-k/metal gate FDSOI devices in order to study the impact of the principal parameters of this technology: silicon film and BOX thickness. The comparison of gated diode performances in bulk and thin BOX FDSOI technology allows us to highlight the ESD robustness degradation. Our experimental results demonstrate that bulk/FDSOI co-integration, via SON (Silicon On Nothing) technology is a possible solution for improvement.
II-Bulk and FDSOI process description Our experimental FDSOI devices feature high-k dielectric (HfO2 2.5nm) and a midgap metal gate stack (ALD TiN 10nm) while the channel is left undoped. The gated diodes and MOSFETs have an ‘intrinsic’ (P-type, 1015 cm-3) body between anode and cathode as shown in Figure 1. The silicon film thickness scaling is more aggressive compared to Partially-Depleted (PDSOI) devices being reduced down to TSi ≈ 7nm to control short channel effect. BOX layer used is 150nm. Another 10nm-thick BOX is also probed to evaluate the effect of thermal dissipation on device robustness. Various widths and multi-finger structures were studied. Their designs and physics mechanisms are actually well known for bulk and PDSOI technologies [5]; this knowledge was used to study and manufacture gated diodes on FDSOI. The basic bulk device is constituted of a PN junction. In particular, a P+/PWELL/N+ architecture is used in order to increase the avalanche voltage. To avoid short circuits due to silicidation on the top of the N+/PWELL/P+ regions, a gate is used as a separation.
anode leakage current as a function of pulse voltage serves to detect failure. The failure criteria are the same for bulk, PDSOI and FDSOI devices: 50% variation of the leakage current. Bulk gated diodes without HKMG width Ron(Ω) It2 (mA/um) 10 x (2.5 um) 1.78 12 10 x ( 5 um) 1.08 11 10 x (10 um) 0.72 11 40 x (5 um) 0.32 10 Table 2: Robustness (breakdown current It2) and Resistance On (Ron) for bulk gated diodes with different number of fingers and widths (W= 10 x 2.5um; 10 x 5um; 10 x 10um; 40 x 5um).
Table 2 shows the main parameters measured for bulk gated diodes used as reference and ported on FDSOI technology.
III-Measurements in FDSOI Table 3 shows experimental data of FDSOI gated diodes for various device widths (number of fingers x unitary width). FDSOI gated diodes with HKMG width Ron(Ω) It2 (mA/um) 10 x (2.5 um) 16 2.8 10 x ( 5 um) 7.8 2.5 10 x (10 um) 4.2 2.4 40 x (5 um) 2.7 2.2 Table 3: Robustness (breakdown current It2) and On Resistance (Ron) for FDSOI gated diodes with different number of fingers and widths (W= 10x 2,5um; 10x 5um; 10x 10um; 40x 5um).
Figure 1: FDSOI gated diode cross section
As compared to bulk, the undoped channel in FDSOI leads to an intrinsic area instead of the WELL implant in the gated diode structure. The other main differences are the ultrathin body, the high-k/ metal gate stack (instead of polysilicon/SiO2 in bulk) and the BOX presence (Figure 1). All devices have been tested with TLP method [7]. This experiment consists in stressing the device with 100ns pulses on the anode, while keeping the gate and cathode grounded. Between pulses, the leakage current It2 is measured. The variation of the
Comparing the breakdown currents It2 measured in Table 3 and in bulk devices with the same geometry (Table 2), we observe that the FDSOI It2 is around four times lower. Conductivity (1/Ron) also drops with the porting from bulk to SOI. The leakage current evolution between two ESD-pulses on gated diode structures shows a soft breakdown phenomenon (before reaching the hard failure). As seen in Figure 2, when increasing the TLP pulse voltage and reaching a specific voltage value, the leakage current starts increasing exponentially. In a previous study on FDSOI devices, this method of electrical DC parameter analysis was also carried out with MOSFET [8].
100
they do in PDSOI or bulk devices (Figure 4 a,b). The current density is higher and the electric field increased.
test at V=0.4V first test at V=0.5V
le ak a g e Cu rre n t (n A)
second test two days later 10
BOX N+
PWELL
1
Exponential behavior
Gate Oxide
Gate
0.1
0.01 0
5 10 Test pulse voltage (V)
15
Figure 2: Leakage current as a function of the test pulse voltage for different polarizations of the FDSOI gated diode (5x5u).
In order to clarify this behaviour, the measurements were repeated two days later. The leakage current does not correspond to its original value; a change of the TLP I(V) characteristic is observed (Figure 3). The slope of the TLP I(V) characteristic is changed at high injection (Figure 3). However, the threshold voltage remains the same whatever the polarization applied (Figure 2).
BOX
INTRINSIC
Gate Oxide Gate
Figure 4 b: TCAD Simulation of FDSOI gated diode (TSi = 7 nm). The current is confined in the thin body.
0,16
I_TLP (A )
Figure 4 a: TCAD simulation of PDSOI Gated diode (TSi=70 nm): Observation of current density.
0,14
first test
0,12
second test two days later
In [5], due to the gate, it has been shown that at high injection level the bulk or PDSOI gated diode can be modeled as two conductances G1 and G2 (Figure 5). In ultrathin FDSOI, only the surface conductance (GFDSOI), with a poor conductivity, is possible. This explains why the conductivity drops from PDSOI to FDSOI.
0,1 0,08 0,06 0,04 0,02 0 0
1
2 V_TLP (V)
3
4
GFDSOI
Figure 3: I (V) TLP characteristic for same gated diode (W=5x5u), tested twice: firstly until 500 % leakage current increase but without hard failure, then two days later until hard failure.
To explain this phenomenon, TCAD Simulations [ISE Sentaurus 2008] of the ESD event on the device was performed with classical drift diffusion model and additional Dirichlet/Neumann boundary conditions. The results indicate that, due to the ultra-thin film and the presence of the BOX, the current lines are impeded to extend in the WELL as
G1 G2 Figure 5: Schematic representation of a gated diode at high injection level: a- FDSOI; b- bulk or PDSOI technologies.
IV-Impact of the BOX thickness As the buried oxide constitutes a thermal barrier during the ESD events, we evaluated the role of the BOX thickness in the TLP dynamic mode. Indeed, for 100ns-pulses, the heat diffusion length is around 170nm (~TSI+TBOX). So the BOX thickness is an important geometric factor for the heat dissipation. For experimental verification, we have compared thick BOX devices (150 nm) with much thinner BOX (10nm). The I(V) TLP characteristics obtained are shown on Figure 6. 0.5
I_TLP (A)
0.45 0.4
Box=150nm
0.35
Box=10nm
0.3 0.25 0.2 0.15 0.1 0.05 0 0
1
2
3
4
5
6
7
V_TLP (V)
Figure 6: I (V) TLP characteristic for gated diodes (W=10x5u), fabricated on two different BOX thicknesses: 150nm and 10nm.
We observe that the reduction of the BOX thickness improves the robustness of the device. The ratio It2(BOX=10nm)/It2(BOX=150nm) reveals a gain of 1.7. The benefit of thin BOX is confirmed by measurements on devices with different widths (W= 6um, 20um).
1250 1250 1150 1150
Temperature(K) Temperature(K)
At high voltage, near the gate, this higher electric field can also reach values that allow carrier injection and storage into the oxide. The charging of the gate dielectric with carriers induces a shift of the I(V) characteristic. This signature is named as ‘latent defect’.
1050 1050 950 950
thick thick BOX BOX (150nm) (150nm) thin thin BOX BOX (10nm) (10nm)
850 850 750 750 650 650 550 550 450 450 350 350 250 250 -0,2 -0.2
-0,15 -0.15
-0,1 -0.1
-0,05 -0.05
0 0
0,05 0.05
0,1 0.1
0,15 0.15
X(um) Y(um) Y(um)
Figure 7: Lattice temperature of thin BOX and thick BOX device versus vertical distance: TBOX(-0.15;0)&(-0.01;0), TSI(0;0.007), gate stack(0.007;0.08), and primary metal dielectric upon.
Another important effect is the conductivity drop, due to the temperature rise (significantly impacting the Ron of the device). Electro-thermal simulations have been carried out to monitor the lattice temperature profile in both thin and thick BOX FDSOI gated diode (Figure 7) and then to evaluate the impact of BOX thickness. In this Figure, the temperature under the thick BOX (350K) is very close to the temperature limit condition, 300K: the 100ns-TLP stress is a quasiadiabatic event and the 150nm BOX prevent heat dissipation in the bulk of the device. In thin BOX devices, the temperature underneath the BOX is around 450K: the heat generated by the hot spot is more easily evacuated thanks to the weaker thermal resistance of BOX. Hence, the maximum temperature in the active silicon is divided by 2 (650K instead of 1250K) between thin and thick BOX. As the temperature degrades the mobility[9], the higher the temperature is, the higher the conductivity drops. So, with a less degraded conductivity, the device can therefore tolerate higher current, improving its robustness. To sum up, the BOX thickness has two effects on device robustness: (i) limiting the thermal dissipation, it drops conductivity and increases self-heating, and (ii) it reduces the overall ESD robustness.
V- Hybrid co-integration of thinfilm and Bulk using SON process
Figure 8: Cross section of hybrid co-integration SOI/bulk devices with SON process.
The presence of BOX and ultra-thin Si film degrades the ESD robustness as seen previously. To avoid this problem, a possible solution could be the hybrid co-integration of bulk devices for ESD protection and FDSOI devices for others functions (Figure 8). In order to validate this concept, we used the SON (Silicon On Nothing) architecture which allows the integration of elements from both bulk and thin film devices on the same die [10]. The following are the technology steps for our device fabrication. On bulk-Si wafer, after the STI formation, a 50Å SiO2 and patterned to isolate bulk area for ESD devices. The FDSOI region is done with SON process [10]. SiGe and Si layers are successively grown by epitaxy. On Si layer, conventional CMOS process is performed. After removing the sacrificial SiGe layer, the tunnel is filled with oxide. Hybrid co-integration of Bulk and FDSOI areas is now available. On bulk, gated diodes were design for ESD applications. They are manufactured with the same design as the bulk devices from Table 1, but with a high-k/metal gate stack (with an equivalent oxide thickness EOT reduced by a factor 1.5). We compare the experimental results of Table 4 with those in Tables 2 and 3. SON bulk gated diodes with HKMG width Ron(Ω) It2 (mA/um) 10 x (2.5 um) 1.59 16.8 10 x ( 5 um) 1.14 14.3 10 x (10 um) 1.20 10.2 40 x (5 um) 0.42 8.3 Table 4: Robustness (breakdown current It2) and Resistance On (Ron) for SON gated diodes with different number of fingers and widths (W= 10 x 2.5um; 10 x 5um; 10 x 10um; 40 x 5um).
We notice that for small W, conductivity and robustness of bulk co-integrated diode (Table 4) are better than in bulk (Table 2). However, for higher W, the conductivity and robustness become lower. This degradation is smaller as compared to devices on SOI but it reveals the influence of the gate stacks on conductivity. The decrease of EOT reinforces the coupling of the gate with the channel, increasing the electric field in G1, the first conductance. Before reaching the critical electric field (carrier velocity saturation), the increase of electric field induces an improvement of effective mobility. Beyond the critical electric field, as the mobility is a decreasing function of Electric field, the increase of electric field induces a degradation of effective mobility. So, at low injection of current, the conductivity is improved and at high injection, it is degraded[5]. The key result appears when comparing the It2 robustness and Ron resistivity of gated diode on FDSOI from Table 3 with the results of co-integrated devices (Table 4). The co-integration of SOI/bulk devices yields much better results than conventional FDSOI and succeeds in manufacturing ESD robust protection. SON process enables to validate the hybrid co-integration strategy to protect advanced FDSOI devices with ESD gated diodes on the bulk part. An alternative solution for hybrid SOI/bulk co-integration is to start from a conventional SOI wafer, as proposed by Fenouillet et al [11].
VI-Conclusion For the first time, the ESD gated diode protection for a high-k/metal gate FDSOI 45nm node technology was evaluated. We have shown that the ultra-thin film degrades the ESD behavior and particularly the electrical conductivity compared to bulk and PDSOI devices. Furthermore, a thick BOX maintains the ESD-stress in quasi-adiabatic condition, also degrading the conductivity. A thinner BOX is beneficial. An original and effective hybrid SOI/bulk co-integration to overcome this degradation and address the ESD issues has been proposed and experimentally demonstrated.
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