Improved Lock-Time in All-Digital Phase-Locked Loops Due to Binary Search Acquisition Stefan Mendel
Christian Vogel
Christian Doppler Laboratory for Nonlinear Signal Processing Graz University of Technology, Austria email:
[email protected]
Signal and Information Processing Laboratory ETH Zurich, Switzerland email:
[email protected]
frequency detector
Abstract— A binary search algorithm for an improved settling time in phase-domain all-digital phase-locked loops (ADPLLs) is proposed. Therefore, an ADPLL structure for high-speed fractional-N frequency synthesis is adapted to extract the ratio between the reference and the output frequency in each reference cycle. A frequency detector compares the obtained ratio to the ideal value. The proposed control algorithm uses the frequency detector output to iteratively search for the desired tuning word. The binary search acquisition speeds-up the acquisition process significantly and suits digitally controlled oscillators with multiple varactor banks well. Behavioral simulations illustrate the proposed technique.
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I. I NTRODUCTION Even for high-speed high-performance wireless communication systems frequency synthesizers based on all-digital phase-locked loops (ADPLLs) are increasingly interesting [1]. An all-digital implementation replaces the voltage controlled oscillator (VCO) of analog or digital PLLs (DPLLs) by a digitally controlled oscillator (DCO), where a digital tuning word instead of a voltage controls the output frequency. For high performance applications an LC based oscillator with switchable varactors was proposed [1]. To overcome the contradictory requirements of a large bandwidth and a fine frequency resolution of the tuning curve with good linearity, the authors in [1] split the DCO into several banks. The ADPLL traverses through several modes corresponding to the varactor banks. Each mode decreases the supported bandwidth but refines the frequency resolution. In this way, a wide frequency range and a fine frequency resolution, which is mandatory for the stringent wireless standards, is achieved in [1]. Since an ADPLL is a feedback control system the inherent tradeoff between the transient behavior (lock time) and the steadystate performance (phase noise suppression), which depends on the loop bandwidth, is an arising problem. To be specific, the lock time depends on the initial frequency offset and the inverse of the bandwith. Several approaches have been proposed to overcome this limitation. One approach is to adjust the loop bandwidth according to the requirements, i.e., a large bandwidth during acquisition and a narrow bandwidth during tracking. In gear shifting [2] several modes are used to iteratively refine the bandwidth, while in adaptive control the bandwidth is changed according to the value of the phase error [3]. With gear shifting an acquisition time of less than 50 μs or 650 reference cycles @ 13 MHz was reported in [2]. The drawback of gear shifting is that the ideal time to shift gears is not known. Due to quantization effects within the DCO the tuning word will exhibit a periodic pattern (orbits), and changing the gear at an inappropriate time will slow down the acquisition in the next mode. Reference feedforward compensation [4] uses estimates of several DCO characteristics to predict the desired tuning word. By injecting the tuning word and by-passing the loop filter the initial frequency
978-1-4244-2182-4/08/$25.00 ©2008 IEEE.
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Fig. 1. A phase-domain ADPLL implementation for wireless communications systems [6] extended with binary search acquisition.
offset is significantly reduced. However, the proposed method depends on good estimates, and it is not shown how to extend the method to multiple varactor banks. A different approach is to sweep the entire tuning range in order to search for the best tuning word. In [5] an ADPLL based frequency synthesizer, running at 4 times the reference frequency, distinguishes between frequency and phase acquisition and, by using a modified binary search algorithm, achieves lock in 50 reference cycles. In this paper we adapt the idea of binary search acquisition from [5] to the phase-domain ADPLL fractional-N frequency synthesizer for wireless communications systems [1], [2], [6], [7]. Figure 1 illustrates the structure of [6] extended by binary search acquisition. II. B INARY S EARCH ACQUISITION A. Basic Idea In [8] a general system level model of a phase-domain ADPLL was introduced and is shown in Fig. 2. In the reference path the frequency fref and in the feedback path the frequency fv are converted to the phase signals ϕr and ϕv , respectively. The phase error ϕe , which is the difference between the phase signals, is filtered and normalized to produce the tuning word d at the input of the DCO. The feedback mechanism controls the phase error ϕe and in consequence the tuning word d, so that the output signal fv converges to the desired output frequency fvss = Nr · fref . The reference frequency-to-phase converter accumulates Nr at each rising edge of the reference clock, where Nr corresponds to the desired number of variable cycles within one reference cycle. Accordingly, in the feedback path Nv is accumulated. Note that Nv corresponds to the actual number of variable cycles during one
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reference cycle. If Nr and Nv are equal the slopes of both phase signales are equal and the phase error ϕe is constant. Consequently, for a type-I ADPLL, where the loop-filter is a proportional factor α, phase-lock is achieved. By contrast, if Nr < Nv the variable frequency fv and the tuning word d are too large and if Nr > Nv both fv and d are too small. Thus, we have a frequency detector similar to the one in [5] and can apply a binary search algorithm.
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The implementation of a phase-domain ADPLL for wireless communications systems [6] with the proposed extension is shown in Fig. 1. It slightly disagrees in the sampling frequency of the system compared to the model in Fig. 2. While in the model (Fig. 2) Nv is accumulated at rate fref , the variable phase ϕv is given by accumulating 1 at a rate of fv in [6]. The corresponding phase signals ϕv [i] and ϕr [n] are not synchronous, since n corresponds to the clock signal REF with frequency fref and i corresponds to the clock signal CKV with frequency fv . To compare these two phase signals a common clock domain has to be introduced. Oversampling the slow clock REF by the fast variable clock CKV results in the retimed reference clock CKR with time index m and an average frequency of fref . The retimed reference clock CKR is used as common clock in the system. Thus, we directly obtain ϕr [m] by accumulating Nr with each rising edge of CKR and ϕv [m] by sampling ϕv [i]. Due to retiming a quantization error ε ∈ (0, 1) is introduced and is given by the time between the rising edge of the REF clock and the rising edge of the CKV clock normalized by the variable period Tv = 1/fv (cf. Fig. 3). However, ε[m] can be measured with the aid of a timeto-digital converter (TDC) and added to the variable phase ϕr [m], so that the phase error accuracy exhibits fractional accuracy [7]. Since the update clock of the ADPLL CKR is the reference clock REF delayed to the next rising edge of the variable clock CKV , the number of CKV periods within one reference period CKR is an integer factor and is denoted as NCKV . The desired number of CKV periods within one CKR cycle, denoted as NCKR , differs from Nr due to the retiming mechanism. However, since ε[m] is known, we can calculate NCKR as NCKR [m] = Nr + ε[m] − ε[m − 1].
(1)
Figure 3 illustrates the relationship between Nr , NCKR [m], and NCKV [m] in lock for Nr = 1.5. The actual values of NCKR
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Relationship between Nr , NCKR [m], and NCKV [m].
and NCKV can be extracted from the phase signals ϕr and ϕv , respectively. Thus, the frequency detector signal used for the binary search acquisition is given by e[m] = ϕr [m] − ϕv [m] + ε[m] − ε[m − 1].
(2)
At the mth reference cycle the phase signal ϕr [m] increases by Nr , while the phase signal ϕv [m] accumulates NCKV . Furthermore, a zero-phase restart (similar to [2]) mechanism sets the reference phase equal to the variable phase, i.e., ϕr [m] = ϕv [m − 1] + Nr . Consequently, with (1) and a zero-phase restart (2) becomes e[m]=ϕr [m−1] + Nr − (ϕv [m−1] + NCKV ) + ε[m] − ε[m−1] =Nr − NCKV + ε[m] − ε[m−1] = NCKR − NCKV .
(3)
C. Control Mechanism The flowchart in Fig. 4 shows the control mechanism of the binary search acquisition process. The index j indicates the actual varactor bank going from j = 1 to jmax . In the first step Init Search the parameters for the search strategy are initialized for the actual bank. The minimal value of the tuning word is 0 and the maximal value is 2#bits(j) − 1. The step Update Tuning Word sets the tuning word to the middle value — max − min dj [m] = . (4) 2
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However, if e[m] > eres than NCKR > NCKV + eres and the variable frequency fv [m] is smaller than the desired frequency fvss . Therefore the step Increase Tuning Word sets the smallest possible tuning word min to dj [m−1]. On the other hand, if e[m] < −eres means NCKR < NCKV − eres and fv [m] > fvss . Therefore the step Decrease Tuning Word sets the largest possible tuning word max to dj [m − 1]. The search algorithm iterates as long as min < max − 1. In case that min equals max − 1 the tuning range [min, max] is found and the ideal tuning word lies in between. If the varactor bank is not the final one (j < jmax ) the acquisition process is refined by the next varactor bank. Assuming we can only increase the frequency in each bank, it must be ensured that the variable frequency before changing to a finer varactor bank is smaller than the desired frequency. Therefore the step Freeze Tuning Word freezes the tuning word of the jth varactor bank, i.e., dj = min, and the step Init Search restarts the binary search algorithm for the next varactor bank. As soon as the absolute value of the frequency detector error |e[n]| is smaller than the resolution of the TDC eres given in (5), the binary search method cannot refine the resolution anymore. In case the final bank has not been reached, i.e., j < jmax , we switch to the next varactor bank. In consequence of (6), it cannot be said whether fv [m] > fvss or fv [m] < fvss . Therefore the actual tuning word dj [m] is decreased before the binary search method is restarted, see step Decrease Tuning Word. Once the final bank and the final accuracy are reached, or the tuning range is found for the final bank, the binary search algorithm terminates. In any case, the ADPLL enters normal closed-loop operation and finishes the acquisition by eliminating the remaining frequency and phase offset. Since in closed loop operation the phase error is ϕe [m] = ϕr [m] − ϕv [m] + ε[m], whereas the frequency detector signal for binary search acquisition is e[m] = ϕr [m] − ϕv [m] + ε[m] − ε[m − 1], we have to compensate the deviation of −ε[m − 1], before entering normal operation. The easiest way is to adjust the reference phase to ϕr [m] = ϕr [m − 1] + Nr − ε[m − 1] as shown in the step Close Loop. By using binary search acquisition it is guaranteed that the freP quency resolution Δfres is acquired within j #bits(j) reference cycles.
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III. S IMULATIONS
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Fig. 4.
Control mechanism of a binary search acquisition.
Note that dj [m] is the tuning word of the jth varactor bank. Changing from one to another varactor bank freezes the tuning word of the preceding bank. To ensure a proper calculation of e[m], the step Zero-Phase Restart is performed. After the Operation step, which indicates the ADPLL operation of one reference cycle, the step Error computes e[m] according to (2). Note, that the accuracy of the TDC is limited, and thus a measurement error due to the TDC inaccuracy is introduced [7], which is eres = Δtres · fvss
(5)
where Δtres is the time resolution of the TDC. In consequence of (5) also the frequency resolution of the binary search acquisition is limited to (6) Δfres = eres · fref .
The simulated DCO consisted of three varactor banks, jmax = 3, with frequency resolutions of K = 2316 kHz, 461 kHz, and 23 kHz. Both tuning words of the first and second varactor bank d1 and d2 consisted of 5 bits, i.e., max = 31, and the final tuning word had 7 bits, i.e., max = 128. The free running frequency f0 of the DCO, i.e., the variable frequency of the DCO for the tuning word 0, was 2.4 GHz. The reference frequency fref was 13 MHz, and the desired frequency fvss was 2.413 GHz, which corresponds to a frequency hop of fref or a change of the frequency command word Nr by one. The TDC resolution Δtres was 20 ps; consequently the resolution of the error signal resulted in eres = 0.0483 (5), and the frequency resolution of the binary search algorithm was Δfres = 628 kHz according to (6). The oscillator phase noise was modeled as described in [9] with the values of the Bluetooth example. Figure 5 shows the tuning word d[m] over the reference cycles m, while Fig. 6 illustrates the corresponding output frequency fv over time. For better visualization of the binary search acquisition, the Xaxes among all banks and modes are differently scaled. Comparing the noise in Fig. 6 of the normal closed loop operation (right subplot)
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The entire binary search acquisition process has taken only 10 reference cycles to achieve a frequency resolution of Δfres = 628 kHz. In contrast, a type-I ADPLL with α = 2−8 and a single varactor bank requires 776 reference cycles to be within Δfres for an equal initial frequency offset of 13 MHz.
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IV. C ONCLUSION
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Through binary search acquisition the locking process of ADPLLs can be accelerated. Because of the quantization in the TDC the binary search algorithm has a certain frequency resolution. Once this frequency resolution is achieved the ADPLL switches to normal closed-loop operation. To ensure a good phase noise performance, a small bandwidth is required and consequently the final acquisition is slow. However, independent of the initial frequency offset the number of reference cycles to achieve the residual frequency offset equals the total number of bits used for all varactor banks. Therefore the method suits well for coarse frequency acquisition, e.g., process, voltage, and temperature compensation or frequency band acquisition. Little additional hardware is required, which is basically the control logic for the binary search algorithm. Compared to reference feed-forward compensation, binary search acquisition requires no calibration or estimation of the DCO gain or the DCO free running frequency. Furthermore, it can be applied to ADPLLs consisting of DCOs with two or more varactor banks. In gear shifting the mode switches are not fixed and consequently it is not ensured that the ideal tuning word for the previous bank has been found. That is, binary search acquisition is superior in coarse frequency acquisition, while gear shifting is advantageous for fine tuning.
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Fig. 5. Oscillator tuning word of the simulated ADPLL acquisition process using binary search acquisition and three varactor banks. Closed−Loop
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Fig. 6. Synthesized frequency fv of the simulated ADPLL acquisition process using binary search acquisition and three varactor banks.
to the noise of the binary search acquisition in the final bank, it appears that the noise has increased although the frequency resolution is refined. This is due to dithering [7], which allows the ADPLL to achieve a frequency resolution better than K. The noise shaping process increases the noise floor but moves noise energy to higher frequencies, i.e., to the out-of-band regions. According to (4) the acquisition process starts with d1 = 15 corresponding to a frequency fv [m] = 2.4 GHz + 15 · 2.316 MHz = 2.4347 GHz that is larger than fvss . Consequently, d1 [m] is decreased in the next step to d1 [m + 1] = 7 or fv [m + 1] = 2.4162 GHz. The synthesized frequency is still too large and d1 will be further reduced in the next step. The iterative search for the desired frequency continues until the final tuning range, i.e. the min = max − 1 is found. The acquisition is now refined using the second varactor bank and the tuning word of the first bank d1 [m] = min is frozen. The corresponding frequency fv [m] = 2.4 GHz + 5 · 2.316 MHz = 2.4116 GHz is the closest possible frequency, which is still smaller than the desired frequency with the resolution of 2316 kHz. The binary search algorithm is restarted for the second varactor bank with min = 0 and max = 31 and after three cycles, i.e., with d2 [m] = 3, the final accuracy of |e[m]| < eres = 0.0483 is reached and the tuning word d2 [m] − 1 (to ensure proper operation in the next bank) is frozen. After two reference cycles the binary search algorithm for the final varactor bank reaches the final frequency resolution of Δfres = 628 kHz. The tuning word for the final bank has settled to d3 [m] = 31 with a corresponding output frequency of fv [m] = 2.4116 GHz + 2 · 461 kHz + 31 · 23 kHz = 2.4132 GHz. However, the remaining frequency offset of 215 kHz must be obtained in normal closed-loop operation.
ACKNOWLEDGEMENT Support of our research by Infineon Technologies Austria AG is gratefully acknowledged. Furthermore, the authors would like to thank N. Da Dalt for fruitful discussions and suggestions for this paper. C. Vogel was supported by the Austrian Science Fund FWF’s Erwin Schroedinger Fellowship J2709-N20. R EFERENCES [1] R. B. Staszewski, C.-M. Hung, D. Leipold, and P. T. Balsara, “A first multigigahertz digitally controlled oscillator for wireless applications,” IEEE Transactions on Microwave Theory and Techniques, vol. 51, no. 11, pp. 2154–2164, Nov. 2003. [2] R. B. Staszewski and P. T. Balsara, “All-digital PLL with ultra fast settling,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 54, no. 2, pp. 181–185, Feb. 2007. [3] J. Lee and B. Kim, “A low-noise fast-lock phase-locked loop with adaptive bandwidth control,” IEEE Journal of Solid State Circuits, vol. 35, no. 8, p. 1137, August 2000. [4] W. Chaivipas and A. Matsuzawa, “Analysis and design of direct reference feed-forward compensation for fast-settling all-digital phase-locked loop,” IEICE Transactions on Electronics, vol. E90, no. 4, pp. 793–801, April 2007. [5] J. Dunning, G. Garcia, J. Lundberg, and E. Nuckolls, “An all-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors,” IEEE Journal of Solid-State Circuits, vol. 30, no. 4, pp. 412–422, April 1995. [6] R. B. Staszewski, C.-M. Hung, K. Maggio, J. Wallberg, D. Leipold, and P. T. Balsara, “All-digital phase-domain TX frequency synthesizer for bluetooth radios in 0.13 μm CMOS,” 2004. [7] R. B. Staszewski and P. T. Balsara, All-Digital Frequency Synthesizer in Deep-Submicron CMOS. John Wiley and Sons, 2006. [8] S. Mendel and C. Vogel, “A z-domain model and analysis of phasedomain all-digital phase-locked loops,” in Proceedings of the 25th IEEE Norchip Conference, 2007, Aalborg, Denmark, 19-20 Novemeber 2007. [9] R. B. Staszewski, C. Fernando, and P. T. Balsara, “Event-driven simulation and modeling of phase noise of an RF oscillator,” IEEE Transactions on Circuits and Systems—Part I: Fundamental Theory and Applications, vol. 52, no. 4, pp. 723–733, April 2005.
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