ALD metal-gate/high-κ gate stack for Si and Si0.7Ge0.3 surface-channel pMOSFETs D. Wu,* S. Persson, A.-C. Lindgren, G. Sjöblom,# P.-E. Hellström, J. Olsson,# S.-L. Zhang, M. Östling, E. Vainonen-Ahlgren,¤ E. Tois,¤ W.-M. Li¤ and M. Tuominen¤ KTH, Royal Institute of Technology, Department of Microelectronics and Information Technology, Electrum 229, SE-164 40 Kista, Sweden; *
[email protected] # Uppsala University, The Ångström Laboratory, P.O. Box 534, SE-751 21 Uppsala, Sweden ¤ ASM Microchemistry Ltd., FIN-02631 Espoo, Finland
Abstract ALD high-κ dielectrics and TiN metal-gate were successfully incorporated in both Si and Si0.7Ge0.3 surface-channel pMOSFETs. The high-κ gate dielectrics used included Al2O3 /HfAlOx /Al2O3, Al2O3 /HfO2 /Al2O3 and Al2O3. The Si transistors with Al2O3 /HfAlOx /Al2O3 showed a sub-threshold slope of 75 mV/dec. and a density of interface states of 3×1011 cm-2eV-1. No obvious degradation of the Si channel hole mobility was observed. The Si0.7Ge0.3 pMOSFETs with the various high-κ gate dielectrics demonstrated enhanced transconductance, drive current and channel hole mobility compared with the Si reference.
1. Introduction As the aggressive down-scaling in CMOS technology continues, the need for high-κ gate-dielectrics in place of the traditional SiO2 increases in order to provide extremely scaled equivalent oxide thickness (EOT) on the order of 1 nm for effective control of short channel effect (SCE) without remarkable increase of gate leakage current [1]. High-κ dielectric materials such as the oxides, silicates or aluminates of Hf and Zr are being intensively investigated [2-4]. Particularly, HfO2 has shown good properties with a dielectric constant up to 20, reasonable barrier height (1.5 eV) towards both conduction band minimum and valence band maximum of Si, and good thermal stability with Si. Recently, manufacturable CMOS with HfO2-Al2O3 dielectrics has been demonstrated [5]. However, transistors with high-κ gate dielectrics often suffer from degradation of carrier mobility [6-8], which is associated with a high density of oxide charges and/or interface traps. Furthermore, smaller transistors will be operated with lower effective carrier mobility under higher electrical fields, as a result of a slower down-scaling of the supply voltages than the rate of miniaturization of the physical dimensions including EOT [1]. In the present work, the various highκ gate dielectrics as well as TiN metal-gate are deposited by means of atomic layer chemical vapor deposition
(ALD). In addition to Si channel pMOSFETs, strained Si0.7Ge0.3 surface-channel devices are also fabricated in order to enhance the channel hole mobility. Comparisons between the Si and Si0.7Ge0.3 pMOSFETs as well as among the Si0.7Ge0.3 devices with various high-κ dielectrics are made.
2. Device fabrication The devices were fabricated on p-type Si (100) substrates using a conventional CMOS process. The nwell was uniformly doped to 3×1017 cm-3. After the formation of LOCOS isolation, channel implantation was performed to form a retrograde channel profile with a surface concentration of 4×1018 cm-3. A 10-nm thick undoped strained Si0.7Ge0.3 layer and its underlying Si buffer were selectively grown to form the Si0.7Ge0.3 surface channel, using reduced-pressure CVD. A 20-nm thick undoped Si layer was grown for the Si channel devices. The thickness and composition for the epitaxial layers are nominal values obtained on blanket calibration wafers. Prior to the deposition of the metal-gate/high-κ stack, the wafers were cleaned in a dilute HF solution (0.5 % in H2O) and rinsed with de-ionized water. Al2O3/HfAlOx/Al2O3 (0.5/4/0.5 nm) laminate film was deposited on Si devices in an ALCVDTM reactor using Al(CH3)3, HfCl4 and H2O at 300 oC. For the Si0.7Ge0.3 pMOSFETs, three kinds of 5-nm thick high-κ dielectrics were deposited: Al2O3/HfO2/Al2O3 (0.5/4/0.5 nm), Al2O3 (5 nm) and Al2O3/HfAlOx/Al2O3 (0.5/4/0.5 nm). For the TiN deposition, TiCl4 and NH3 were used. The stoichiometry of the TiN layer was 1:1. After gate patterning, TiN metal gate was dry-etched by using a gas chemistry of BCl3 and Cl2. After extension and deep source/drain implantations, the samples were annealed at 930 oC in N2 for 10 s. Post-metallization sintering was performed in forming gas at 400 oC for 30 min. Finally, the samples were annealed in H2O vapor at 300 oC for two hours. The schematic cross-section of a fabricated Si0.7Ge0.3 surface-channel pMOSFET is shown in Fig. 1.
TiN gate p+
p+ Si buffer
Si0.7Ge0.3
n-well
high-κ
Figure 1. Schematic cross-section of the gatechannel region of a fabricated Si0.7Ge0.3 surfacechannel pMOSFET.
3. Results and discussion The C-V data for the various high-κ dielectrics of Si and Si0.7Ge0.3 pMOSFETs are shown in Fig. 2. An EOT of 3.4, 2.8 and 2.3 nm was extracted for the Si0.7Ge0.3 pMOSFETs with Al2O3, Al2O3/HfAlOx/Al2O3 and Al2O3/HfO2/Al2O3, respectively, which indicates the presence of a ∼1.3-nm thick interfacial SiO2 using εr=10 for Al2O3 and 20 for HfO2 [9]. The interfacial SiO2 was likely introduced prior to the ALCVDTM processing. The Si pMOSFET showed a similar EOT compared to the Si0.7Ge0.3 using the same high-κ dielectric. Assuming that the interfacial SiO2 layer was also present for both Si and Si0.7Ge0.3 channel pMOSFETs with the Al2O3/HfAlOx/Al2O3 gate dielectric, εr=14 was obtained for the HfAlOx. The kinks observed on the C-V curves of the Si0.7Ge0.3 devices in the accumulation region around VG=1 V are likely to result from slow interface states close to the conduction band of the surface Si0.7Ge0.3 layer [10]. The strained Si0.7Ge0.3 layer has a bandgap of 0.92 eV, smaller than that for Si (1.1 eV). Hence with the same Al2O3/HfAlOx/Al2O3, both Si0.7Ge0.3 and Si devices enter the accumulation at a similar gate voltage, while the gate voltage at which inversion occurs is considerably more negative for the Si device resulting in a larger voltage interval on the C-V curve (Fig. 2). 7
W/L = 50/10 µm
Capacitance (pF)
6
100 KHz
5 4 HfAlO /Si
3
x
HfO /SiGe 2
Al O /SiGe
2 1
2
3
HfAlO /SiGe x
-2
-1 0 1 2 Gate Votage (V) Figure 2. C-V characteristics for Si and Si0.7Ge0.3 pMOSFETs with different TiN/high-κ gate stacks.
The work function of the ALD TiN gate was determined experimentally as 5.0 eV, on a separate wafer with MOS capacitors of thermally grown SiO2 to different thicknesses. As evident in Fig. 2, no gate depletion effect was found due to the use of the TiN metal-gate for both Si0.7Ge0.3 and Si channel devices. The extracted threshold voltages of the fabricated Si0.7Ge0.3 and Si transistors with different gate lengths are shown in Fig. 3. The differences in threshold voltage among the Si transistors and the Si0.7Ge0.3 transistors with both Al2O3/HfO2/Al2O3 and Al2O3/HfAlOx/Al2O3 can be partly explained by the valence band offset between the Si and strained Si0.7Ge0.3 layers and by the different EOT values obtained for the high-κ dielectrics. The threshold voltages of the Si0.7Ge0.3 transistors with the Al2O3, however, are considerably higher than the simulated ideal ones, indicating that there could be large amounts of negative fixed charges in the Al2O3 layer. The Al2O3 dielectric also showed a substantially higher density of slow traps than the two-sandwiched dielectrics [11], according to low-frequency noise measurements. The origin of the fixed charges and/or slow states in the Al2O3 is being investigated. The density of interface states for the Si transistor was measured to be 3×1011 cm-2eV-1, using charge-pumping method. The density of interface states for the Si0.7Ge0.3 transistors with the various high-κ dielectrics, however, ranged from 1.6×1012 to 1.8×1012 cm-2eV-1. The density of gate leakage current for the Si0.7Ge0.3 and Si transistors is shown in Fig. 4. Though the leakage currents for the Si0.7Ge0.3 devices with the various high-κ dielectrics is generally higher than that for the Si device, which is likely caused by the higher density of interface states, they are still comparable to that of a Si transistor with SiO2 of the same EOT [12]. The IDS–VGS, gM–VGS and IDS–VDS characteristics for the Si and Si0.7Ge0.3 transistors with LG=10 µm and WG=50 µm are shown in Fig. 5, Fig. 6, and Fig. 7, respectively. The Si transistor displays a good subthreshold behavior with a sub-threshold slope of 75 mV/dec. (Fig. 5). The Si0.7Ge0.3 transistor with the same high-κ dielectric Al2O3/HfAlOx/Al2O3, however, shows a higher sub-threshold slope, 110 mV/dec., due to the higher density of interface states. The difference in subthreshold slope for the Si0.7Ge0.3 transistors, 135 mV/dec. for Al2O3 and 105 mV/dec. for Al2O3/HfO2/Al2O3, is mainly due to the EOT difference since the density of interface states is similar for the devices. Improvements in both peak transconductance (Fig. 6) and drive current (Fig. 7) up to 30 % are found for the Si0.7Ge0.3 transistor with Al2O3/HfAlOx/Al2O3, compared to the Si transistor with the same high-κ stack. As expected, the Si0.7Ge0.3 transistor with Al2O3/HfO2/Al2O3 shows the highest transconductance and drive current since its EOT is the smallest. The Si0.7Ge0.3 transistor with Al2O3 still shows higher transconductance and drive current than the Si transistor, despite of its larger EOT value.
HfAlO /Si x
0.6
HfO /SiGe 2
0.4
Al O /SiGe
0.2
HfAlO /SiGe
2
3
x
0 -0.2 -0.4 -0.6
1 10 Effective Gate Length (µm) Figure 3. Threshold voltage vs. effective gate length for Si and Si0.7Ge0.3 pMOSFETs with different TiN/high-κ gate stacks.
10
-5
10
-6
10
-7
10
-8
2
10
x
HfO /SiGe 2
Al O /SiGe 2
3
HfAlO /SiGe x
1.2
-9
-2 -1.5 -1 -0.5 0 0.5 1 1.5 2 Gate Voltage (V) Figure 4. Gate leakage current density vs. gate voltage for Si and Si0.7Ge0.3 pMOSFETs with different TiN/high-κ gate stacks.
Drain Current, I
110 mv/dec.
-1 G
10
-3
10
-5
10
-9
Al O /SiGe 2
3
HfAlO /SiGe x
L = 10 µm
0.4
G
0.2 0 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 Gate Voltage, V (V)
10
x
2
Al O /SiGe 2
2
1.5
GS
HfAlO /Si HfO /SiGe
-7
HfO /SiGe
Figure 6. gM–VGS for Si and Si0.7Ge0.3 pMOSFETs of LG=10 µm with different TiN/high-κ gate stacks.
75 mv/dec.
10
x
D
0.6
135 mv/dec.
L = 10 µm
HfAlO /Si
V = -0.1 V
0.8
105 mv/dec.
3
HfAlO SiGe x
-2.5 -2 -1.5 -1 -0.5 0 0.5 Gate Voltage, V (V)
1
GS
Figure 5. IDS–VGS for Si and Si0.7Ge0.3 pMOSFETs LG=10 µm with different TiN/high-κ gate stacks. The Si and Si0.7Ge0.3 transistors of LG=0.6 µm were also found to be well-performing, similarly to their counterparts of LG=10 µm, though the threshold voltages differed (Fig. 3). In Fig. 8, the IDS–VGS characteristics for such short-channel devices are shown. No degradation of the sub-threshold slope can be found for the transistors. Similar improvements in transconductance and drive
(µA/µm)
10
DS
(µA/µm)
10
1
1
DS
Gate Leakage Current (A/cm )
HfAlO /Si
M
-4
Transconductance, g (µS/µm)
10
current were also found for the Si0.7Ge0.3 transistors compared to the Si ones. The channel hole mobility was evaluated for all transistors using the standard split C-V technique. The results are shown in Fig. 9, along with the universal mobility curve for holes in Si as reference. No obvious mobility degradation is found for the Si transistor since its effective mobility results coincide with the universal curve. This observation implies the great potential of replacing the traditional poly-Si/SiO2 gate stack with an ALD metal-gate/high-κ gate stack. For the Si0.7Ge0.3 devices with the various high-κ dielectrics, the mobility is consistently higher than the universal curve at Eeff above 0.65 MV/cm. The Si0.7Ge0.3 transistors with either Al2O3/HfAlOx/Al2O3 or Al2O3/HfO2/Al2O3 show an enhancement in hole mobility amounting to 35% at Eeff=0.9 MV/cm, as compared to the Si reference or the universal mobility data. At low effective electric field, however, lowered mobility values are observed for the Si0.7Ge0.3 transistors. In addition, the decrease in mobility towards low effective field does not follow the usual sharp roll-off due to Coulomb scattering by the ionised charge in the channel. This behavior is attributed to the presence of a high density of interface states, which makes the extraction of carrier mobility by the standard
Drain Current, I
Threshold Voltage (V)
0.8
8
HfAlO /Si V
GT
x
= -1.4 V
HfO /SiGe 2
Al O /SiGe 2
x
L = 10 µm
4 2 0 -2
3
HfAlO /SiGe
6
G
VGT = -0.6 V
-1.5 -1 -0.5 Drain Voltage, V
DS
0 (V)
0.5
Figure 7. IDS–VDS at different gate overdrives for Si and Si0.7Ge0.3 pMOSFETs of LG=10 µm with different TiN/high-κ gate stacks.
Drain Current, I
DS
(µA/µm)
10
100 mv/dec. 127 mv/dec.
1
10
-1
10
-3
10
-5
V = -0.1 V D
L = 0.6 µm G
75 mv/dec. HfAlO /Si x
HfO /SiGe 2
10
-7
10
-9
Al O /SiGe 2
110 mv/dec.
3
HfAlO /SiGe x
-2.5 -2 -1.5 -1 -0.5 0 0.5 Gate Voltage, V (V)
1
GS
Figure 8. IDS–VGS for Si and Si0.7Ge0.3 pMOSFETs of LG=0.6 µm with different TiN/high-κ gate stacks.
2
Hole Mobility (cm /V*sec)
100 90
5. Acknowledgements J. Seger, J. Westlinder and M. von Haartman are acknowledged for assistance in device processing and fruitful discussions. This work was financially supported by the Swedish Foundation for Strategic Research (SSF) through the ‘High-Frequency Silicon’ program and by EU IST-1999-11603 project SIGMOS.
References Universal
80 70 60
gate dielectrics demonstrated enhanced transconductance, drive current and channel hole mobility, as compared with the Si reference. The Si0.7Ge0.3 transistors with Al2O3/HfO2/Al2O3 exhibited the greatest improvements in transconductance and drive current without further degradation of the channel hole mobility, compared with the Si0.7Ge0.3 devices with Al2O3/HfAlOx/Al2O3 or Al2O3.
HfAlO /Si x
50
HfO /SiGe
40
Al O /SiGe
2
2
3
HfAlO /SiGe x
30 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Effective Electric Field, E (MV/cm) eff
Figure 9. Channel hole mobility vs. Eeff for Si and Si0.7Ge0.3 pMOSFETs with different TiN/high-κ gate stacks, with reference to the universal mobility curve for holes in Si. split C-V technique unreliable at low effective electric field [12]. Accurate mobility extraction requires correct interpretation of the C-V measurement results [13]. Despite the apparent mobility degradation at low electric field, it is clear that the enhanced channel hole mobility in the Si0.7Ge0.3 channel is responsible for the improved transconductance and drive-current for the Si0.7Ge0.3 transistors discussed above.
4. Conclusion A successful integration of ALD high-κ dielectric and TiN metal-gate into a standard CMOS process for fabrication of both Si and Si0.7Ge0.3 surface-channel pMOSFETs has been demonstrated. The Si transistor with Al2O3/HfAlOx/Al2O3 showed fairly low subthreshold slope of 75 mV/dec. and low density of interface states of 3×1011 cm-2eV-1. No obvious degradation of the channel hole mobility was observed when the Al2O3/HfAlOx/Al2O3 gate dielectric was used in the Si transistor. Although a higher density of interface states and a larger sub-threshold slope were observed, the Si0.7Ge0.3 pMOSFETs with various high-κ
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