2015 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT)
Improved Optimum Bit Loading for Power Line Communication Syama Sasikumar' ,
s. Narayanan2
'.2Dept. of Electronics & Communication Engineering, Mar Baselios College of Engineering and Technology, Thiruvananthapuram, India '
[email protected],
[email protected] Abstract-Orthogonal Frequency Division Multiplexing (OFDM) power line communication (PLC) systems perform better with the implementation of efficient bit loading techniques. In this paper, improvement in raw bit rates for PLC is obtained by using the combination of greedy incremental bit loading algorithm and the concept ofmultiwire PLC with multiple electrical connections between transmitter and receiver. Comparison of raw bit rates for two wire and multiwire PLC systems are reported and analyzed. For transmit power of -55dBmlHz, raw bit rate of 180 Mbps is obtained for a two wire PLC system wheras a higher raw bit rate of around 230 Mbps is obtained for multiwire PLC system. Keywords-power line communication (PLC); orthogonal jrequency division muliplexing (OFDM); bit loading; optimisation; nmltiwire . I.
INTRODUCTION
Power line communication (PLC) is a technology which is used to provide data communication through power Iines, which are conventionally used for providing electricity. PLC has gained interest due to very significant advantages such as ubiquity, existing infrastructure and cost effectiveness. PLC is currently used for a wide variety of applications such as smart grid, horne automation and narrowband and broadband communication. Despite the above mentioned advantages, PLC has many disadvantages which include changing topologies, continuously varying load conditions, transients, multipath issues and different types of noises. Besides, since PLC was not designed for data communication it acts as a very harsh medium for the same [1]. The several disadvantages have triggered lot of research in the area of PLC. Many modulation techniques from Binary Phase Shift Keying (BPSK), Frequency Shift Keying (FSK), Phase Shift Keying (PSK), Gaussian Minimum Shift Keying (GMSK), Spread Spectrum, Spread Frequency Shift Keying (S-FSK) has been applied to mitigate these disadvantages. Recently, Orthogonal frequency division multiplexing (OFDM) has emerged as a suitable communication technique
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for PLC owing to its robustness to multipath, ability to resist interference and tlexibility of design. Research is currently going on in several areas of OFDM PLC in order to further improve the performance. One of the important areas of research is bit loading in OFDM [2]. Bit loading techniques are used to improve the performance of OFDM systems. Conventional techniques load equal number of bits to different subchannels irrespective of the varying conditions. Bit loading techniques try to allocate different number of bits to different subchannels after considering the subchannel conditions. Subchannels with higher attenuation are allocated less number of bits while those with low attenuation are allocated more number of bits. In such a manner, bit rates ofthe system can be improved. Several works in literature deal with bit loading in OFDM systems. Simple bit loading algorithrns for OFDM systems is discussed in [3]. Waterfilling alogorithm is conventionally used for bit loading and power allocation as done in [4]. Algorithrns having greedy nature provide better results compared to waterfilling algorithrn. Greedy type algorithrns look for the best immediate solution and thus the fmal result would be optimum. Greedy type bit loading in time varying PLC system is the subject of study in [5] . In our own previous work [6], bit loading was performed in a generalized PLC system using greedy type technique and the effect of system parameters on the result of bit loading was analyzed. This paper focuses on the improvement on result of bit loading from [6] for an OFDM PLC system. The advantages of the concept of multiwire PLC with multiple paths for transmission between transmitter and receiver is utilized for the purpose. Remaining portion of this paper is organized as folIows. Section 11 gives the bit loading problem addressed. Section III deals with abrief introduction to multiwire PLC. Section IV discusses ch ann el model used for this work. Section V presents and discusses the simulation results. Finally, Section VI concludes the paper.
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2015 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT)
11.
PROBLEM DEFINITION
The bit loading problem addressed is as shown below: maXlllllse : (1)
channel generator for indoor PLC systems is proposed in [9]. It models MIMO PLC channel as the superposition of correlated SISO channels. A flexible FPGA (Field programmable gate array) based broadband channel emulator for MIMO PLC is presented in [10]. IV.
subject to constraint : N
IPj
