Improving Yield Through the Application of Process Window OPC

Improving Yield Through the Application of Process Window OPC Jaione Tirapu Azpiroz, Azalia Krasnoperova, Shahab Siddiqui, Kenneth Settlemyer, Ioana Graur, Ian Stobert, James M. Oberschmidt IBM Microelectronics, Hopewell Junction, NY 12533 ABSTRACT As the industry progresses toward more challenging patterning nodes with tighter error budgets and weaker process windows, it is becoming clear that current single process condition Optical Proximity Corrections (OPC) as well as OPC verification methods such as Optical Rules Checking (ORC) performed at a single process point fail to provide robust solutions through process. Moreover, these techniques can potentially miss catastrophic failures that will negatively impact yield while surely failing to capitalize on every chance to enhance process window. Process-aware OPC and verification algorithms have been developed [1,2] that minimize process variability to enhance yield and assess process robustness, respectively. In this paper we demonstrate the importance of process aware OPC and ORC tools to enable first time right manufacturing solutions, even for technology nodes prior to 45nm such as a 65nm contact level, by identifying critical spots on the layout that became significant yield detractors on the chip but nominal ORC could not catch. Similarly, we will demonstrate the successful application of a process window OPC (PWOPC) algorithm capable of recognizing and correcting for process window systematic variations that threaten the overall RET performance, while maintaining printed contours within the minimum overlay tolerances. Direct comparison of wafer results are presented for two 65nm CA masks, one where conventional nominal OPC was applied and a second one processed with PWOPC. Thorough wafer results will show how our process aware OPC algorithm was able to address and successfully strengthen the lithography performance of those areas in the layout previously identified by PWORC as sensitive to process variations, as well as of isolated and semi-isolated features, for an overall significant yield enhancement. Keywords: PWOPC, Yield, Contact, 65nm

1. INTRODUCTION Some rudimentary form of optical proximity correction was already in use a couple of thousand of years ago by Roman inscriptions [3]. However, it was not until the early 80s that the first automated application of mask shapes precompensation for systematic effects of frequency limited diffraction was proposed on the framework of photographic image reproduction [4]. Rules based optical proximity corrections remained predominant in the following years [5], still limited to small areas up to the 90nm technology node in the early 2000s. In the mid 90s, however, a new class of algorithms were developed that allowed fast and iterative pre-compensation of an entire chip, through the application of lithographic process models to compute the expected resist printed contours at each sample point of a sparsely sampled layout as illustrated in figure 1(a). These methods, known as model based OPC [6-8], enabled the further lithographic scaling and were finally introduced in production with several critical levels of the 65nm node. Model based OPC methods rely on mathematical models of the lithography system that typically consists of optical models covering the exposure of the mask, diffraction and imaging inside the resist medium, and empirical models of the resist development process often calibrated to hundreds measurements of resist linewidth on wafer. Hence the label optical proximity correction remains today as a legacy of the original purpose of these algorithms, but they are used today to compensate for more than just the diffraction-limited optics. OPC algorithms use very sophisticated models that enable pre-compensation for other systematic optics induced effects (eg. lens polarization response), resist development and more recently also for the process of etching. For efficiency of the algorithms, the optical models and hence the original model-based OPC algorithms assume a single pair of focus and dose values, often associated with the plane of best focus and the anchor dose, determined empirically during process development to print a specific feature of the layout on target. The resulting pre-compensation of the mask shapes is then performed to guarantee the fidelity of the pattern transferred to wafer at the nominal process conditions of dose and focus. Prior characterization and optimization of the resolution enhancement technique (RET) and process conditions for exposure should then guarantee enough degree of fidelity through the expected window of dose and defocus variations. Algorithms such as Mentor Graphics

Optical Microlithography XXII, edited by Harry J. Levinson, Mircea V. Dusa, Proc. of SPIE Vol. 7274, 727411 · © 2009 SPIE · CCC code: 0277-786X/09/$18 · doi: 10.1117/12.811868

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Optical Rules Checking (ORC) were developed in parallel to perform a more densely sampled evaluation as sketched in figure 1(b) to further verify that printed contours fall within tolerances at nominal conditions.

OPC at Nominal

Verification at Nominal

Process Variability Band

Failure

(a)

(b)

(c)

Tolerance Bands

Fig. 1. (a) Model based Optical Proximity Corrections apply iterative pre-compensation to the mask shapes through the modeling and simulation of resist printed contours at each sample point of a sparsely sampled layout. (b) Post-OPC verification at nominal conditions performs a more densely sample test that printed contours fall within tolerances. (c) Simulation of the printed contours at different process conditions form the so-called process variability bands (pvbands), which help disposition areas of weak process window.

1.1 Process Window Aware Computational Lithography Tools Nominal OPC and nominal verification methods (nominal ORC) operate to minimize the difference between the simulated resist contours and the designer target, often described as the edge placement error (EPE), at nominal conditions of dose and focus. Soon after model based OPC became an essential step in subwavelength optical lithography, it has also become clear that post-OPC verification at nominal conditions is insufficient to identify areas of unacceptable deviation of resist contours from the target due to process variations. Nominal verification often also fails to identify potential areas of severe yield loss due to large feature size variations [2, 9-11]. An alternative approach to nominal verification has become common, which is capable of reconciling the extraction of contour variability across the lithographic process window with acceptable tolerances in the design [2]. The process window refers to the maximum range of dose and defocus errors in which the critical dimension (CD) value of a printed feature on wafer remains within a predetermined tolerance range. By performing multiple simulations with varying pairs of dose and defocus values, typically on the borders of the lithography process window, and extracting the most outer and most inner contours, a process variability band (PVband) is formed. This PVband represents the expected effect of process variations on the shape of the device resist contours. A separate algorithm hat specifies the allowed tolerances on these PVbands for different sections of the design as provided by the designer’s intent form the tolerance bands (TB). The width of each band governs the range of deviation from the design target that is acceptable to prevent critically altering the behavior and performance of the designed circuitry. Hence they provide a proper intersection between design specs and process variability and allow to disposition areas of weak process window. This intersection is sketched in figure 1(c) for a generic 2-dimensional line end feature. These contour simulations across different process conditions within the expected window of the lithography process also provide more accurate extraction of the electrical device timing [10]. Nominal OPC can guarantee minimum EPE values at nominal conditions, but the actual expected position of the edge contour is becoming increasingly sensitive to process variability, negatively impacting the device timing performance and potentially reducing the pattern process window. Process Window OPC (PWOPC) is an extension of nominal model based OPC that provides proper mask shape pre-compensation optimized for process variability and yield [1]. Any PWOPC algorithm should place a mask edge in such a way that the expected pattern contour placement, averaged across all process window, falls at the design target, regardless of where the contour prints at nominal. In other words, PWOPC

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aims to minimizing the mean EPE across the process window rather than the nominal EPE. As a result PWOPC will center each feature pvband about the design target and inside the tolerance bands, hence reducing the potential for failure at defocus conditions and overall increasing the robustness of the feature process window. In this paper we demonstrate the value of process window aware ORC and OPC on actual production chips at technology nodes as early as 65nm. Low levels of wafer yield were observed on a 65nm contact level that was negatively impacted critical chip production. The designs had successfully passed both nominal OPC and ORC procedures and yet they suffered from a high open failure rate. Process window ORC verification identified several areas of isolated and semi-isolated contacts with excessive variation at defocus conditions which were also verified on resist and post-etch wafers. A model based PWOPC algorithm was customized to address the weak process window of these contacts while maintaining their pvbands within specs. The algorithm also included checks and constraints to prevent overlay violations. After processing one of the designs with PWOPC and passing the subsequent PWORC, a new mask was built. Wafers were exposed with both masks at exactly the same illumination and process conditions, and resist critical dimension (CD) measurements across dose and focus demonstrated improved lithographic performance on those wafers exposed with the PWOPC mask. Moreover, wafer final test demonstrated an average yield improvement of 8 points of the PWOPC mask against the fab baseline for the same chip using the nominal OPC mask.

2. PROCESS WINDOW ORC AND YIELD DETRACTORS In subwavelength lithography, the importance of process window verification methods such as the pvbands described above, to locate weak areas to process variations, have been recognized for technology nodes as early as 65nm. Integration into production flows, however, requires longer acceptance and development times. Nominal OPC and ORC had been successfully applied to 65nm contact level that was later showing alarming rates of open failures as the example illustrated in figure 2, and unusually low yield numbers as a consequence. The RET (resolution enhancement technique) for this process consisted of conventional illumination with a 0.85NA dry lithography, attenuated phase shifting mask and no sub-resolution assist features. Selectively biasing of isolated contacts or the optimization of a whole new resolution enhancement technique could have helped enhance the process window robustness. Instead, a combination of PWORC, used to precisely identify the cause of the yield loss, and of PWOPC, used to finely apply model based compensation on those weak contacts, enough to enhance their process window while maintaining the printed contours within tolerances, was applied to this level, maintaining the RET and process unchanged.

MVRPV

SC326 000.OISO)

O5WSG3OZ6.00-OISOFO S52

&*V O,.m x15SE 27

Fig. 2. Cross section example of open failure on a 65nm contact level.

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J MURPHY

2.1 Nominal ORC vs Process Window ORC The 65nm contact level suffered from low levels of wafer yield despite having passed all ORC checks at nominal conditions of dose and focus. Sensitivity to 3sigma mask error was small. Hence, ORC verification at enough combination of dose and defocus error were carried out to cover enough process window area. The checks used the process optical model of a conventional unpolarized illumination of 0.74 sigma and 0.85NA dry lithography anchored to a 225nm pitch, and a Calibre VT-5 resist model calibrated to wafer linewidth measurements through the conventional minimization of the Root Mean Squared (RMS) error [12]. In particular, the simulations were performed with Calibre OPCpro from Mentor Graphics and employed a range of +/-100nm defocus and +/-4.5% dose variations and used the same resist model for a combination of optical models built at varying focus positions. These PWORC simulations unveiled 11 unique sites (on two different chip designs) as critically failing out of nominal conditions. Figure 3 displays 4 of these critical spots, with the arrow pointing at the contact with the critically weak process window, numbered from 1 to 4. Also illustrated in figure 3 is the underlying polysilicon layer (PC). All the PWORC results, those displayed and not displayed, corresponded to isolated and semi-isolated contacts with a tendency to become small beyond specs at defocus conditions, thus confirming the hypothesis that the weak process window performance of these contacts caused the high incidence of open contacts across the chip. The highlighted sites represented hundreds of repetitions across both chips.

Weak-CA 1

Weak-CA 2

Weak-CA 3

Weak-CA 4

PC

CA Fig. 3. Several unique sites flagged by PWORC as critically failing at out of nominal conditions. Contact layer is in red color with a cyon arrow pointing at the flagged contact with the critically weak process window, and in orange is the underlying polysilicon layer (PC).

2.2 Wafer Verification Wafer verification of the resist critical dimension (CD) was performed for the areas high-lighted as weak by PWORC simulations. Resist linewidth data measured with an Applied Materials Scanning Electron Microscrope (nanoSEM) across several defocus and exposure dose values was compared against the predicted CD as simulated by our models. The corresponding measured and simulated resist CD values are plotted in figure 4(a) and (b) for weak areas number 3 and 4 of figure 3. The model predictions as compared against the measured data appear accurate within a range of ±50nm, but tend to predict even larger contact CD than measured when extending to a ±100nm defocus range. Nevertheless, the wafer CD data appear to confirm these contacts as becoming increasingly small at out of focus conditions. Further wafer verification was provided by post etch data of these same highlighted areas. In particular, a random chip lot was stopped and the PWORC highlighted sites were measured. It was observed that the post-etch CD on all these weak areas were consistently below specs, with two of the sites being significantly problematic. The measured difference in nm between the post-etch CD value and the target spec, defined as ΔCD = CDMeasured - CDTarget, for 6 of the PWORC highlighted contacts is collected in table 1, with errors as high as -6nm and -12.7nm for two of the contacts. SEM images of these two contacts are displayed in figures 5(a) and 5(b), respectively. Wafer verification of resist CD as well as post-etch CD confirmed the conclusions derived from the PWORC analysis, that is, isolated and semi-isolated contacts become unacceptably small beyond tolerances at defocus conditions and critically contributing to the low yield levels observed at 65nm CA level.

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Sim 5% Sim -5%

Delta CD(nm)

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(a)

Fig. 4 Resist linewidth data measured with an Applied Materials Scanning Electron Microscrope (nanoSEM) across dose and focus and plotted against the simulated CD for (a) weak contact 3 of table 1, and (b) weak contact 4 of table 1.

Weak-CA # Post-Etch ΔCD (nm) 1 -2.7 2 -2.5 3 -6 4 -12.7 5 -1.3 6 -2.5

Table. 1. Difference between the post-etch CD value and the target spec, ΔCD = CDMeasured - CDTarget, for 6 of the PWORC highlighted.

Weak-CA 4

0000 00

000 000 0 00 0 0000 0000

0000000

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00000000. O0000O0.oO 0O000Q..O0 00o000..

88

ΔCD ~ -6 nm (a)

,00 ooEj

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Weak-CA 3

ΔCD ~ -12.7 nm (b)

Fig. 5. SEM images of two of the failing contacts highlighted by PWORC and showing the largest deviation from the postetch specs after a random chip lot was measured.

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3. PROCESS WINDOW OPC ALGORITHM 3.1 Process Window OPC and Overlay Constraints Nominal OPC algorithms aim to minimize the difference between the simulated printed resist contours and the design target on each measurement site. This difference between the target and the printed contours is often known as the edge placement error (EPE). Nominal OPC will distort the mask shapes according to the amount necessary to minimize EPE at nominal focus conditions, but as was observed through our PWORC and wafer verification, this can lead to printed contours falling outside the tolerance band at out of focus conditions. In fact, given the large curvature of the Bossung plots in section 2.2, it is clear that the CD value at best focus will correspond to outer contour of the pvband, while the mean CD has a smaller value and inner pvband contour is likely to fall outside the tolerances. Hence it is expected that mainly isolated and semi-isolated features suffer from weak process window. This situation is illustrated in figure 6(a) for a random isolated contact in the layout and reinforced by the mainly negative EPE distribution at defocus conditions plotted in figure 10(a). Common solution approaches to this problem such as the application of sub-resolution assist features or the development of selective biasing rules, would require prior simulation analysis. Alternatively, a PWOPC algorithm was implemented, tailored to improve the process window of these features, to safely apply fine model based design retargeting to center the expected mean CD through process and bring both outer and inner pvband contours inside the tolerance bands. Specifically, a PWOPC code was enabled by OPC-pro LAPI (Litho Application Programming Interface) and executed on Calibre OPC-pro from Mentor Graphics, which retargeted to the high tolerance limit of +3nm from target all failing sites at defocus conditions. In this manner, the new nominal contour aims to print at the high tolerance limit while still within the tolerance band, and allows for the contours at defocus conditions to also fall within the tolerance bands. The pursued effect of centering the process variability bands within a tolerance band of ±3nm is plotted in figure 6(b) for the isolated contact of figure 6(a). Figure 7 represents the PWOPC algorithm flow, with the step described above covering block (1). No new sites were employed for PWOPC and all site placements were chosen identical to the nominal OPC site placement.

Target

Printed Image @Nominal Conditions

Printed Image @Out of Focus Conditions

Tolerance Band

+3nm -3nm

OPC site

Centered PVBand

Nominal OPC

PWOPC (b)

(a)

Fig. 6. PWOPC retargeted to the high tolerance limit all failing sites at defocus conditions such that the process variability bands for this measurement site is centered within a tolerance band of +/-3nm.

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In order to guarantee robust printability, PWOPC intentionally introduces deviations from the designer intent at nominal conditions. With the application of the PWOPC described above, where contact CD is deliberately made to print larger than designed at nominal conditions, then overlay violations and the risk of shorts become a concern. Hence additional constraints need to be implemented in order to maintain inter-layer overlay above ground rules minimum, which in this case of contact layer, are critical with respect to the polysilicon layer (PC). In particular, those contact fragments that fell within a the ground rule distance from a PC edge were marked as “close-to-PC” during execution of PWOPC and subsequently were not allowed to move, forcing corrections to be applied only on the remaining non-marked edges. Figure 8(a) shows weak CA number 1 of table 1, which has one of the contact edges falling in close proximity to a PC line, hence restricting any further movement of this edge, and allowing readjustments only on the remaining three edges. This example shows a case of application of PWOPC on one of the critical spots highlighted by PWORC. Figure 8(b) show another common example of two contacts in close proximity to two PC lines that restrict the movement on two of the perimeter edges, hence allowing correction to be applied on the other two edges only. Ground rule restrictions prevent all four contact edges from falling in close proximity to PC, and they also cover those to Metal and Active layers which were less restrictive. Finally, all other non-flagged edges receive OPC based on the EPE at defocus conditions readout and the original target. These last two steps correspond with blocks (2) and (3) on the block diagram of figure 7. Overall, PWOPC resizes trouble contacts and asymmetrically re-centers their pvbands in a precise amount based on process window simulations. Overlay violations are also avoided with additional rules.

Nominal OPC Mask

Model Based Retargeting of Defocus Failures

CA-PC Overlay Constraints

(1)

(2)

PWOPC

(3)

PWORC

(4)

Fig. 7. Custom PWOPC algorithm block diagram.

3.2 Process Variability Bands Simulated pvbands are shown in figure 9(a) for the case of nominal OPC mask shapes and PWOPC mask shapes corresponding to the case illustrated in figure 8(a). It is clear from the position of the simulated resist contours at the three unrestricted edges that PWOPC introduced deviations from the target at nominal conditions. The design target, however, is still within the pvband, which is now kept within the tolerance bands, and the mean resist contour placement through process is expected closer to the target. Also visible in figure 9(a) is the effect of the overlay control which restrict the movement of the edge closest to the PC line and, therefore the PVbands for the nominal OPC and the PWOPC masks on this fragment mostly overlap. Small variations of the resist contours on this constrained edge result from the diffraction proximity effect due to the adjustment of the remaining edges. Displayed in figure 9(b) are the pvbands for the nominal OPC mask and the PWOPC mask corresponding to the case of figure 8(b), where the effects of close contact proximity and of two close polysilicon lines is visible. The process window correction algorithm used exactly the same process models (optical and resist models) and process conditions that the nominal corrections. It was observed in section 2.3 that this model could result in some inaccuracies at conditions very out of focus, falling short of predicting the exact amount of contact area shrinking with defocus. Hence, PWOPC could still be applying conservative corrections, so it is guaranteed that PWOPC will not necessarily drive excessively large changes, but the concern arises in that it will not fully compensate for the weak contacts out of focus.

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Weak CA 1

Other CA

Final Mask Layout

OPC Sites

PWOPC

Close to PC Marker

PC Nominal OPC

(b)

(a)

Fig. 8. Example of overlay constraints for (a) weak CA number 1 of table 1, which has one of its edges falling in close proximity to a PC line, hence restricting any further movement in this direction, and (b) another common example of a contact in close proximity to two PC lines that restrict the movement on two of its edges.

Simulated Resist Contours

Simulated Resist Contours

Target CA PV Band with Nominal OPC PV Band after PWOPC

OPC Sites

PC

PC

(a)

(b)

Fig. 9. Simulated process variability bands (PVbands) of resist contours across a range of defocus and dose errors. The most outer contour and most inner contours form the borders of the PVbands. Resist simulations are shown for both cases of nominal OPC mask and PWOPC mask using exactly the same optical and resist models. (a) weak CA number 1 of table 1, and (b) example of two contacts in close proximity to two PC lines.

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3.3 Edge Placement Error Histograms This new PWOPC code was then applied to the entire chip layout and EPE distribution data was computed at nominal focus and at 100nm defocus. Nominal OPC was also run at nominal and out of focus conditions in order to record EPE distribution data for this mask. OPC algorithms based solely on the simulated contours at 0nm defocus will attempt to minimize the edge placement error (EPE) only at nominal conditions. This is clear from the plot of the EPE distribution at nominal conditions for the nominal-based OPC (Nominal OPC) mask displayed in figure 10(a). The number of instances of EPE larger than 5nm in absolute numbers (actually smaller than -5nm EPE error) for this mask when evaluated at 100nm out of focus was 68.53K as shown in the EPE distribution at defocus conditions in the same figure 10(a). By compromising on slightly larger EPE at 0nm defocus as with the PWOPC mask, the curve of EPE distribution at nominal conditions is allowed to shift towards positive values while still remaining tightly centered about 1nm as shown in figure 10(b). The curve for EPE distribution at out of focus conditions for this mask is thus also significantly shifted towards smaller absolute values as seen in figure 10(b), and the number of instances of EPE smaller than -5nm across focus is reduced to 1.36K, that is, about 50X smaller with PWOPC. PWOPC thus provides a final process with across focus variability shifted toward zero relative to that of the nominal OPC mask without violating the tolerance specs. This algorithm imposed a runtime increase approximately 3X that for the chip under evaluation. Steps (2) and (3) of the bock diagram in figure 7 have the largest impact on runtime, step (3) due to the required optical and resist simulations, and step (2) due to the additional computational burden on measuring and tagging inter-level distances. At 65nm technology the overall turn around time of PWOPC still remained within hours. Potentially faster and more advanced PWOPC algorithms have appeared and are available today on engines such as OPC-pro from Mentor Graphics [13] and Invarium [14]. After PWOPC was applied on the entire layout, this mask also successfully passed a second round of process window ORC as indicated by step (4) of the diagram in figure 7.

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Fig. 10. Edge Placement Error (EPE) histograms at nominal and out of focus conditions for (a) the mask prepped with OPC based solely on nominal conditions and (b) the mask prepped with PWOPC.

4. LITHOGRAPHIC PERFORMANCE OF PWOPC MASK 4.1 Simulated Lithographic Performance Process variability band simulations like the one displayed in figure 9 were used to generate resist CD data across dose and focus and form Bossung curves as those illustrated in figure 11(a) for the nominal-OPC mask of the feature in figure 8(a), and in figure 11(b) for he PWOPC mask of the same feature. Example in figure 11 corresponds to weak contact

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number 1 of table 1. Although the overall effect is subtle, a comparison of figure 9(a) against 9(b) shows that the response through focus becomes slightly less sensitive to defocus errors. Improvement can be quantitatively measured through the computation of the maximum depth of focus (DoF) allowed for each value of exposure latitude (EL) as plotted in figures 12(a) and 12(b) for the nominal-OPC and PWOPC masks, respectively. At 10% exposure latitude, the depth of focus can be seen to improve by a 6% with the PWOPC mask. Moreover, the overall process window performance, measured as the area under the curve, is estimated to improve about 12% with the PWOPC mask over the nominal-OPC mask.

PWOPC

Nominal OPC 120

0

110

01

00S

0 COS Focus (sm)

01

QIS

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.Ot

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Fig. 11. Simulated CD through dose and focus (Bossung curves) for weak contact number 1 as computed using (a nominalOPC mask and (b) the PWOPC masks.

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25 25

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D 20 =

jJ15

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DOF: 0.219iJm Exp Let: 10.031% Cerder Dose: 33.694 EU Center Focus: 0.013 pm

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005

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Fig. 12. Lithographic Exposure Latitude-Depth of Focus plots computed from the pattern Bossung curves for the nominalOPC and PWOPC masks, respectively.

4.2 Verification on Product Wafer Two sets of wafers were used for verification. Both sets were exposed with exactly the same process and anchor conditions, but one set used the mask processed with the nominal OPC code while the other was exposed with the new mask processed with the PWOPC code. Focus-Exposure matrices (FEMs) were measured for a number of locations, including SRAMs and the critical weak-CA locations of table 1 as previously highlighted by PWORC. The same exercise was carried out on both stack wafers and product wafers with underlying topography. Similar conclusions were drawn from the data measured on either set of wafers, although the results in this section correspond to data measured on product wafers. Figure 13(a) displays the Bossung curves, i.e. measured wafer CD across focus at several exposure dose values, for weak contact number 1 of table 1. It is observed that this contact received as much as 10nm compensation at

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nominal conditions, hence also improving the performance within ±100nm defocus by nearly the same amount. Similarly, as the data collected in table 2 suggests, most isolated and semi-isolated contacts received the appropriate amount of compensation, based on the deviations across process window, while nested CAs as the one of figure 13(b) received little or none.

Weak-CA 4

Wafer CD (nm)

135

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125 115

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Fig. 13. Focus-Exposure matrices (FEMs) measured on two sets of wafers exposed with exactly the same process and anchor conditions, but one using the nominal OPC mask while the other was exposed with the mask processed with PWOPC. (a) Bossung curves for weak contact number 1 of table 1. (b) Nested contact.

Process window (PW) and depth of focus (DoF) values were extracted from the measured Bossung curves and collected in table 2. The data under column “DoF Improvement” in table 2 refers to the improvement on depth of focus between measured resist CD collected on the wafers exposed with the PW-OPC mask relative to wafers exposed with the nominal-OPC mask. An average 16% measured DoF improvement in lithographic performance was observed as a consequence of PWOPC on most isolated and semi-isolated contacts. This improvement was achieved without producing bridging issues through focus and dose.

SRAM CA Iso CA Semi-Nested Weak-CA 1 Weak-CA 2&3 Weak-CA 4

Comp (nm) DoF Improvement 5nm 17% 9nm 19% 7nm 30% 10nm 11% 5nm 13% 7nm 9.33%

Table. 2. Measured compensation applied by PWOPC on selected weak areas across the mask as measured on the wafer. Depth of focus (DoF) values were extracted from the measured Bossung curves and the improvement of DoF on the wafers exposed with the PWOPC mask calculated with respect to the DoF on wafers exposed with nominal-OPC mask

4.3 Wafer Final Test Final wafer yield statistics were calculated on a total of 16 wafers exposed with the new 65nm PWOPC CA mask for a relevant product design and compared to the fab baseline for this process as determined by data corresponding to the Nominal-OPC CA mask. The study was done using 3 CD splits, one where the exposure was anchored at the process nominal conditions, one where the exposure was anchored to print a CD 8nm larger than the target CD at nominal, and one where the exposure was anchored to print a CD 8nm smaller than the target CD. Overall, the wafer final test (WFT) yield resulted in 8 points improvement relative to the fab baseline. These WFT yield results are plotted relative to the baseline in figure 14 for all wafers under evaluation. Among these wafers, the highest yielding was 13 points above the baseline and the lowest yielding one was still a couple of points above the baseline. This improvement came at the

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expense of a 3X runtime penalty on the design processing prior to building the mask, but required no additional RET optimization or OPC model calibration.

Wafer Final Test

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0

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W afer Number

Fig. 14. Wafer final test (WFT) yield results for a total of 16 wafers exposed with the new 65nm PWOPC CA mask and compared to the fab baseline for this process as determined by data corresponding to the Nominal-OPC CA mask. The study was done using 3 CD splits, one where the exposure was anchored at the process nominal conditions, one where the exposure was anchored to print a CD 8nm larger than the target CD at nominal, and one where the exposure was anchored to print a CD 8nm smaller than the target CD. Overall, 8 points yield improvement relative to the fab baseline was achieved.

5. SUMMARY AND CONCLUSIONS This paper demonstrates the value of an early adoption of process window-aware computational tools such as process window OPC and process window verification, even in technologies that typically do not receive such treatment. In fact, process window ORC unveiled the precise cause of a decrease in wafer yield of a 65nm CA level, which subsequent wafer verification confirmed. It was determined that isolated and semi-isolated contacts suffered from a weak process window at defocus conditions that contributed to unusually large numbers of open failures. This situation could have required a new resolution enhancement technique and new OPC models, but instead a custom process window OPC algorithm was implemented that selectively improved the performance of weak process window areas while maintaining printed contours within tolerances and avoided overlay violations. A new mask was built and focus-exposure wafers exposed that demonstrated an improved process window of isolated and semi-isolated contacts, while nested contacts and overlay constraints were maintained. Wafer final test (WFT) yield resulted in an 8 point improvement with this new PWOPC mask relative to the fab baseline for this process as using the Nominal-OPC mask, while all other conditions were maintained constant. The PWOPC concept applied in this work refers to the act of compromising the EPE at nominal conditions to improve the process window. Our algorithm performed retargeting and OPC based on EPE readout at defocus conditions. Different approaches exist under the same label that aim at centering the pvbands within tolerances, or at ensuring that the mean expected edge position rather than the nominal contour falls closest to the design target, or simply attempt to improve yield by ensuring process window printability of weak areas. The current PWOPC was designed to improve yield but, since trouble contacts are both resized and their pvbands re-centered in a precise amount based on process window simulations, the mean expected edge placement is also potentially more stable with process variations, hence also improving the circuit timing characteristics. Further evaluation of this effect, while relevant, was beyond the scope of this paper. Inter-level overlay constraints was a significant component of our PWOPC algorithm. Shrinking budgets for inter-level spacing, on the other hand, and increasing OPC runtimes in newer technology nodes is limiting the application of PWOPC across the chip. Instead, application on problematic areas may become a more common use model.

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6. ACKNOWLEDGEMENTS The authors would like to acknowledge Dario Gil, Tim Farrel, Scott Mansfield and Alan Leslie for management support and Lars Liebmann for discussion, technical support and for presenting this material at the SPIE Optical Microlithography 2009 conference.

REFERENCES [1] [2] [3] [4] [5]

[6] [7] [8] [9] [10] [11]

[12] [13] [14] [15]

Azalia Krasnoperova, James A. Culp, Ioana Graur, Scott Mansfield, “Process Window OPC for Reduced Process Variability and Enhanced Yield”, Proc. SPIE 6154, 61543L-1, (2006). Ioana Graur, James A. Culp, James Bruce, Mohamed Al-Iman, Mohamed Bahnas, “Tolerable CD Variation Analyzer Using Perturbed Nominal Models Demonstrated on AltPSM” Proc. SPIE 5992, 59920H, (2005). Franklin M. Schellenberg. “Resolution Enhancement Technology: The Past, the Present, and Extensions for the Future”. Proc. SPIE Vol. 5377, p.1, (2004) Bahaa E. A. Saleh and Soheil I. Sayegh. “Reduction of Errors of Microphotographic Reproductions by Optical Corrections of Original Masks”. Optical Engineering, Vol 20(5). Pp. 781-784 (1981). O. W. Otto, J. G. Garofalo, K.K. Low, C-M Yuan, R. C. Henderson, C. Pierrat, R. L. Kostelak, S. Vaidya, P. K. Vasudev. “Automated Optical Proximity Correction – A rules-based approach” Proc. SPIE, Vo; 2197, pp. 278-293, (1994). Nick Cobb, Avideh Zakhor, Eugene Miloslavsky. “Mathematical and CAD Framework for Proximity Correction”. Proc. SPIE, Vol. 2726, pp. 208-222, (1996). Pati YC and Kailath T. “Phase-Shifting Mask for Microlithography – Automated Design and Mask Requirements” J. Optical Society of America A, Vol. 11(9), pp. 2438-2452, (1994). John P. Stirniman and Michael L. Rieger. “Fast Proximity Correction with Zone Sampling” Proc. SPIE, Vol. 2197, pp.294-301,(1994). Ching-HengWang, Qingwei Liu, Liguo Zhang. “Optimized OPC approach for process window improvement”. Proc. of SPIE Vol. 6924, 69243E, (2008). R. S. Fathy, M. Al-Imam, H. Diab, M. M. Fakhry, J.A. Torres, B. Graupp, J. M. Brunet, M. S. Bahnas. “Litho Aware Method for Circuit Timing/Power Analysis through Process”. Proc. of SPIE Vol. 6521, 65210O, (2007). William Howard, Jaione Tirapu Azpiroz, Yalin Xiong, Chris Mack, Gaurav Verma, William Volk, Harold Lehon, Yunfei Deng, Rui-fang Shi, James Culp, Scott Mansfield. “Inspection of Integrated Circuit Databases through Reticle and Wafer Simulation: An Integrated Approach to Design for Manufacturing (DFM)”. Proceedings of SPIE Vol. 5756, p. 61. (2005). Y. Granik and N. B. Cobb. “New process models for OPC at sub–90nm nodes,” Proc. SPIE 5040, 1166–1176, (2003). James Word and Kyohei Sakajiri, “OPC to Improve Lithographic Process Window” Proc. SPIE Vol. 6156, 61561I, (2006) Apo Sezginer, Franz X. Zach, Bayram Yenikaya, Jesus Carrero, Hsu-Ting Huang “Sequential PPC and processwindow-aware mask layout synthesis”, Proc. SPIE Vol. 6156, 615613, (2006) Bayram Yenikaya and Apo Sezginer. “A rigorous method to determine printability of a target layout”, Proc. of SPIE Vol. 6521, 652112, (2007)

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