Increased Multilayer Fabrication and RF ... - IEEE Xplore

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 7, JULY 2014

Increased Multilayer Fabrication and RF Characterization of a High-Density Stacked MIM Capacitor Based on Selective Etching Victor Farm-Guoo Tseng, Member, IEEE, and Huikai Xie, Senior Member, IEEE

Abstract— This paper presents the fabrication and characterization of a high-density multilayer stacked metal–insulator–metal (MIM) capacitor based on a novel process of depositing the MIM multilayer on pillars followed by polishing and selective etching steps to form a stacked capacitor with merely three photolithography steps. In this paper, the pillars were made of glass to prevent substrate loss, whereas an oxide–nitride–oxide dielectric was employed for lower leakage, better voltage/frequency linearity, and better stress compensation. MIM capacitors with six dielectric layers were successfully fabricated, yielding capacitance density of 3.8 fF/μm2 , maximum capacitance of 2.47 nF, and linear and quadratic voltage coefficients of capacitance below 21.2 ppm/V and 2.31 ppm/V2 . The impedance was measured from 40 Hz to 3 GHz, and characterized by an analytically derived equivalent circuit model to verify the radio frequency applicability. The multilayer stacking-induced plate resistance mismatch and its effect on the equivalent series resistance (ESR) and effective capacitance was also investigated, which can be counteracted by a corrected metal thickness design. A low ESR of 800 m was achieved, whereas the self-resonance frequency was >760 MHz, successfully demonstrating the feasibility of this method to scale up capacitance densities for high-quality-factor, high-frequency, and large-value MIM capacitors. Index Terms— Capacitance density, equivalent series resistance (ESR), metal–insulator–metal (MIM) capacitor, multilayer stack, polishing, radio frequency (RF) passive device model, selective etching.

I. I NTRODUCTION

T

HE on-chip integration of passive components, such as capacitors and inductors [1]–[4], has received increasing attention in the past decade due to the rising demand for portable devices, requiring miniaturized passives with high precision, high-quality factor, high bandwidth, and low cost for radio frequency (RF), analog/mixed signal, and power applications [5], [6]. Capacitors are undoubtedly the most ubiquitously employed passive component, with picofaradranged capacitors typically used for RF matching and filtering, and nanofarad-ranged capacitors widely used for noise decoupling and sample-and-hold functions. Currently,

Manuscript received February 11, 2014; revised April 21, 2014; accepted May 14, 2014. Date of publication June 3, 2014; date of current version June 17, 2014. This work was supported by ARPA-E under Award DE-AR0000105. The review of this paper was arranged by Editor N. Bhat. The authors are with the Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL 32611 USA (e-mail: [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2014.2325491

back-end-of-line (BEOL) integrated metal–insulator–metal (MIM) capacitors are gaining mainstream status due to their superior performance. Compared with other integrated capacitor technologies, such as the polysilicon/silicon-based trench capacitors [7], [8] and crown-shaped capacitors [9], or the native intrametal lateral flux capacitors [10], [11] (also known as metal–oxide–metal capacitors), MIM capacitors offer lower resistive loss, lower substrate coupling noise, no charge depletion-induced voltage dependence, higher self resonance, and moderately high capacitance density [2]. However, as the capacitance density requirements stated in the latest 2011 International Roadmap for Semiconductors (ITRS) [12] continue to increase, further thinning of the dielectric layer tends to lead to excessive leakage currents and dielectric loss, thus either opting for high-k dielectric materials [13]–[16] or migrating to multilayer stacked structures [2] cannot be avoided. Yet, high-k dielectrics tend to exhibit permittivity with higher bias voltage dependence, whereas multilayer stacking will inevitably increase the complexity and cost of the fabrication due to the repetitive photolithography and etching steps, resulting in a tradeoff between capacitance density, performance, and low-cost manufacturing. To resolve the interconnection dilemma of stacked MIM capacitors, we have previously demonstrated a novel fabrication process [17] based on the selective etching of two alternating metal plate materials, allowing the parallel stacking of several tens of MIM capacitors with a minimal amount of additional process steps. Thicker medium/high-k dielectrics with better voltage linearity and lower loss [18], [19] could be used in this case, and other techniques, such as increasing the electrode surface area combined with atomic layer deposition (ALD) [20], could be incorporated into this technology as well, thus enhancing the capacitance/energy density and performance without incurring an undesirably high manufacturing cost. In this paper, to further establish the feasibility of this method to scale up capacitance density, pillars made of glass were employed to prevent substrate loss, whereas an oxide–nitride–oxide (ONO) dielectric was used as an attempt to lower the leakage current, improve the voltage/frequency linearity [18], [19], and compensate for the inherent film stress to increase the number of stacks, with which six-layer stacked MIM capacitors were successfully fabricated. Furthermore, the impedance was measured from DC up to RF frequencies, and characterized by a more comprehensive equivalent circuit model based on our previously derived analytical model [17]

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to verify the RF applicability of the device. The plate resistance mismatch and its effect on the equivalent series resistance (ESR) and effective capacitance was also taken into account, showing that a corrected metal thickness should be used to minimize effective capacitance frequency dependence. Although the measured ESR and leakage currents were larger than prediction, possibly due to polishing damage on the MIM cross section, the effectiveness of this fabrication method to scale up capacitance densities for high-quality-factor, high-frequency, large-value MIM capacitors was nevertheless successfully demonstrated. II. D EVICE C ONCEPT AND FABRICATION The core concept of our device fabrication is illustrated in the sequence of process step cross sections shown in Fig. 1. First, two rounded pillar-like structures are formed by isotropic etching into the substrate or underlying material [Fig. 1(a)]. To access the individual layers of a MIM multilayer stack without resorting to numerous photolithography steps, the multilayer stack is deposited onto the pillar structures [Fig. 1(b)], and then fine polished down to expose the multilayer cross section on a horizontal surface at the edge of the pillars [Fig. 1(c)], allowing the ease to perform further process steps on each layer. As shown, the capacitor conductive layers are also chosen as two alternating metal materials (metal 1 and metal 2) that possess material properties, which allow them to be selectively etched via chemical reactions. Hence, two specific wet etch processes, each designated to etch only metal 1 or metal 2, are conducted on either one of the pillars, slightly receding the top of only one metal material down into the etched trenches on the exposed cross section surface [Fig. 1(d) and (e)]. Then, a dielectric redeposition step is carried out to refill the trenches [Fig. 1(f)], followed by a carefully controlled anisotropic etch-back step to expose the top of only one type of metal material on each pillar [Fig. 1(g)]. Finally, two metal electrodes are formed on top of the pillars to interconnect the metal plates of the same material and complete the interdigitated MIM capacitor structure [Fig. 1(h)]. An obvious advantage of this process is the usage of only three additional photolithography steps while operating on near nanoscale structures without the need of high resolution/registration equipment. Regarding scaling limitations, the pillar height must be at least 1–2 times larger than the multilayer combined thickness, but the pillar areas could be decreased, and multiple pillars could be used to provide a better top surface for polishing. For this paper, a soda lime glass substrate was chosen to eliminate possible substrate leakage paths and coupling parasitic effects, whereas a BOE (6/1):HCl (37 wt.%):H2 O = 1:2:4 isotropic wet etch solution was used to etch and form the pillar structures, with the addition of HCl in the etchant mixture used to remove the precipitated insoluble components of the soda lime glass [21] to enhance sidewall smoothness. A photoresist on top of 100-nm-thick Cr composite etch mask was used for better interface adhesion to prolong the etch time before mask peeling off occurs [21]. As shown in Fig. 2, the pillars were etched to ∼30 μm in height, and the amount

Fig. 1. Fabrication process flow cross section. (a) Isotropic etching to form the pillars. (b) Deposition of the MIM multilayer stack. (c) Fine polishing to expose the multilayer cross section. (d) Selective metal 1 etch. (e) Selective metal 2 etch. (f) Dielectric redeposition. (g) Dielectric etch-back. (h) Electrode metallization.

of notching defects were greatly reduced compared with [17], thus forming smoother pillars to promote a good step coverage during the subsequent multilayer deposition step. For the MIM multilayer material composition, metal 1 and metal 2 were chosen as sputter deposited Au (sandwiched by two 20-nm Ti adhesion layers) and Cr, with both thicknesses as 0.25 μm. Ti/Au/Ti and Cr were chosen since this is the

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Fig. 2.

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 7, JULY 2014

Pillar structure formed by isotropic etching into the glass substrate.

Fig. 3. MIM multilayer cross section exposed on the edge of a pillar after the polishing step (the ONO layers are sandwiched between the Au and Cr layers).

simplest combination that can be selectively wet etched. The dielectric was chosen as plasma-enhanced chemical vapor deposition (PECVD) deposited ONO, with the silicon nitride thickness as 80 nm, and the two sandwiching silicon dioxide thicknesses as 10 nm. The entire MIM multilayer stack consists of four Cr layers, three Au layers, and six ONO dielectric layers in between the metal layers, whereas the first and last layers of the multilayer stack were 0.5-μmthick silicon dioxide layers used for protection/passivation. A 30-min forming gas (N2 /H2 ) anneal step at 400 °C was performed after the deposition of the entire multilayer stack. Compared with typical PECVD deposited silicon dioxide or nitride, the ONO dielectric offers a moderate dielectric constant with better voltage/frequency linearity as well as lower leakage due to its lower interface trap density [18], [19], and also helps to compensate for the overall accumulated stress within the multilayer stack due to the tensile stress nature of silicon nitride and compressive stress nature of silicon dioxide, thus achieving a larger number of MIM stacks. For the fine polishing step, an alumina lapping film with 0.3-μm abrasive was first used to grind through the MIM multilayer stack, and then a fine porous polyurethane polishing cloth with 0.05-μm colloidal silica/alumina suspension slurry was used to refine the polished surface. The polishing rate and uniformity were controlled using specific sample fixtures to maintain levelness and apply different pressures, whereas thick photoresist was spin coated to protect the recessed capacitor area from being attacked [Fig. 1(c)]. Fig. 3 shows the exposed multilayer cross section on the edge of a glass pillar after the

Fig. 4. Close-up view of process details after the selective Au and Cr etch, dielectric redeposition, and dielectric etch-back steps. (a) Only the Au layers exposed on one pillar. (b) Only the Cr layers exposed on the other pillar.

polishing step, with the individual Au, Cr, and ONO layers clearly seen. Gold etch TFA (8 wt.% I2 , 21 wt.% KI, 71 wt.% H2 O) and chromium etch 1020 [6 wt.% HNO3 , 16 wt.% (NH4 )2 Ce(NO3 )6 , 78 wt.% H2 O] from Transcene were chosen, respectively, as the etchants for the selective Au and Cr etch, as both were shown to be highly selective to all the other materials used. A short Ti etch [HF (49 wt.%):H2 O2 (30 wt.%):H2 O = 1:1:20] was also done after the selective Au etch to remove the remaining Ti adhesion layers. The dielectric redeposition and etch-back steps were done by first depositing a 0.4-μm-thick PECVD silicon dioxide as the refill, and then conducting a CHF3 plasma-based reactive ion etch to remove the excess silicon dioxide. Process results on both pillars after the sequence of selective metal etch, dielectric redeposition, and etch-back steps are shown in Fig. 4(a) and (b), with only the Au layers exposed on one pillar, and only the Cr layers exposed on the other. Finally, two Cu electrodes were electroplated onto the top of the pillars to a thickness of ∼20 μm from a Cu/Cr seed layer through a photoresist mold, and the seed layer was then removed. The Cu thickness is needed to provide a lower ESR and also protect the fragile multilayer cross section. The completed six-layer stacked MIM capacitors are shown in Fig. 5. In this paper, capacitors with areas of 300 μm × 800 μm and 800 μm × 800 μm were successfully fabricated. Among all process steps, the critical device failure modes were found to originate from various polishing-induced damages to the multilayer cross section, resulting in various

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Fig. 7.

Unit half capacitor cell for modeling purpose.

Fig. 8.

Single-port equivalent circuit model for the stacked MIM capacitor.

Fig. 5. Completed six-layer-stacked MIM capacitors (area of 300 μm × 800 μm).

Fig. 6. Example of the polishing-induced smearing and shattering damages on the MIM multilayer cross section at the edge of the pillars.

electrical contact issues between the Cu electrode and metal plates. Examples of these damages are shown in Fig. 6, such as the smearing of the softer Au over the other layers, and the films or substrate material chipping away or slightly shattering. Precisely controlled chemical–mechanical polishing equipment should be employed for future process improvement, whereas maintaining a lower grinding rate through the MIM multilayer. III. C APACITOR M ODELING To more accurately model the broadband capacitor impedance response, a compact analytical model was constructed based on decomposing an MIM capacitor into numerous unit half capacitor cells (Fig. 7), each resembling a half parallel plate transmission line structure. Assuming an equipotential surface at the middle of the dielectric (valid with a sufficiently small electrical size condition) and no dielectric loss, the unit cell impedance can be expressed as [17], [22] μd td x td ρm x + iω −i Z (x, y, ω) ∼ = 3ytm ωεd yx y

(1)

with ρm and tm as the resistivity and thickness of the metal plate, y and x as the width and length of the unit half capacitor cell, and εd , μd , and td as the permittivity, permeability, and thickness of the half dielectric layer. The plate resistance, series capacitance Cs , and series inductance L s (typically below 50 fH) of each capacitor layer can then be calculated.

For an entire-stacked capacitor with constant metal and dielectric thicknesses, the current path sharing through the metal plates in the middle of the multilayer stack must be considered, causing the plate resistance of the middle capacitors (R2 –R5 ) to be roughly 1.72 times the plate resistance of the edge capacitors (R1 and R6 ) for the current Au/Cr plate sequence arrangement, referring to the single port lumped equivalent circuit model shown in Fig. 8. The dominant source of inductance was found to be due to the electrodes, and denoted as ESL. C p represents the parasitic capacitance between the electrodes and probes that needs to be de-embedded during the measurements. All dielectric related losses are combined into the term Rd , and when the capacitor quality factor is much larger than 1, Rd can be expressed as Rd =

tan δ (ωε + σ )/ωε = ωCtot ωCtot

(2)

with εd = ε − iε defined as the complex permittivity of the dielectric, Ctot as the total capacitance (6 × Cs in this case), and σ representing the bias voltage-dependent small signal conductivity of the dielectric. Rd is only significant at lower frequencies. The frequency response of the ESR and effective capacitance Ce of the entire capacitor can then be simulated. The plate resistance mismatch between the individual capacitor layers leads to a variation among the RC cutoff frequencies, causing ESR and Ce to have frequency dependence, even when Rd and inductance effects can be neglected. Before reaching the cutoff frequencies, Ce is equal to Ctot , and for an N-layer stacked MIM capacitor, ESR can be expressed as   N  Cs 2 Ri (3) ESR = Rd + Ctot i=1

with i denoting each capacitor layer and Ri as its plate resistance. Upon reaching the cutoff frequencies, ESR and

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Fig. 9.

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 7, JULY 2014

Low-frequency ESR measurements and modeling results.

Ce start to drop, until ESR reaches its minimum value as Rd plus the parallel connection of all Ri ’s, and Ce reaches its minimum value of 1 (4) Ce =   2 N  i=1

1 Cs

Ri Rtot

with Rtot as the sum of all Ri ’s. This drop in Ce at higher frequencies can be corrected by redesigning the metal plate thicknesses to match all Ri ’s, such as doubling the Cr plate thicknesses in the middle of the multilayer stack. Increasing the number of stacks will reduce the amount of drop in Ce at higher frequencies. The variation among dielectric layer thicknesses will also increases the ESR and Ce frequency dependence. IV. M EASUREMENT R ESULTS To measure the capacitor impedance, an HP4294A impedance analyzer with a Cascade Microtech DCP100 probe was used for lower frequencies from 40 to 10 MHz, and an E4991A RF impedance analyzer with a GGB model 40A-GS-150P Picoprobe set was used for higher frequencies from 1 MHz to 3 GHz. The measured capacitance of the six-layer-stacked MIM capacitors with areas of 300 μm × 800 μm (size 1) and 800 μm × 800 μm (size 2) were 1.03 and 2.47 nF, respectively, yielding a capacitance density of ∼3.6–3.8 fF/μm2 , which is approaching the current capacitance density requirements stated in the 2011 ITRS [12]. Due to the experimental nature of this paper and the unstable polishing process, the yield was as low as ∼10% out of around 250 devices. The low frequency response of the ESR for both capacitor sizes are shown in Fig. 9, showing close coherence with the modeling results. At frequencies >800 Hz, ESR is dominated by the leakage current, which increases the ESR and lowers the quality factor. From the ESR plot, the fitted σ of the dielectric was found to be ∼9 ×10−12 S/cm, which is still higher than typical dielectrics [18], but roughly 2.3 times lower than [17]. At midfrequencies, dielectric loss tangent effects dominate, achieving a maximum quality factor of 250 at 20 kHz with a

Fig. 10.

RF measurements and modeling results for (a) ESR and (b) Ce .

tanδ of roughly 0.0034. At frequencies >1 MHz, ESR reaches its minimum dominated by the combined plate resistance, and is ∼800 m for size 1 capacitors and 1030 m for size 2 capacitors. The higher than predicted plate resistance was due to the aforementioned polishing-induced electrical contact defects, and an improved polishing process is currently under development. The more detailed RF response of the ESR and Ce for size 2 capacitors are shown in Fig. 10(a) and (b). As mentioned in Section III, due to the plate resistance mismatch, ESR and Ce exhibit a drop of ∼7% after 10 MHz, corresponding well with the modeling results. In addition, shown in the plots are the simulated ESR and Ce if the middle and edge Cr plate thicknesses were corrected to achieve a uniform plate resistance of 980 m, showing that the drop in Ce can be eliminated. Ce rises again after 100 MHz due to the frequency approaching the self-resonance frequency, which is ∼760 MHz for size 2 capacitors and ∼1.26 GHz for size 1 capacitors, corresponding to an ESL of ∼17 pH. The normalized C–V measurements at 10 kHz, 1 MHz, and 10 MHz are shown in Fig. 11, with the quadratic and linear voltage coefficients of capacitance (VCC) displayed as α (in ppm/V2 ) and β (in ppm/V), respectively. From 10 kHz to 1 MHz, α and β are shown to be relatively constant with a slight decrease, reaching very low values of −0.29 ppm/V2 and 2.14 ppm/V, respectively, which are expected due to the

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with a VCC 760 MHz for nanofarad ranged capacitors, which is suitable for analog filtering and decoupling. By further substituting for state-of-the-art high-k dielectrics [13], increasing the number of stacks, optimizing the multilayer thicknesses, and improving on the polishing and dielectric refilling processes, a much higher capacitance density (>20 fF/μm2 ) with better impedance performance can be achieved. ACKNOWLEDGMENT Fig. 11.

Normalized C–V measurements at 10 kHz, 1 MHz, and 10 MHz.

The authors would like to thank the Nanoscale Research Facility and the Interdisciplinary Microsystems Group of the University of Florida for providing the equipment needed for device fabrication and characterization. R EFERENCES

Fig. 12.

Leakage current density measurements.

larger ONO dielectric thickness used. At 10 MHz, α and β increase to −2.31 and 21.2 ppm/V, possibly due to the variation among the RC cutoff frequencies, causing more electric field to be applied on the capacitor layers with less plate resistance. At frequencies below 500 Hz, α and β rises again, possibly due to the nonlinear bias voltage-dependent leakage current. The measured leakage current density is shown in Fig. 12, with the calculated dielectric conductivity near zero bias voltage roughly corresponding to the σ value mentioned above. The leakage current of the dielectric in this paper was still one to two orders of magnitude larger than typical dielectrics of similar thickness [18], and a premature breakdown was occasionally seen at ∼7 V, indicating that either the dielectric deposition process needs to be improved, or there are excessive remnant air voids in the dielectric refill. A better polishing process that induces fewer defects, or a more conformal dielectric refill process, such as ALD, could be used as a future remedy. If corresponding selective etching processes could be found, higher work function metals could be employed to help reduce the leakage current, or IC BEOL compatible metals (TiN/Cu or Al) could be employed for ease of integration. V. C ONCLUSION The fabrication and RF characterization of a stacked MIM capacitor based on a novel selective etching method is reported, achieving a capacitance density of 3.8 fF/μm2 ,

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Victor Farm-Guoo Tseng (M’13) received the B.S. and M.S. degrees in electrical and computer engineering from National Chiao Tung University, Taiwan, in 2005 and 2007, respectively. He is currently pursuing the Ph.D degree in electrical and computer engineering with the University of Florida, Gainesville, FL, USA. He was with Texas Instruments from 2009 to 2010 as a DLP product engineer. His research interests include MEMS, high density capacitors/inductors, and electromagnetic sensing.

Huikai Xie (M’02–SM’07) received the M.S. and Ph.D degrees in electrical and computer engineering from Tufts University in 1998 and Carnegie Mellon University in 2002, respectively. He joined the University of Florida in 2002, where he is currently a professor in the ECE department. His research interests include MEMS/NEMS, microactuators, integrated power passives, CNTCMOS integration, optical MEMS, IR sensors, and biomedical imaging.