Influence of Thermal Cycling on the Thermal Resistance of Solder ...

Journal of ELECTRONIC MATERIALS, Vol. 38, No. 12, 2009

Special Issue Paper

DOI: 10.1007/s11664-009-0857-5 Ó 2009 TMS

Influence of Thermal Cycling on the Thermal Resistance of Solder Interfaces H.Y. GUO,1 J.D. GUO,1,3 and J.K. SHANG1,2 1.—Shenyang National Laboratory for Materials Science, Institute of Metal Research, Chinese Academy of Sciences, Shenyang 110016, China. 2.—Department of Materials Science and Engineering, University of Illinois at Urbana-Champaign, Urbana 61801, IL, USA. 3.—e-mail: [email protected]

The thermal resistance of Si/Sn-52In/Cu sandwiched samples was measured by the laser flash method after various stages of thermal cycling. The thermal resistance was found to increase with increasing thermal cycles after 120 cycles. Cross-sections of the samples were examined by scanning electron microscopy. Cracks were observed in both the solder bulk and the interface between the intermetallic compound and solder. The increase of the thermal resistance was related to widening of the crack segments that were inclined to the interface. Key words: Solder thermal interface materials, thermal cycling, thermal resistance, crack propagation

INTRODUCTION The design of an efficient heat transfer path is important to keep a microprocessor operating within its temperature limit. However, usually there are various interfaces along the thermal transfer path. It is well known that, when two solid surfaces are attached, asperities on each surface create gaps filled with low-thermal-conductivity air between the two solids at the interface, resulting in thermal contact resistance,1 as shown in Fig. 1. To minimize this thermal contact resistance, thermal interface materials (TIMs) are needed to fill the gap at the interface. Several types of TIMs have been developed, such as grease, gel, and phase change materials (PCMs). Most of the polymer-based materials have low thermal conductivities, e.g., below 5 W/m K. With increasing integration density in the microprocessor, heat dissipation has become a major issue. The thermal transfer capacity of traditional polymerbased TIMs has reached its limit because of their intrinsic low thermal conductivity, which limits

(Received February 26, 2009; accepted June 1, 2009; published online June 25, 2009)

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further improvement of the capacity for heat transfer in an integrated circuit (IC) package. Solder alloys are attractive TIMs because of their excellent thermal conductivity. However, there are several problems that limit the use of solders as TIMs, voiding being one of the main ones. Fleischer and coworkers2 found that, for small random voids, the thermal resistance of a solder die attach layer increased linearly with void volume percentage, whereas for large contiguous voids, the increase followed an exponential relationship. Hu et al.3 have performed experimental characterization of voids in solder-type TIMs by using low-thermalconductivity buried void-like inclusions. In their experiment, hot spots, with a 15°C temperature rise above the average die temperature, were found right on top of the void-like inclusions at a device power density above 50 W/cm2. Another main problem is the stress caused by the coefficient of thermal expansion (CTE) mismatch between the Si die, solder, and copper heat sink. Chen and Nelson4 performed analytical studies of thermal stress distributions induced by the CTE mismatch between bonded materials, and found that the maximum shear stress always occurs at the edge of the joint and that significant tensile stress may occur if flexure is allowed. He et al.5 measured the thermal

Influence of Thermal Cycling on the Thermal Resistance of Solder Interfaces

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Fig. 1. Diagram illustrating the waviness and roughness of two contacting surfaces. Fig. 2. Schematic of the laser flash method.

residual stress in a silicon die by Raman piezospectroscopic techniques, and the measured results agreed with the analytical results of Chen and Nelson.4 Olsen et al.6 pointed out that soft solders transmit very little stress to the die due to their very low mechanical strength and high ductility. These stresses would be primarily accommodated by the deformation of the soft solder joint, which results in creep and fatigue damage. However, exactly how these damages affect the thermal resistance of solder interfaces remains uncertain. In IC packaging, soldering is used to form various joints sequentially at different temperatures, so that solders with different melting points are required. In flip-chip ball grid array (FC-BGA) packages, eutectic Sn-Ag-Cu (SAC) solder, with a melting point of 217°C, is the most popular. Therefore, solders chosen as TIMs should be reflowed at temperatures lower than the melting point of eutectic SAC solder. It is recommended that the melting point of solder TIMs should be in the temperature range from 120°C to 150°C. In this study, eutectic Sn-52In (melting point 118°C) was studied as a solder TIM; the thermal resistance of the samples after various stages of thermal cycling was measured by the laser flash method and correlated with the microstructure of the interfaces. EXPERIMENTAL PROCEDURES The Sn-52In solder used in this study was prepared from high-purity materials (Sn, In: 99.99 wt.%). In this experiment, Si/solder/Cu sandwiched samples were prepared. Si slices with dimensions of 10 mm 9 10 mm were cut from wafers and then electroless plated with Ni-P metallization. Prior to soldering, the square copper plates were mechanically polished using 0.5-lm diamond paste, and then rinsed in deionized (DI) water and ethanol alcohol. The Sn-52In solder ingot was first rolled into a sheet with a thickness of 0.15 mm, then cut into slices with dimensions of 10 mm 9 10 mm. A Si/Sn-52In/Cu sandwich structure was then formed by using Sn-52In to solder one Si slice to one Cu plate. The thickness of the molten solder was maintained at about 100 lm by the use of two spacers. The sandwich sample was put on a hot

plate and reflowed at a temperature of 150 ± 5°C for 60 s. Mildly activated rosin flux was used during soldering. These samples were then cooled in air to room temperature and ultrasonically cleaned in acetone to remove dissolved rosin flux. After soldering, the samples were subjected to thermal cycling in the temperature range of 40°C to 100°C. The ramp-up heating time was 20 min, the holding time at 100°C was 10 min, and the cooling time was 57 min, without any holding time at 40°C. The period of each cycle was 87 min. The thermal resistance was measured by the laser flash method after various stages of thermal cycling. As shown in Fig. 2, the test instrument consisted of an 8-ns pulsed Nd:YAG laser, a HgCdTe (MCT) infrared (IR) detector with a response time of 40 ns, and a 500-MHz-bandwidth oscillograph. The thermal diffusivity a was calculated from Ref. 7 a ¼ 1:37L2 =ðp2 t1=2 Þ;

(1)

where t1/2 is the time required for the backside temperature to reach half of the maximum temperature rise and L is the thickness of the sample. Once the thermal diffusivity of the sample is known from the laser flash method, the effective thermal conductivity kcomposite of the sample can be calculated through kcomposite ¼ a qcomposite Ccomposite ;

(2)

where qcomposite and Ccomposite are the effective density and specific heat of the sample, respectively. qcomposite and Ccomposite were calculated from qcomposite ¼

Ccomposite ¼

LSi LCu LSn52In qSi þ qCu þ qSn-52In L L L (3)

LSi LCu LSn52In CSi þ CCu þ CSn-52In ; L L L (4)

where LSi, LCu, and LSn-52In are the thicknesses of Si, Cu, and Sn-52In solder of the sample, respectively. The effective total thermal resistance of the

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Fig. 3. Components of the thermal resistance for the Si/Solder/Cu sample.

Fig. 5. SEM images of as-reflowed interface microstructure: (a) on the Si side and (b) on the Cu side.

Fig. 4. Variation of the thermal resistance with number of thermal cycles.

sample can be calculated from kcomposite through the equation htot ¼

L kcomposite

(5)

:

As shown in Fig. 3, the total thermal resistance of the sample htot can be expressed as htot ¼ hCu þ hSi þ hTIM ;

(6)

where hCu and hSi are the thermal resistances of the copper and the silicon layer, respectively. hTIM was chosen to express the TIM performance. It depends on the quality of the thermal conduction through the TIM and the quality of the contact between the TIM and the two surfaces.8 From Eqs. 1 to 6, we can deduce hTIM to be: hTIM ¼

L a qcomposite Ccomposite

hCu hSi :

(7)

Fig. 6. SEM image of the interface on the Si side, showing the crack initiated at the solder grain boundary after 15 thermal cycles.

The cross-sectional microstructures were observed by using an FEI Quanta 600 scanning electron microscope (SEM) after various stages of thermal cycles. The sample was clamped by a welldesigned clamp after soldering, and then carefully


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Fig. 7. Cross-sectional SEM images of central part of the interface on the Si side after various stages of thermal cycling: (a) 70 thermal cycles, (b) 120 thermal cycles, (c) 200 thermal cycles, (d) 300 thermal cycles, and (e) 700 thermal cycles.

grinded by 2400-grit silicon carbide paper. After grinding, the sample was rinsed ultrasonically to remove the tiny silicon carbide particles embedded in the solder. After that the sample was polished with a 0.05-lm alumina solution. The samples used for observation of crack propagation were etched using FeCl3 ethanol solution (96 mL ethanol, 2 mL 35% HCl, and 5 g FeCl3). RESULTS AND DISCUSSION Figure 4 shows the change in hTIM after various stages of thermal cycling; every datum point is the

average of three samples. It can be seen that hTIM remained almost constant during the early stage of thermal cycling, but increased notably after 120 cycles. After 200 thermal cycles, hTIM increased linearly with increasing number of thermal cycles. After 700 thermal cycles, hTIM had increased from the initial 0.0258 cm2 K/W to 0.0297 cm2 K/W, about 15%. Figure 5 shows cross-sectional SEM images of the as-reflowed Si/solder/Cu sandwiched sample, where the silicon and copper layers were well bonded and no defects at the Si/solder and Cu/solder interfaces, and in the solder bulk were observed. As shown in

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H.Y. Guo, J.D. Guo, and Shang

Fig. 8. Cross-sectional SEM images near the edge on the Si side of the interface after various stages of thermal cycling: (a) after 70 cycles, (b) after 120 cycles, (c) after 200 cycles, and (d) after 500 cycles.

Fig. 6, cracks initiated at grain boundaries in the solder near the Si side after 15 thermal cycles. Inoue et al.9 also observed that cracks initiated in the area near the Si side when they tested the thermal fatigue life of Sn-Pb solder for die bonding to copper substrate. Moy and Shen10 found that failure of solder joints under shear frequently occurs along a path near and parallel to, but not necessarily exactly at, the interface between the alloy and the bonding material. Figure 7a–e shows in situ SEM images of the central part of the sample after various stages of thermal cycling. It can be seen that the thin discrete cracks had extended in width, but not in length, with continued thermal cycling. After 200 cycles, these discrete cracks connected to each other to form a large crack, leading to the increase of the thermal resistance of the sample. Finally, after 700 cycles of thermal cycling, a continuous large crack formed at the solder surface. With increasing number of thermal cycles, the cracks moved away from the intermetallic compound (IMC) into the solder bulk. This is because the plastic deformation field in the solder was nonuniform when the sample was subjected to thermal cycling. Material elements in the mid-regions of the solder had more freedom to experience rotation while material elements near the interface were

constrained by the rigid silicon.10 Moreover, most of the cracks near the Si side initiated at an angle of 45° to the Si/solder interface. Interestingly, the propagation mode of the cracks near the edge of the sample was somewhat different from that of the cracks near the central part. Figure 8a–d shows SEM images of the edge of the cross-section of the sample after various stages of thermal cycling. Besides the cracks in the solder bulk near the Si side, thin cracks also appeared at the interface, between the IMC layer and the solder bulk, and the cracks in the solder bulk and at the interface connected to each other to form a continuous crack. During subsequent thermal cycling, these cracks propagated along the IMC/solder interface and also grew in width. In the solder bulk near the Cu side, tiny cracks were also observed after 200 thermal cycles (as shown in Fig. 9a and b), which may also contribute to the increase of the thermal resistance. However, the cracks on the Cu side were narrower than those on the Si side. During thermal cycling, thermal stress was generated in the Si/solder/Cu joint due to the difference in the CTE between the Si die, solder, and Cu. Because the difference of the CTE between Si (2.8 ppm/K) and Sn-52In solder (25 ppm/K) is larger than that between Cu (16.8 ppm/K) and Sn-52In,


Fig. 9. SEM image of the crack near the Cu side: (a) after 200 thermal cycles and (b) after 500 thermal cycles.

the thermal stress was concentrated near the interface between the Si and Sn-52In solder. On the other hand, the solder region adjacent to the IMC layer is a weak zone, and cracks tended to initiate in this zone during long-term thermomechanical cycling. Therefore, it is no surprise that the cracks were first observed in the solder bulk near the Si side. On the other hand, because the solder is very soft at high temperatures, the damage should occur mainly as the temperature decreases. Figure 10 shows the forces and moments acting on an elementary section of the sample when the sample was

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cooled down. It can be seen that shear stress would be imposed on the solder because of the CTE difference between the Si and Sn-52In solder, and the maximum tensile stress would be at an angle of 45° to the Si/solder interface. Therefore, most of the cracks near the Si side grew wider along the maximum tensile stress during thermal cycling. According to the analytical and numerical simulation results of He et al.,5 peel and shear stresses of die/ solder interface caused by the CTE mismatch were higher near free edges or corners, which promoted crack initiation at the IMC/solder interface at the edge of the sample. Hutchinson and Suo11 pointed out that a crack in such an interface can either continue to propagate along the interface or deviate into the layer subject to compressive stresses, provided its toughness is lower than that of the interface. So cracks initiated in the IMC/solder interface at the edge of the sample might deviate into the relatively weak solder during thermal cycling. Figure 11a–d shows the change of IMC layer thickness before and after 700 thermal cycles in both the Si/solder and Cu/solder interfaces. The thickness of the IMC layer in the Cu/solder interface grew from the initial 2 lm to about 5 lm after 700 thermal cycles, while the IMC layer in the Si side experienced an immeasurably slow growth, indicating a slower reaction rate of Sn-52In solder with electroless plated Ni-P than copper substrate. Figure 12a–d shows an energy-dispersive x-ray (EDX) spectrum of the IMC layers before and after 700 thermal cycles in both the Si/solder and Cu/solder interfaces. The atomic compositions of the IMC are listed in Table I. An IMC layer of Cu-NiSn-In phase was observed at the Ni-P/solder interface on the Si side after reflow. The Cu atoms were dissolved into and then diffused through the molten solder to form a Cu-Ni-Sn-In phase at the Ni-P/solder interface during reflow, which accelerated the IMC growth rate at the Ni-P/solder interface. The IMC layer at the Cu/solder interface was composed of Cu, Sn, and In after reflow, and a small amount of Ni was also detected after 700 thermal cycles. The increase of IMC layer thickness here is much less compared with the increase in thickness (about 9 lm) by isothermal annealing at 100°C for the same time (about 40 days) as reported by Kim et al.12 However, the growth rate of the IMC at lower temperatures (90°C).12 In our experiments, since the dwell time at the highest temperature was only 10 min during each thermal cycle, the thickness of the IMC layer did not increase much. Moy and Shen10 performed numerical simulations of lap-shear-test solder joints with ‘‘flat’’ and ‘‘nodular’’ types of intermetallic between the copper substrate and the solder; they found that the equivalent plastic strain contour plot pattern was very similar to those in cases without the intermetallic. Considering the relatively thin IMC layer on the Si side, its effect on the crack growth

ACKNOWLEDGEMENTS This work was supported by the National Basic Research Program of China (Grant No. 2004CB619306) and the National Natural Science Foundation of China (Grant No. 50706057). Special thanks are due to John and Jill for improvement of the English. REFERENCES 1. F. Sarvar, D.C. Whalley, and P.P. Conway, Electronics System Integraion Technology conference (Dresden, Germany, 2006), p. 1292. 2. A.S. Fleischer, L.H. Chang, and B.C. Johnson, Microelectron. Reliab. 46, 794 (2004). 3. X.J. Hu, L.N. Jiang, and K.E. Goodson, 20th IEEE SEMITHERM Symposium (2004), p. 98. 4. W.T. Chen and C.W. Nelson, IBM J. Develop. 23, 179 (1979).

2478 5. J. He, W.L. Morris, M.C. Shaw, and N. Sridhar, International Symposium on Microelectronics (1998), p. 583. 6. D.R. Olsen and H.M. Berg, IEEE Trans. Comp. Hybrids Manuf. Technol., CHMT-2, 257 (1979). 7. W.J. Parker, R.J. Jenkins, C.P. Butler, and G.L. Abbott, J. Appl. Phys. 32, 1679 (1961). 8. R. Prasher, Proc. IEEE 94, 1571 (2006). 9. H. Inoue, Y. Kurihara, and H. Hachino, IEEE Trans. Comp. Hybrids. Manuf. Technol., CHMT-9, 190 (1986).

H.Y. Guo, J.D. Guo, and Shang 10. 11. 12. 13.

W.H. Moy and Y.-L. Shen, Microelectron. Reliab. 47, 1300 (2007). J.W. Hutchinson and Z. Suo, Adv. Appl. Mech. 29, 63 (1992). D.-G. Kim and S.-B. Jung, J. Alloy. Compd. 386, 151 (2005). H.P.R. Frederikse, R.J. Fields, and A. Feldman, J. Appl. Phys. 72, 2879 (1992). 14. H.L.J. Pang, K.H. Tan, X.Q. Shi, and Z.P. Wang, Mater. Sci. Eng. 307, 42 (2001). 15. P.L. Hacke, Y. Fahmy, and H. Conrad, J. Electron. Mater. 27, 941 (1998).