limited in electrical performance and/or have had difficulty accessing the interior of the IC. Probing is ...... Top and cross-sectional OM images of CEP on MLC. 62.
IN F O R M A T IO N T O U S E R S
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A COMPARATIVE CHARACTERIZATION ANALYSIS OF VARIOUS PROBING TECHNOLOGIES FOR AREA ARRAY INTEGRATED CIRCUITS
BY
NORMAN J. ARMENDARIZ, B.S.. M.S.
A Dissertation submitted to the Graduate School in partial fulfillment o f the requirements for the Degree Doctor o f Philosophy Interdisciplinary Program
Subjects: Materials Science, Chemical and Electrical Engineering
New Mexico State University Las Cruces, New Mexico May 1997
Copyright 1997 by Norman J. Armendariz
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UMI Number: 9901745
Copyright 1997 by Armendariz, Norman Jesus AH rights reserved.
UMI Microform 9901745 Copyright 1998, by UMI Company. AH rights reserved. This microform edition is protected against unauthorized copying under Title 17, United States Code.
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“A Comparative Characterization Analysis o f Various Probing Technologies for Area Array Integrated Circuits,” a dissertation prepared by Norman J. Armendariz in partial fulfillment of the requirements for the degree, Doctor o f Philosophy, has been approved and accepted by the following:
Timothy J. Pettibone Dean o f the Graduate School
Stuart Munson-McGee Chair o f the Examining Committee
Date
Committee in Charge: Dr. Stuart Munson-McGee, Chair Dr. Cecilio R. Barrera Dr. Jeffrey S. Beasley Dr. Paul M. Furth Dr. Mark M. Montoya
u
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DEDICATION
“Dedicated to those who seek to understand before seeking to be understood, (S. Covey) ”
“para mi madre venada
”
and to my father who embraced and enabled me on this route with involving his life into ours with unconditional support and who was, and will always be with my brothers and me, whenever, and fo r whatever was achieved through our lives that was obtained with honor whether by pen, sword or sweat.
iii
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ACKNOWLEDGEMENTS
SEMATECH Cerprobe Corporation IBM Microelectronics Inc. Micro Substrates Corporation Circuit Components Incorporated New Mexico Space Grant Consortium Society for Hispanic Professional Engineers Lockheed Engineering & Science Corporation National Aeronautics and Space Administration University o f Illinois Materials Research Laboratory New Mexico State University Chemical Engineering Department New Mexico State University Electrical Engineering Department Cerprobe Research and Development and Engineering Departments Society for the Advancement of Chicanos & Native Americans in Science Shin-Etsu, NHK and JSR Special thanks are in order for those individuals who encouraged, supported and contributed to this seven year effort which has culminated in this final dissertation. My advisor Dr. Stuart Munson-McGee and members of the NMSU PhD Committee; Dr. Paul Firth, Dr. Jeff Beasley, Dr. Cecilio Barrera and Dr. Mark Montoya. and Zane Close, Eswar Subramanian, Denny Bates, Dan Higgins, Rick Just, Marcelino Armendariz, Martin Martinez, Gerry Back, Gerald Piper, Tom Montoya, Rey Rincon, Armando Ramos. Norman Greenman, Dr. Ram Panicker, Dr. M. Masyood Akhtar, Dr. Jogender Singh, Dr. Avigdor Zangvil, and Son Dang, whose “surgeon-like” micro-assembly skills checked reality to create the possible from the impossible.
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VITA
April 18, 1960 -- Bom at Pueblo, Colorado, U.S.A. 1983 -- Graduated from the University o f Southern Colorado, Pueblo, CO, Bachelor o f Science in Metallurgical Engineering Technology 1987 — Graduated from the University o f Illinois, Urbana-Champaign, IL, Master o f Science in Metallurgical Engineering 1986-1990 -- Research Metallurgical Engineer, LTV Steel Corp., E. Chicago, IN 1990-1992 -- Senior Test Engineer, Lockheed ESC, Las Cruces, NM 1992-1993 -- Process Development Engineer, Micro Substrates Corp., Tempe, AZ 1993-Present -- Research and Development Engineer, Cerprobe Corp., Tempe, AZ
PROFESSIONAL AND HONORARY SOCIETIES ASM-Intemational -- American Society o f Metals-Materials Information Society SACNAS -- Society for Advancement of Chicanos and Native Americans in Science
PUBLICATIONS Armendariz, N. J., Janoff. D. D., Tapphom, R. M., '‘Spectroscopic Measurement of Temperature and Pressure of Q:." NASA Tech Briefs, Vol. 19, No. 11, November. 1995. Armendariz, N. J., " Failure Mechanisms in Probe Card Materials." Southwest Test Workshop Conference. San Diego, CA, June, 1995 and 1996.
FIELD OF STUDY Major Field: Interdisciplinary- Materials Science, Chemical & Electrical Engineering. V
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ABSTRACT
A COMPARATIVE CHARACTERIZATION ANALYSIS OF VARIOUS PROBING TECHNOLOGIES FOR AREA ARRAY INTEGRATED CIRCUITS
BY NORMAN J. ARMENDARIZ, B.S., M.S.
Doctor of Philosophy, Interdisciplinary Program New Mexico State University Las Cruces, New Mexico, 1997 Dr. Stuart Munson-McGee, Chair
This comparative analysis evaluates various probing technologies and proposes an interconnection technology as a test platform to simulate actual probing conditions for manufacturing and implementing the technologies in cost-effective commercial probe card form, specifically for area array bumped "flip chip" integrated circuits. Integrated circuits (IC) continue to increase in size, density of transistors and increased electrical performance with a corresponding increase in the number of input/outputs requiring connections. The semiconductor industry has responded with area array solder bump interconnection technologies which place the connection points across the entire bottom surface to provide the IC more I/Os and shorter routes vi
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than present peripheral wirebonding to aluminum pads. However, present cantilever and buckling beam probing methods to electrically test “flip chip” die have been limited in electrical performance and/or have had difficulty accessing the interior of the IC. Probing is essentially determined by three (3) first-order factors: electrical resistance of the physical junction between the probe tip and the bump being probed; alignment of the probe to the bump; and the ability to repeatedly perform the former tasks for all pins for every contact made with a bump. These and other requirements are based on SEMATECH specifications desired by major domestic semiconductor manufacturers anticipated test needs into the next century. The test platform or experimental probe card appeared to be a manufacturable and feasible format in terms of providing the probes a method of interconnection from the high density pattern to a low-density tester interface in probe card form. The 40Pb/60Sn deformed less than the 95Pb/5Sn bump composition under similar vertical loads. Each of the probe concepts exhibited a range o f forces and deflection for minimum electrical contact resistances. The concepts which approached the bump vertically required more force (10-12 gms) to minimize electrical resistance as compared to those probe concepts which "scrubbed” or “twisted,” (4-6 gms). Most concepts exhibited limited deflection ranges based on planarity and dimensional data but adequate positional accuracy. Electrical properties, specifically ampacity, were found to be limited in concepts which used a spring component. Two experimental concepts appeared to be competitive to present “buckling beam” probing technologies, if further developed.
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TABLE OF CONTENTS
Chapter
Page LIST OF TA BLES....................................................................................
xiii
LIST OF FIG URES..................................................................................
xv
LIST OF ABBREVIATIONS.................................................................
xxi
1.
INTRODUCTION.....................................................................................
1
2.
INTEGRATED CIRCUIT PRO C ESSES...............................................
6
2.1
Crystal P u lling............................................................................
8
2.2
Wafer S licing................................................................................
8
2.3
Pattern G eneration.......................................................................
8
2.4
Thin Film L ayering.....................................................................
9
2.5
Photoresist C o atin g ......................................................................
9
2.6
Pattern (Mask) D evelopm ent.....................................................
9
2.7
Etching...........................................................................................
10
2.8
Bump Process..............................................................................
11
2.9
Wafer P ro b e..................................................................................
12
2.10
D icing...........................................................................................
13
2.11
Die A ttach.....................................................................................
13
2.12
Encapsulation...............................................................................
13
2.13
Final T e st.......................................................................................
13
2.14
Future T e st....................................................................................
13
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3.
4.
5.
PRESENT AREA ARRAY PROBING TECHNOLOGIES
14
3.1
Epoxy R in g ................................................................
14
3.2
Ceramic B lad e..........................................................
16
3.3
Buckling B ea m ...........................................................
17
3.4
M em brane....................................................................
21
3.5
Experimental Probe Technologies..........................
23
3.5.1
WBP (Wirebond Bump Probe)................
23
3.5.2
MBP (Multi-Bump P robe).......................
24
3.5.3
Elasticon® Probe........................................
27
3.5.4
CBP (Cross Bridge P robe).......................
29
AREA ARRAY PROBING REQUIREMENTS..................
30
4.1
SEM A TECH ...............................................................
30
4.2
Area Array Development O bjective.........................
31
4.3
Area Array Development Strategy...........................
32
4.4
Area Array Test Approach .......................................
32
AREA ARRAY BUMP CHARACTERIZATION...............
JJ
5.1
M icrocharacterization.................................................
33
5.2
Bump Deform ation.....................................................
35
5.3
Finite Element A nalysis.............................................
39
5.4
Bump Dimensional and Positional Accuracy.........
42
ix
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6.
7.
8.
9.
TEST PLA TFO RM ...................................................................................
44
6.1
PCB (Printed Circuit Board).....................................................
46
6.2.
MLC (Multi-layered Ceramic) Holder A ssem bly..................
47
6.3
ISOCON®....................................................................................
48
6.4
MLC (Multi-layered Ceramic) Interposer...............................
55
PROBE CONCEPT DESCRIPTIONS....................................................
59
7.1
SWP (Spring Wire Probe)..........................................................
59
7.2
CEP (Conductive Elastomeric..Probe)......................................
61
7.3
VPP (Vertical Pin Probe)...........................................................
63
7.4
PPP (Plated Platform Probe)......................................................
65
7.5
AWP (Angled Wire Probe)........................................................
66
MECHANICAL CHARACTERIZATION............................................
68
8.1
Cyclic Testing.............................................................................
68
8.2
Force and Deflection...................................................................
70
8.3
Balanced Contact Force............................................................
72
8.4
Radial S crub................................................................................
73
DIMENSIONAL CHARACTERIZATION...........................................
76
9.1
SWP (Spring Wire Probe).........................................................
77
9.2
CEP (Conductive Elastomeric Probe).....................................
78
9.3
VPP (Vertical Pin Probe) ..........................................................
79
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10.
9.4
PPP (Plated Platform P robe).......................................................
80
9.5
AWP (Angled Wire Probe).......................................................
81
9.6
Probe Concept Dimensional and Positional Sum m ary
82
ELECTRICAL CHARACTERIZATION...............................................
86
10.1
Electrical Resistance...................................................................
86
10.1.1
SWP Resistance............................................................
87
10.1.2 CEP Resistance.............................................................
89
10.1.3 VPP Resistance.............................................................
90
10.1.4 PPP Resistance..............................................................
91
10.1.5 AWP Resistance............................................................
92
10.1.6 Probe Electrical Resistance Sum m ary........................
92
10.1.7 Test Platform Component Resistance.........................
94
10.2
Current Carrying Capability .......................................................
95
10.3
Bandw idth.....................................................................................
99
10.4
Current Leakage...........................................................................
101
10.5
Capacitance...................................................................................
102
10.6
C ross-talk......................................................................................
103
10.7
Propagation D elay........................................................................
105
10.8
Im pedance.....................................................................................
106
10.9
Inductance.....................................................................................
107
10.10
B2SPICE Electrical M odel.........................................................
108
xi
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11.
12.
PROBE TO BUMP INTERACTION.....................................................
111
11.1
Contact A re a ................................................................................
111
11.2
Deflection ....................................................................................
116
11.3
Contam ination.............................................................................
120
CONCLUSIONS AND QFD COMPARATIVE A N A LY SIS
123
REFERENCES...........................................................................................................
134
xii
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LIST OF TABLES Page Table 4.1-1
National Semiconductor Technology Probing Roadmap
31
Table 5.2-1
40Pb/60Sn Bump Deformation
37
Table 5.2-2
95Pb/5Sn Bump Deformation
38
Table 5.4-1
40Pb/60Sn Bump Dimensional and Positional Summary
43
Table 6.4-1
MLC Dimensional and Positional Summary
58
Table 7.3-1
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The highest density o f packaged circuits are currently obtained utilizing multichip modules o f flip chips with area array interconnects on multilayered ceramic substrates with a 25% reduction in size and a 22% reduction in weight. In addition to the low profile, small size and footprint, there are other advantages that integrated circuits made in flip chip configurations offers to the semiconductor manufacturer and are listed as follows:
•
Reliability without hermeticity at the chip level has been achieved based on the use o f glass, sputtered S i0 2, C VD oxide or nitride, or polyimide passivation films on the face of the chip.
•
Robust, high strength interconnections between the chip and package for severe mechanical environments of shock and vibration in automotive, aircraft and space applications. Moreover, reliability significantly improved with underfill o f the packaged die.
•
Self alignment of flip chips during reflow soldering as a result o f surface tension forces in liquid solder permits accurate placement with joints made simultaneously in a reflow furnace with assembly yields > 6 a and defects from 0.5 to 3.0 ppm.
3
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•
Superior electrical properties with low capacitance, inductance and resistance exist, due to the short electrical paths enabling future application for high frequency circuitry.
•
Excellent thermal properties, since flip chips are not encapsulated, the semiconductor manufacturer can use the exposed back side of the chip and take advantage o f the silicon’s thermal properties, if configured properly.
However, area array flip chip technology has some limitations. Semiconductor manufacturers have determined some areas where flip chip technology would need to overcome. Some o f the disadvantages or limitations are listed as follows:
•
Commitment to fixed footprints of bump patterns and matching substrates can be constraining with limited availability and cost o f flip chips from semiconductor vendors and immature bump facilities recently coming on-line.
•
CTE mismatch between silicon and substrate causes limitations as thermal cycle fatigue with underfill encapsulation processing appearing as a requirement. Heat dissipation (2.0 watts) is limited in flip chips without thermal enhancements.
•
Alpha particle radiation from ordinary solder can cause soft errors. 4
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•
Inability to optically inspect hidden area array bumps may be a consideration in the quality control of soldered interconnections. However, bump process optimization may eliminate the need for bump inspection.
Moreover, a lack of required manufacturing, handling and specifically testing infrastructures can be significant obstacles for enabling future flip chip acceptance. The present testing or probing technology will not be able to readily physically access high-density (< 150 pm pitch) arrays and high pin-counts (> 2500) o f fully area arrayed bumps and/or perform the desired electrical parameters for wafer-level test. As a result, probing and probe devices for area array tests then become extremely complicated and the problem essentially becomes an issue o f both interconnecting from existing test equipment to an area array pattern and properly probing or interacting with the bumps. Consequently, probing and probe devices for testing area array integrated circuits require an evolution o f present technology or a revolution in new technology. As a result, a comparative study o f various probing technologies is proposed for evaluating and understanding the basic physical, chemical and electrical interactions of novel interconnection and probing concepts with area array or “bumped” integrated circuits. Probing is considered critical to enabling the semiconductor industry’s thrust towards area array manufacturing technologies and ensure that testing does not become the limiting technology.
5
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2.
INTEGRATED CIRCUIT PROCESSES
The global prevalence o f computers and information processing is a direct result of the widespread availability of the integrated circuits contained on small “chips” or die of semiconductor material, silicon or gallium arsenide. Silicon, (Si) the element, is most commonly used because it is a natural semiconductor. In other words, unlike insulators such as glass or conductors such as copper, silicon can be altered to be between a conductor or insulator, hence the term semiconductor. The critical point in the evolution of contemporary electronics was the joining or “integration” of individual resistors, capacitors and transistors on the surface of the semiconductor silicon. Before the invention o f the integrated circuit in 1959, each component of an electronic circuit had to be manufactured individually and then wired together. In an integrated circuit or IC, the individual components exist, but rather than appearing as discrete components, they are formed in or deposited on the silicon and are connected by deposited metal layers. As a result, ICs made electronics cheaper, more versatile, smaller, more reliable and with less distance for electrical currents to travel and thus many times faster. Today's most advanced chips each hold many hundreds of thousands of components. However, fabricating a chip layer by layer involves very precise photo-engraving on the order o f 0.3 pm or 4/100000 of an inch.
6
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Integrated circuit manufacturing is a meticulous and painstaking process, described in part in Figure 2-1 and in the following individual sections. It has created an entire new industry, projected to more than double annual worldwide revenues from $150 billion to an excess o f $310 billion by the year 2000.1 By that time, the electronics business as a whole, built on a chip foundation, will be by far, the largest industry in the world and usher in the “electronic age.”
INTEGRATED CIRCUIT MANUFACTURING SEQ UENCE Implant
Silicon Ingot
Oxidation Fumac*
Oxidation
LPCVO
Fumac*
Fumac*
n r n Wafer* Enhancement
Threshold Mask 2
Implant
Source/Drsln Photolithography
Active Area initial Oxidation Photolithography Diffusion Furnace
Qata oxide
Masks
Poty OepoaHlon Sputterer
Etch Contacts
Contact Source/Drain Photolithography Anneal
Metal Deposition
Mask 4 Deposit Mask 5 Protective -► Bonding Pad Passivation Photolltho*aphy
■*
Final Wafer _________ Acceptance Teat Wafer Probe
Metal Photolithography
y r
01* Separation
Bond
Complete Assembly and Test ma
Figure 2-1 shows the principle steps in the making of an integrated circuit Source I.C.E.
7
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2.1 Crystal Pulling In order to make ICs or chips, a batch processing system based on multiple chip fabrication on a silicon substrate or “wafer” is the cost-effective process vehicle. To make wafers, silicon is chemically processed so that it becomes 99.999999% pure. The purified silicon is melted and grown into long, cylindrical “ingots.” Atoms o f high-purity molten silicon attach to a small seed crystal, forming a single crystal ingot.
2.2 Wafer Slicing The ingots are sliced into thin wafers o f uniform thickness by lapping and then are polished until they have flawless, mirror-smooth surfaces. Numerous technologies to ensure that the wafers are planar and defect free have required parallel development o f new chemical and physical etching processes as well as profiling inspection techniques.
2.3 Pattern Generation An enlarged layout of the integrated circuit components and interconnections for every fabrication step is generated at a computer-aided design (CAD) terminal. A pattern for each layer is duplicated on a glass photomask or reticle by an electron beam generator. The routing o f the interconnections are either laid-out to peripheral aluminum pads or area array solder bumps.
8
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2.4 Thin Film Layering Individual circuit components and their interconnections are formed in thin layers of material on or in the wafer. Complex integrated circuits may require as many as 20 layers. Thin film layering begins by forming an epitaxial layer. This is a thin layer o f silicon with different electrical characteristics than the underlying wafer. It is deposited on the wafer surface at high temperatures to form thin, uniform layers of S i02. This insulative layer is "grown” on top of a polished silicon wafer. Next, is chemical vapor deposition, where insulating or conductive layers are deposited on the wafer surface via chemical reaction or electrical discharge. Sputtering metal layers for contacts and interconnections are then deposited onto the wafer according to the particular bumping method employed to complete the process.
2.5 Photoresist Coating A photo-sensitive material (photoresist) is spread evenly over the wafer surface. It will be used for the transfer o f layer patterns to the wafer, which becomes soluble when exposed to ultra-violet light (UV).
2.6 Pattern (Mask) Development Multiple patterns are transferred from the reticle to the coated wafer by a wafer stepper. Patterns or masks that were created during the design phase are used to define the circuit pattern on each layer o f a chip. The mask is placed over the
9
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photoresist layer. UV light shines through the clear spaces in the mask, exposing portions of the photoresist. The portions of the photoresist exposed to UV light then become soluble. The exposed pattern is '‘developed” in a chemical solution which removes the soluble portion, then “baked” leaving only the transferred pattern.
2.7 Etching Reactive gases etch away the exposed areas to create a dimensional pattern on the wafer surface. When the exposed portions o f photoresist are removed, a portion o f the silicon dioxide layer underneath is revealed and then etched away. The remaining photoresist is removed, leaving a pattern of silicon dioxide on the silicon wafer. During "doping,” the exposed areas o f the silicon wafer are bombarded with various chemical impurities called ions, thereby altering the way the silicon in these areas conducts electricity. This patterning process is repeated for each layer with additional materials such as polysilicon, which conducts electricity, and are deposited on the wafer through further masking and etching steps. Each layer of material has a unique pattern. Together, they will form the chip’s circuitry in a 3-dimensional structure. To provide a link to the additional layers put on the wafer, “windows” are formed by repeating masking and etching steps. Aluminum is applied to fill the “windows” forming electrical connections between the chip’s layers. Among the many reasons A1 is chosen for this application is that it makes good electrical contacts to silicon and also bonds to silicon oxides.
10
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2.8 Bump Process If a “flip chip” format is the selected method for subsequent connection, then the aluminum pad requires further processing depending on the particular bump manufacturing method. For example, the IBM C4 (controlled collapse chip connection) process requires a sputter clean to prepare the final aluminum (Al) metal. Chrome (Cr) is deposited as a barrier and adhesion promoter to the Al and polyimide. Next, copper (Cu) and Cr are co-deposited as the primary wetting surface for the bump. This is followed by a flash of gold (Au) to inhibit copper oxidation. With the IBM process, an evaporated shadow or bump mask is used to define the solder bumps. Once the bumps are deposited, first with lead (Pb) then with tin (Sn), the mask is removed with the bump resembling a truncated cone. Subsequently, a non oxidizing reflow process performed above the bump liquidus temperature yields the final and round C4 bump, Figure 2.8-1.
C r/C u
P o ly im id e / P a ssiv a tio n
A fte r R e flo w
Figure 2.8-1 shows an example of the pad limiting and connection metals after evaporative deposition (L) and the resulting bump profile after reflow (R).
II
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2.9 Wafer Probe A completed wafer contains hundreds o f chips, each of which may contain millions o f transistors. Each of the chips on a wafer needs to be tested to determine if the processing indeed was performed properly and that the function o f the chip has been realized. To initially screen-out the good chips from the bad chips prior to chip (die) separation or wafer dicing, testing begins with wafer level probing with each IC on the wafer electrically tested and characterized in a test system as shown in the following Figure 2.9-1.
ROBER
ROBE CARD
Figure 2.9-1 shows the three (3) major pieces o f equipment used for present area array waferlevel testing, a probe card, a prober and tester. Source Electroglas.3
12
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2.10 Dicing The wafer is diced into separate chips with a precision diamond saw.
2.11 Die Attach Individual chips are mounted in a suitable package and fine wires or solder bumps connect each to leads or pads in the package.
2.12 Encapsulation The package is sealed for mechanical and environmental protection.
2.13 Final Test Packaged chips are functionally tested for electrical performance.
2.14 Future Test The integrated circuit process becomes more complicated as the variety o f the devices and applications require cost-effective and yet reliable dice. Testing becomes a limiting process and attempts to eliminate testing based on process optimization or built-in-self-testing would nevertheless require some verification and would also drive testing from the individual die packaged level to the wafer-level and which would mostly likely require a “whole'’ wafer-level test approach with the capability o f testing more parameters and at a range o f temperatures, e.g., from -55 to 200 °C.
13
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3.
PRESENT AREA ARRAY PROBING TECHNOLOGIES
3.1 Epoxy Ring Present semiconductor testing devices are mostly designed for periphery probing (2-3 rows deep) of aluminum pads down to a pitch o f about 3 mils (75 pm). Metal wire probes (W, Be/Cu, etc.), bent at the tip, are used as the probing feature to interface and make the mechanical and electrical contact with the pad of the device under test (DUT). This technology has also been utilized for probing bumped dice (C4, 40Pb/60Sn and Au bumps) and up to 5-6 peripheral rows o f an array are presently being tested successfully using this technology,4 Figure 3.1-1.
Figure 3.1-1 shows a conventional cantilever epoxy-ring probe device for area array applications under construction using probe wires which could fully access 6 rows into the DUT to probe bumps spaced approximately 9.8 mils (250 pm) apart.
When a probe card is required, the customer provides the coordinates of the bonding pads or a wafer to generate a layout diagram and a template. The template is used to build a probe-ring assembly. Probe needles are placed in the template, 14
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oriented from the device pad to the ATE (automated test equipment) channel on the probe card. A ceramic or anodized-aluminum support ring is then bonded to the needles with a ceramic-based adhesive. After curing, the probe-ring assembly is mounted and soldered to the printed circuit board. The probe wires are then planarized with respect to each other, and the contact force o f each probe tip is measured to insure it is relatively the same for all probes in a given probe card. The combination of the flexing o f the probe at the bend and at the point of attachment to the ring gives each probe “independent suspension,” thus ensuring that any small differences in height between the probe tips and between the pads are accommodated. Alignment to the die pattern is accomplished by visual means since the probe tips can be viewed straight through the PCB. Electrical contact is assured when the probe tip is moved across the pad surface “scrubbing” or breaking any non-conductive surface, e.g., oxide or “dirt,” Figure 3.1-2.
Figure 3.1-2 shows the variety of custom probe cards utilizing epoxy-ring and blade technologies (L), and a high-density, high-pin-count epoxy ring card, with >700 pins and a pitch 0175 pm (R). S o u rc e C e rp ro b e . 15
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3.2 Ceramic Blade Blade probe cards, primarily alum ina ceramic, have been a long standing performer for lower density, low leakage applications. Ceramic-blade probe cards offer stability at high temperatures with easy repairability. Applications o f low current measurements for process control probing in the sub- picoamp range utilize this technology. For very high-frequency testing of GaAs ICs and other high speed devices, microstrip blades have been developed. These blades feature a controlledimpedance strip bonded to the ceramic substrate which carries the signal directly from the tips o f the needles to the test system interface. The probe is either brazed or soldered to the metallized ceramic blade, depending on the probe type required (W, BeCu or W/Pd). The probe is then bent to the appropriate probe angle and planarized to the required tip diameter before aligning to the DUT pattern and soldering to the printed circuit board, Figure 3.2-1.
Figure 3.2-1 shows the variety ofceram ic blades presently manufactured for specific applications (L) and a completed ceramic blade probe card for high-frequency applications (R). S o u rc e C e r p r o b e .5 16
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3 J Buckling Beam The Cobra® probe, which was developed by IBM Research about 20 years ago to probe C4 technology (which was also developed by IBM) is still the major domestic area array probing technology used. The contacts or probes employ the principle of a buckling column whereby the application o f a force beyond a critical value causes buckling to occur. Figure 3.3.1(L). The force/deflection profile o f a buckling beam is characterized by an initial increase in force followed by a constant force across the remaining deflection, which is about 100-125 pm, Figure 3.3-1(R). The contact is made to a pad where the tail of the probe wipes (or scrubs). The “fan-out” to the PCB is made through coaxial wires as the space transformer, Figure 3.3-2. The probes are usually made o f Paliney-7 and coated with insulating parylene with swaged and slightly pre-bent (pre-buckle) features to provide vertical retention, Figures 3.3-3 and 3.3-4. ■o
rce
FO R C E
DISPLACEMENT
////777
d is p l a c e m e n t b u c k l in g
beam
C O M P R E S S IO N
S P R IN G
Figure 33-1 shows a drawing of the Cobra9 buckling beam working principle (L) and the force deflection profiles o f a buckling beam and spring, which is similar to a cantilever profile (R). S o u rc e F e in m e ta ll.6 17
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TESTER LQ*G 80DR3
CWTACTS
WIRES 1 million touchdowns while maintaining the ability to meet the electrical and physical specifications. Reliability. > 500,000 touchdowns M TBF (mean time between failure) when complying with clean and P M (preventive maintenance) specifications. A failure is defined as any instance o f a probe not meeting the electrical or physical specifications.
The mechanical characterization of the probe concepts primarily focused in four (4) areas considered critical to meeting the lifetime, reliability and physical probing requirements for area array probing. The mechanical characterization studies include: cyclic (fatigue), force (load) versus deflection (compression), balanced contact force (BCF), and radial scrub. Each o f probe concepts were evaluated for mechanical properties, primarily force versus deflection when mounted in complete array form on an MLC. Limited cyclic (fatigue) testing was performed on individual SWP and PPP concepts and only the VPP was measured for BCF (balanced contact force) in complete array form. In addition, an analysis o f the radial scrub expected for the VPP concept was also performed.
8.1 Cyclic Testing Lifetime testing was not performed on any bumped wafers; however, cyclic or fatigue testing was performed on two (2) concepts, PPP and SWP (W-filament based). The PPP survived approximately 185,000 cycles before failing at the platform/post interface at a constant deflection o f 0.0005 inches.
68
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SWPs were built on MLC mechanicals and processed with a hard (Shore 80) Agepoxy base covered with an additional layer of transparent silicone elastomeric encapsulation of Sylgard 184 . In addition, the spring was capped with the same Agepoxy used for the base attachment. Each SWP was force/deflection tested and one SWP was isolated electrically to determine when a failure occurred during test in the cycling machine using a WC (tungsten carbide) flattened stylus. The SWP was cycled within a constant 0.003 inches stroke on a continuous basis and interrupted at 500 and 3,000 K-cycles to measure the force and deflection. The SWP exhibited a load drop after 500 and 3,000 K-cycles from about 8 to 7 gms and from 8 to 5 gms, respectively. The test was terminated after 3,300 K-cycles and the Ag-epoxy appeared to have worn through (about 0.001 inches) with a section of the W material o f the spring exposed, Figure 8.1-1.
ISWPW a
3000K CYCLES
200 O B=LB7nO N (m iU |
Figure 8.1-1 shows the force vs. deflection profile of the SWPW at §00 and 3,000K-cycles under a deflection of upto 3.0 mils (L) and the top o f SWPW’s Ag-epoxy cap exposed (R).
69
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8.2 Force and Deflection SEMATECH Specification: Force. The probe contact force must be uniform, varying AA02- PROBE CONTACT OAJ4ET®
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Figure 9.2-3 shows the CEP diameter (L) and height (R). 78
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300
350
9 3 VPP (Vertical Pin Probe) Dimensional Characteristics
Figure 9.3-1 shows a top view (L) and angled view (R) o f the VPP as built on the 250 pm array.
VPPAA02-POSITIONAL ACCURACY
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Figure 9.3-2 shows the VPP position on the array grid (L) and distance from true position (R).
VPPAA02 PROBE HT. (From MLC S u rfic a )
VPPAA01 PROBE CONTACT DIAMETER 02
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N N «N eN PROSE NUMBB l
PROSE NUMBS*
Figure 93-3 shows the VPP diameter (L) and height from MLC surface (R).
79
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9.4 PPP (Plated Platform Probe) Dimensional Characteristics
Figure 9.4-1 shows a top view (L) and the area o f detail o f three (3) interconnected PPPs (R).
PPPAAOI-POSmCNAL ACCURACY (RJ
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PPPAA01-PROBE CONTACT DIAMETER
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Figure 10.1.3-2 shows the deflection vs. force & resistance profiles for the VPP (L) measured on a bumped stylus as compared to Paliney-7®, which was measured on a bumped wafer (R).
10.1.4
PPP Resistance
The DC electrical measurement o f the PPP concept was performed with the same experimental set-up used for the SWP concepts, but with only the PPP platform (not the post section) soldered to the Au-stylus as shown in Figure 10.1.4-1. Also, the platform extended slightly less beyond the stylus than when actually manufactured.
02
03
O aftectJon ( m ilt)
Figure 10.1.4-1 shows a side-view of the single PPP platform attached to the stylus without the Ni-post (L) and the corresponding deflection vs. force & resistance profiles (R). 91
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10.1.5
AWP Resistance
The DC electrical measurement o f the AWP concept was performed with the same experimental set-up used for the SWP concepts, with only six (6) filaments surrounded by the elastomer simulating the probe contact and secured to the Austylus with a similar silicone elastomer, Figure 10.1.5-1.
DafUctlon va. Fore* & R*4«anca-A W P
Figure 10.1.5-1 shows a top view o f the AWP Au filaments contact surfaces measured (L) and the corresponding deflection vs. force & resistance profiles (R).
10.1.6 Probe Electrical Resistance Summary Table 10.1.6-1 summarizes the force and deflection required for the various probe concept configurations to achieve a minimum or stable electrical resistance on a bumped wafer or stylus. In addition to the resistance obtained, the contact resistance, which is defined as the difference between what was measured on the solder bumps and Au-platen is also listed to compare the effects of the DUT surface shape and composition on the resistance at the critical probe/bump interface. Figures 10.1.6-1 and 10.1.6-2. 92
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Table 10,1.6-1 PROBE PAL-7 W SWPWX AWP PPP VPP CEP SWPFe20 SWPWXO AgEPXY SWPW2
Force and Deflection Required for Minimum Resistance
Deflection (mils) 0.05 0 .0 1 1.75 2.73 0.23 2.20 6.45 3.03 2.29 0.12 3.58
Force (gms) 10.35 12.07 3.04 3.24 4.54 7.5 12.74 11.78 8.59 10.70 5.08
Resistance(Ohms) 1.66 1.85 2.1 2.25 2.37 2.40 2.73 2.74 2.83 2.90 6.95
Contact Res.(Ohms) 1.48 1.71 0.99 0.97 2.25 0.20 1.53 1.71 1.63 0.40 5.06
Figure 10.1.6-1 shows the probe deflection (L) and force (R) required for minimum contact resistance on 40/60 bumps (ranked in increasing order).
70
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250 mA with no discernible decrease in force (mechanical strength) detected. The ampacity o f concepts utilizing Au-coated Fe springs (VPP, SWPFe) or Ni/Aucoated W filaments (SWPWX) exhibited relatively low values with increased resistances and a significant decrease in mechanical strength below the 250 mA cun-ent specification. However, the SWP concepts which were CEP-filled (SCP) or wire-core filled (SWF) showed higher ampacity levels with lower and constant resistances and relatively constant mechanical strength above 250 mA o f current.
•
The AC bandwidth o f the SWP and VPP ranged from 1.5 to 1.8 Hz and the AWP, CEP and PPP bandwidth ranged from 4.8 to 6.6 GHz as-attached to the MLC. The probe bandwidth appears to be dependent on the probe resistance and distance the probe is from the MLC surface.
•
The PCB and the MLC bandwidths were 2.8 and 6.7 GHz, respectively. Although an entire probe card was not measured, the bandwidth may be limited more by the FR-4 (fiber-reinforced epoxy) construction of the PCB and may have detrimentally affected all probe concept bandwidths. Moreover, other studies have shown that alternate materials such as cyanate-ester would most likely improve this property.32
126
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•
The AC maximum impedance was greatest for the SWP (75 Q), VPP (126 Q) and PPP (126 Q) concepts and less for the CEP (57 Q) and AWP (61 Q) concepts. It appears that the impedance was affected by the relatively long length of uncontrolled impedance traces (VPP) and the close proximity o f the probes (PPP platforms) to each other which in effect may have behaved similar to an antenna.
A QFD comparative analysis was performed to systematically determine how each o f the probe concepts performed with respect to each other based on the test results with respect to present requirements and possibly provide the foresight to determine which concepts may offer the most potential for future area array applications. In other words, this comparative analysis attempts to critically evaluate the relationship between what is important and what areas require further improvement. QFD was initially developed in Japan to get engineers to consider quality early in the design process. It started in the Kobe shipyards as a way to view quality as taught by Deming and others and has since expanded into the automotive and semiconductor industry.3j In addition to the probe concepts evaluated in this study, the present buckiing-beam or Cobra probe (CBR) is included in the comparative analysis although only limited testing was performed since it was not readily available. However, vendor data and user input provided a basis for the comparison as the benchmark to evaluate the experimental concepts.
127
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Figure 12-1 shows the partial QFD analysis report chart. Each o f the probe concepts (HOWs) was graded in terms o f performance to each of the twenty (20) major parameters (WHATs) considered critical for area array probing and are listed to the left. Three (3) grades comprise the probe parameter performance scale; 3. 6 and 9, with 9 meeting or exceeding the requirement. Moreover, each parameter is assigned a weight or importance (WHYs) listed on the right from 1 to 5, with 5 being the most important (must have) characteristic. The combined relationship between each probe concept parameter performance and level o f importance (WHATs vs. HOWs) is totaled at the bottom with a bar chart comparing each probe concepts overall performance. In addition, the performance and importance of each parameter (WHATs vs. WHYs) is listed at the right with each parameter totaled and accompanied with a bar chart. In other words, this column indicates the degree to which each parameter was addressed by all probe concepts. The QFD comparative analysis shows that no one concept resulted as the overwhelming clear solution, with each concept exhibiting advantages or disadvantages when compared to each other. No concept fully addressed all requirements. However, based on the current available data and acknowledging that lifetime and contamination testing results have yet to be concluded, the Cobra and AWP followed by the VPP and SWP concepts, appear to be the probing technologies most applicable for near-term and prototype area array probing development.
128
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P 3 C 5 E CONCEPTS (HOWs) WHATs vs HOWs Legend
Moderate
C ontact Arec Positional Accuracy Ciometer Precision Deflection Planarity Force 9CF Low Resistance low
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Figure 12-1 QFD (quality for function deployment) comparative analysis.
129
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In order to better understand which probe concepts show the most promise for future area array probing and in overcoming the limitations observed in this study without further significant development, each o f probe technologies current weaknesses, strengths and areas for improvement are listed in Table 12-1 for comparison and are discussed in the order o f the previous QFD ranking.
Table 12-1
Probe Concept Areas For Development
PROBE
CURRENT STR E N G TH S
CBR
Domestic (High cost), off-lh eshelf) scaleable to 150pm . Ampacity. Large deflection. Constant force vs. deflection. Modular. Durable
High cost. Low BW (continuous wired space transformer). High force. Large planarity. Large force distribution (High BCF). Bump deformation. Contamination?
Coaxial wire or MLC space transformer. Planarity. Tighter geometric tolerances, alternate materials or pin d esign . Cleaning methods?
AWP
Low c o s t Good electrical. Low force. Minimum Bump deformation
Foreign. Low deflection, positional accuracy dependent on density, Scaleable to 250 pm . Alignm ent? Contamination? Durability?
Wire-materials. density, positional accuracy, cum ulative load platform, stepped surface features. Elasticon? Alignment & C leaning methods (adhesive block)?
VPP
Off-the-shelf, scaleable to 200pm . Large deflection. Constant force vs. deflection. Low Resistance, Position accuracy. Modular
Foreign. High c o s t Low am pacity. High force. Large force distribution (High BCF). Low BW . Planarity, High X-T. High Z. Contamination? Durability?
Planarity, Spring materials (SW F. double pitch, fewer coils). Cleaning methods?
SWP
Domestic. Low Cost. Repairable. Medium fo r c e . Medium deflection. Scaleable to 200pm . Low fatigue. Position accuracy
Low ampacity. Low BW , H igh X-T. High Z. High resistance. Planarity. Surface wear. Contamination? Durability?
Spring materials. Surface modification. Planarity. WBP extended wire. W N i/A u Plating.. Cumulative load platform. VPP double pitch. C leaning methods?
CEP
Good electrical. Positional accuracy. Planarity. Scaleable to 150pm.
Foreign. High C o s t N on robust contact surface. Low deflection. High force. Contamination? Durability?
Surface m odification, alternate panicle arrangement or elastom er configuration. Cum ulative load platform. C leaning methods (adhesive block)?
PPP
Domestic (Low Cost). Low resistance. High am pacity. High BW, Low force. Robust contact area
Low deflection. Scaleable to 250pm . Fatigue. High X -T. High Z. Contamination? Durability?
Photoresist, alternate platform metallurgy. Design (ven ical. stacked platforms), cum ulative load platform, underfill. Cleaning methods?
CURRENT W EAK NESS
IM P R O V E M E N T S?
Foreign or off-shore technologies are considered a weakness (although in some cases it may be the low cost provider) with the domestic technologies considered easier to address customer requirements and further developed if manufactured on130
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site, without incurring encumbering licensing agreements or relatively longer design cycles and product delivery schedules. Obviously, the Cobra has been the industry workhorse for > 20 years and has a proven test capability which may be extended with enhanced manufacturing methods to reduce cost and improve mechanical and electrical performance in terms o f tighter pitch, bump deformation, bandwidth and impedance control with possibly incorporating an MLC instead of the continuous wire as a space transformer or interposer with further design and development required. In addition, the Cobra® may provide interim probing solutions for probing flat pads prior to bump processing. The experimental AWP concept showed excellent electrical properties, but appeared limited in mechanical properties, e.g., deflection and may have contamination, wear and fine-pitch limitations (positional accuracy). However, if deflection can be improved, increased filament density achieved and precise surface features such as “steps” incorporated into the elastomer, then the potential exists for its applicability to both array bumps and possibly aluminum pads. The VPP (off the shelf) concept which is considered to be very Cobra -like in approach also showed promise in terms of its manufacturability and mechanical properties and “robust” design; however, the ampacity and bandwidth would need to be addressed. Possibly, an SWP with increased ampacity capability (SWF) may be incorporated into the VPP, instead of the present piano wire spring for the compliant component.
131
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The experimental SWP concept, in particular the SWF attached to a WBP with an extended wire section located within the spring inner-core, appeared to offer the most potential for further SWP prototype array probing development. Although the ampacity and bandwidth would most likely need further study and enhancement, the SWP offers a manufacturable solution that would most likely meet most mechanical and electrical requirements for 250 to 200 pm pitch arrayed bumped features, if given a serious development effort. The experimental CEP concept exhibited manufacturability, but marginal electrical properties and limited mechanical properties. Cost, contamination and wear are also a concern. However, this probe concept may be better suited for second-level type connections similar to ISOCON® applications. The experimental PPP concept showed manufacturability and mixed electrical properties (low BW and resistance but high cross-talk and impedance), and limited mechanical properties, e.g., deflection, fatigue. Contamination and fine-pitch applications were also o f concern. However, this technology may show promise as an interconnection technology to other probe concepts or for other low-density bump or pad interconnection applications, e.g., contactor sets, BGA test sockets. An MLC or MLL (multi-layered laminate) die package used by the customer appears to be the optimum interconnect method for electrically and physically connecting to the DUT, with alternate HTCC (high temperature co-fired ceramic) MLCs most likely meeting the requirements. Although the present test platform is
132
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considered static, a platform (substrate) which is allowed to move may improve the net deflection of an array o f probes by cumulative loading. In summary, the modular construction of the platform lends itself to present Cobra®-type and VPP assemblies as well as experimental probe concepts such as the AWP or SWP for further evaluation. In other words, a production-type area array card mounted with a Cobra®type or enhanced VPP probe head would provide an interim or short-term solution, while developing in parallel an experimental AWP, SWP or probe concept yet to be conceived for future applications. This approach becomes more feasible in terms o f development, manufacturability and time to market and thus not only be costeffective but result in a test-effective solution for future area array test applications.
133
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REFERENCES
1-
Yager. G., "Direct Chip Attach Appears Most Effective." Electronic Engineering Times, pg. 58. June 1996.
2-
I.C.E.. Integrated Circuit Engineering Corp.. "Basic Integrated Circuit Technology." Scottsdale. AZ. Jan. 1995.
3-
Electroglas. Inc.. product brochure. "Automatic Wafer Probing Systems." Santa Clara. CA, May 1996.
4-
Nelson. R.and Subramanian. E.. " Enhanced Probe Card Facilitates At-Speed Probing Applications." International Test Conference Proceedings, v. 43.2. pg. 936. Oct. 1992.
5-
Cerprobe Corp.. product brochure. "Cerprobe Knowledge. Innovation, and Performance." Tempe. AZ. May 1995.
6-
FeinmetaH Gmbh. product brochure. " SiProbe Silicon Probe Cards." Contact Technologies. Inc.. Newbury Park. CA. May 1995.
7-
Upsys Reseau Eurisys. product brochure. "Cobra Probe. Advanced Test Probe Technology ." Cerprobe Corp.. Tempe. AZ, June 1995.
8-
Zimmermann. K.. "SiProbe-A New Technology' for Wafer Probing." International Test Conference Proceedings. IEEE 0-7803-2991. pg. 106. May 1995.
9-
Roark. R.. and Young. W.. " Formulas for Stress and Strain." McGrayv-Hill. NY. 1975.
10- Dax. M.. " Active Substrate Membrane Probe Card." Semiconductor International. Inspection. Measurement and Test. Pg. 56. May 1996. 11- Packard-FIughes Interconnect, product brochure, "Gold Dot™ Technology. High Performance Electronic Interconnections." Irvine. CA. June 1995.
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12- Eldring, J.. and Marrs. R., "Flip Chip Attachment of Silicon Devices Using Substarte Ball Bumping and the Technology Evaluation on Test Assemblies for 20 Gbits Transmission." Electronic and Components Technology Conference. May 1995. 13- Shih. D. Y.. "New Ball Grid Array Module Test Sockets." Electronic Components and Technology Conference Proceedings. IEEE-07803-3286, pg. 467. July 1996. 14- Hirano. T.. ” Silicon Microprobing Array for Testing and Bum-In." Electronic Components and Technology Conference. IEEE-0-8186-6560. pg. 89-94. July 1994. 15- SEMATECH development agreement No. 35070300. "Array Probe Technology" confidential. May 1995. 16- Bhatti, P.. and Gschwend. K.. "Three-Dimensional Creep Analysis of Solder Joints in Surface Mount Devices." Transactions of ASME. v. 117. pg. 20. Mar. 1995. 17- Smith. J.. IEEE Transactions on Components. Hybrids and Manufacturing Technology , v. 11. no. 4. Dec. 1988. 18- Lau. J.. "Bending and Twisting of 60Sn40Pb Solder Interconnects with Creep." Journal of Electronic Packaging-Technical Briefs, v. 116. pg. 154. June 1994. 19- Gen in. D.. and Wurster. M.. " Probing Considerations in C-4 Testing o f IC Wafers." International Conference Multichip Modules Proceedings, pg 124. Nov. 1992. 20- CCI-Circuit Components Inc.. product brochure and data sheet. “ISOCON Interconnections." No. 0293-004. Tempe. AZ. Feb. 1993. 21- Sergent. J.. "Materials for Multichip Modules." Electronic Packaging & Production, pg. 28. Dec. 1996. 22- J. M. Nev Co.. product brochure."Nev. Capabilities and Processes." Bloomfield. CT. Dec. 1994. 23. Tuma. J.. "Engineering Mathematics Handbook." 2nd Ed.. McGraw-Hill. NY. 1979. 135
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
24- Vladimirescu. A., and Zhang, K... “SPICE Version 2G User's Guide. ~Dept, of Electrical Engineering and Computer Science, University of California. Berkeley. CA. Aug. 1981 25- Eldnng. J.. and Seo. S.. “Application o f Alternative Bumping And Flip Chip Technique for SuperBGA^.'' International Flip Chip, BGA. TAB and Advanced Packaging Symposium™, Feb. 1995. 26- Dietz. J.. and DeHaven. K... Motorola C4 Product Design Manual. "Chip and Wafer Design." MMTG. v. 1. issue A. May 1996. 27- Nelson. J.. and Nowak. M.. "C4 Packaging for CMOS ASICs. " Surface Mount International, pg. 8-13. June 1995. 28- Landzberg. A., and Norris, K... “Reliability o f Controlled Collapse Interconnects. ' IBM Journal o f R&D, v. 13. pg. 266-271. Feb. 1969. 29- Tuckerman. D.. "A Cost Effective Wafer-Level Bum-In Technology." Multichip Module Conference Proceedings, pg. 34-40. April 1994. 30- Joint Industry' Standard. J-STD-012. " Implementation of Flip Chip and Chip Scale Technology." Surface Mount Council. Jan. 1996. 31- Rymaszewski. E.. and Tummala. R.. “Microelectronics Packaging Handbook. ' Van Nostrand Reinhold. pg. 366-391. May 1992. 32- Higgins. D.. and Armendariz. N.. " PCB Materials Study." SEMATECH Report No. 11. Austin, TX. Sep. 1996. 33- ITE-lntemational TechneGroup Incorporated. “QFD, CAPTURE Windows Version User's Reference." Milford. OH. June 1992.
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