thin-film capacitors as synapses in integrated circuit implementation of artificial netlral networks is described. A continuous-valued synapse (analog memory) ...
INTEGRATED CIRCUIT NEURAL NETWORKS USING FERROELECTRIC ANALOG MEMORY LAWRENCE T. CLARK, ROBERT 0. GRONDIN, and SANDWIP K. DEY* Centerfor Solid-state Electronics Research *Dept. of Chemical,Bio & Materials Engineering Arizona State University, Tempe, Az., 85287 ,4 B S T R A C T The application of ferroelectric thin-film capacitors a s synapses in integrated circuit implementation of artificial netlral A continuous-valued networks is described. synapse (analog memory) where the synaptic efficacy is controlled by the polarization of a ferroelectric capacitor element is presented. In contrast t o non-volatile ferroelectric RAM applications, the ferroelectric analog synapse utilizes non-destructive readout. A ferroelectric capacitor circuit model has been added to the SPICE circuit simulation program and is complete with respect to current vs. time, polarization, and The simulated current vs. voltage responses. response in characterization circuits is shown to closely model that of PZT thin-film capacitors produced in our lab. Simulation and experimental results a r e presented which demonstrate the proposed synapse circuit to possess a number of favorable characteristics, including very infrequent refresh and fine programming granularity.
I. INTRODUCTION Artificial neural networks (ANN'S)promise the solution of problems which have heretofore proven difficult using conventional computers, by employing many simple computational elements working in parallel to arrive at a solution. Such neuromorphic computation may allow the solution of problems involving multiple simultaneous constraints, which humans solve naturally and easily, but which pose significant difficulties to conventional computers. Examples of this sort of task are pattern recognition, vision, and associative memory. Currently, ANN'S are typically software programs running on conventional computers,where they lose their advantages of massive parallelism and functional simplicity. Consequently, to realize the full potential of this computational paradigm, i.e., solutions in real-time, hardware implementation is necessary. Where size, weight, and power dissipation are important, integrated circuit (IC) implementation is desirable. The development of high density, programmable electrical synapses is requisite to the construction of integrated circuits which implement artificial neural networks directly as analog circuits. Such circuits utilizing a number of IC memory technologies including static RAM [I], dynamic
analog charge storage [2],read-only resistive connections [3], and EEPROM [4], have been fabricated. These approaches meet the requirements of small size, programming granularity and accuracy. and non-volatility to varying degrees. The use of ferroelectric thin-films in integrated circuit synapse circuits will be described. An analog memory element employing electrical non-destructive readout (NDRO)is presented. The resulting synapse circuit supports continuousvalued weights. Experimental measurements of a discrete component implementation of the circuit using thin-film ferroelectriccapacitorsproduced in our lab by sol-gel method are presented, and the performance of an integrated circuit implementation is predicted using these results. Finally, results from a ferroelectric capacitor circuit model added to the SPICE circuit simulation program are presented. The SPICE model is appropriate for the simulation of both digital RAM and analog circuit applications. This is in contrast with previous work, which typically modeled only selected responses or was unsuitable for circuit simulation [5][6]. Through simulation of the ferroelectric synapse, high programming resolution, as well as favorable programming saturation characteristicsare demonstrated. 11. NEUROMORPHIC COMPUTATION The basic computing element in neural computation is a processing unit "neuron". Fig. 1 illustrates the basic circuit structure. The resistors correspond to synapses, the input line to the amplifier (which represents the neuron itself) serves the function of dendrite, and the output line corresponds to the axon. The charging current into the capacitor on the amplifier input is given by
dx.
c -$ =
c wij N
(Yj - Xi) ,
j=l
where Xi represents the voltage on the ith amplifier input, Yj is the voltage of the jth output, C is the capacitor value, and Wij is the conductance between the jth amplifier output and ith input. Thus the contribution made by the jth amplifier to the ith input is directly proportional to the conductance (efficacy) of the connection. Xi is essentially a weighted sum of the inputs and accordingly, the Wij are the synaptic efficacies, often referred to as "weights". Note that a connection must have a negative
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conductance if it is to inhibit, i.e., reduce, Xi. Resistors, having only positive conductances, require that this be simulated by using amplifiers with inputs and/or outputs of opposing polarity. Wij'S which must be negative are connected to the negative input, while those which are excitatory are connected to the positive input. Thus Wij = Wij- + Wij+ with the superscripts representing the inhibitory and excitatory connections respectively. The transfer function of the amplifier is monotonically increasing and bounded, generally a tanh or step function. As resistors are not typically employed in VLSI circuits, synapse circuits are built using transistor circuits which inject current into the capacitor representing Xi. This circuit multiplies the voltage representing the weight by the impinging axon voltage with the result represented by a current, i.e. the circuit is essentially a transconductance amplifier.
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number of areas including non-volatility [lo]. improved thinfilm processing and integration with IC processing techniques [ll], and excellent resistance to upset caused by ionizing radiation. Ferroelectric dielectric materials are characterized by a spontaneouspolarization which may be reversed by an applied electric field. A parallel plate capacitor structure is commonly used as it is the simplest electrically accessible memory cell. The material may be viewed as a collection of regions (domains) having like polarization. When no field is applied, the domains retain their orientations. At low fields, these domains are relatively unaffected (although most ferroelectric materials lack a true switching threshold, commonly known as the "half-select disturb problem" [12]). A high field, when applied opposite to the polarization of the ferroelectric material, will switch the ferroelectric. Here, domains which are polarized with the applied field will grow, while those oriented against it will diminish. Consequently, charge which was bound to the structure to balance the old orientation will flow, resulting in the switching current illustrated in Fig. 2. A field applied to a capacitor which has already been switched results in a largely capacitive current, also shown in the figure. This difference in displacement current produced by switching and non-switching capacitors allows the cell state to be read, albeit in a manner which disturbs the cell state, termed destructiveread-out PRO). 0.2 I
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Figure 1. Electronic "neuron" comprising resistors, wires and amplifier.
A number of such neurons, interconnected as a singlelayer matrix can function as an associative memory which produces the stored vector which most closely matches that input. The network relies on the inherent feedback for operation and can may require many iterations to complete a retrieval [7]. The most commonly used training algorithm, Back propagation of errors, utilizes multiple layers which communicate downward during retrieval and upward during training 181. Training algorithms for neuromorphic computers span from these relatively simple versions to complicated feedback structures based on models of biological neural function [9]. However, all neural architectures share the common characteristic of having a large number of neural units interconnected by programmable synapses. 111. FERROELECTRIC CAPACITOR MEMORY
Recently, there has been a resurgence of interest in the use of ferroelectric capacitors as IC memory storage elements. This resurgence has been driven by progress in a
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The measurement circuit used to generate Fig 2 consists of a waveform generator, ferroelectric capacitor, and 50R resistor in series. The voltage across the resistor thus represents the current being measured. The long RC time constant is due to the high E, of the PZT thin-film (E, > 500) and the large size of the capacitor used (lmm diameter). This large capacitive load necessitates a custom built waveform generator utilizing mercury wetted relays to achieve a sufficiently small rise time so as not to affect the results. As a consequence, the slowly ramping Switching component may
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be am-ibuted to the slowly rising field as the voltage across the capacitor follows Vh(l - exp(t/RC)). The Sawyer-Tower circuit illustrated in Fig. 3 is commonly used to characterize ferroelectric capacitors by directly showing the polarization vs. applied electric field (PE) characteristics. The hysteresis, obvious in Figure 4, forms the basis for use as non-volatile memory circuit elements. The circuit operates by the application of a slow (60-IkHz) sine wave, plotted on the x axis, while the voltage on the integrating capacitor
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IV. FERROELECTRIC ANALOG SYNAPSE irm
The proposed analog synapse circuit is represented schematically in Fig. 5. The analog memory circuit which contains the ferroelectric storage device comprises Fig. 6 . Here, the voltage Vw which represents the polarization state
v
pp
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is plotted on the y axis. The y axis thus represents the polarization state of the ferroelectriccapacitor since
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The capacitance of the integrating capacitor should be much greater than that of the ferroelectric capacitor so that the plotted E accurately represents that applied across the ferroelectric. Minor hysteresis loops are formed by applying a smaller amplitude sin wave across the ferroelectric. The result is a polarization less than the saturation polarization Ps, with a correspondingly lower remanent polarization Pr. This behavior suggests one means to program an analog polarization onto the ferroelectric.
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Dendrite X Figure 5. Analog synapse circuit.
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Figure 3. Sawyer-tower circuit,
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Figure 6. Analog memory circuit
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of the ferroelectric capacitor is the weight voltage, used in turn to control the multiplier circuit. This polarization state is programmed by the application of pulses on the control lines V,1 through V d . Transistors T1 and T2 apply the pulses of amplitude -Vpp or Vpp, respectively, to the ferroelectric. These pulses will alter the polarization state through partial switching. To stop the switching abruptly, transistors T3 and T4 are utilized to ground the programming node at the end of a negative or positive pulse, respectively. When all of the transistors are off, the programming node is essentially tristated, to minimize potential leakage through the ferroelectric thin-film. Omission of transistors T3 and T4 would still allow the node to be tri-stated, but at the programming voltage, thereby allowing switching to continue until the voltage diminished. Given the high impedance presented by MOS gate oxides, and assuming a low-loss ferroelectric film, no leakage path exists through which the Vw terminal can discharge [141. In actuality, the ferroelectric thin-film has some finite conductivity. The required refresh rate is consequently a function of the weight resolution required by the application and the conductivity of the ferroelectric thin-film. This refresh rate has experimentally been found to be very low and is discussed below. The weight voltage may be programmed by two methods: application of amplitude modulated pulses or by applying pulses of fixed amplitude, either pulse-width modulated or a series of narrow pulses. The former method programs an analog voltage onto the Vw terminal by traversing minor hysteresis loops, where the voltage is the E=O intercept (Pr) for the loop. In the latter method, partial switching behavior [141 is utilized. Here, the width of a pulse may be modulated analogous to the amplitude modulation of the first scheme. Application of a series of very short pulses allows adaptive training algorithms to be utilized, with each training iteration either applying a pulse or not, of either polarity, as required. The learning rate at each iteration may be controlled by modulating the pulse width or, alternately, the pulse amplitude. Simulation results indicate either method to be effective. A combination of pulse-width and amplitude modulation has been proposed for programming analog EEPROM memories [151. To complete the synapse circuit, the voltage on V, is used to bias a transconductance amplifier. A number of suitable designs exist., see e.g., [16], with the simplest being a single transistor. The amplifier output current represents the multiplication of the input and the weight voltage stored, i.e., the weight controls the amplifier gain. This modulated current represents the efficacy of the synapse at charging or discharging Xi. By implementing the synapses as a matrix, with the control lines running horizontally and the programming lines running vertically, row at a time programming may be employed. Here, the Vpp or -Vpp nodes are grounded during the pulses on a node already having the proper weight.
The synapse circuit has been constructed using discrete components. An electrometer with an input impedance of 2(lOl4)n was utilized to simulate the gain control input of the transconductance amplifier. A lmm diameter PZT (60/40) thin-film capacitor produced in our laboratory was probed as the ferroelectric device. A 47nF integrating capacitor was used. The programming node was grounded after programming. It was assumed that this represented a worst case measurement, since in a real IC implementationonly the diode reverse-biasleakage current will flow through the node. RC timeconstant calculations are also simplified through this approach. A workstation was utilized to automatically measure the node voltages over time. The circuit was programmed and the decay of the modulating voltage Vw was measured. The results are plotted in Fig. 6. An RC time-constant of 94 minutes was calculated from the resulting data. The voltage decay mechanism is assumed to be depolarization or leakage through the ferroelectric due to the small DC bias imposed on the ferroelectric capacitor. This was verified by measuring the retention of a voltage stored on the linear capacitor alone, where the node voltage decayed less than 10% in 24 hours. It should be possible to remove the ferroelectric capacitor from the test circuit and then measure the polarization to determine the actual decay mechanism (or conhibutions by each).
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Figure 7. Experimentally measured weight voltage decay.
C. .IC Imdementat ion and Performana The expected performance of an IC implementation may be inferred if it is assumed that the decay is due to
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leakage. The capacitance of the ferroelectric capacitor used for the measurement was measured to be approximately 3.8nF using a standard laboratory capacitance bridge. The integrating capacitor was 4 7 s . Based on the above RC=94min., a film resistance of R=l.l(lO1 l)Q was calculated, three orders of magnitude less than the electrometer input impedance. Based on the retention time for the linear capacitor alone, leakage through it was assumed to be negligible. The conductivity of the ferroelectric thin-film capacitor was calculated to be 5.16( 10-14)(Qxm)-! A conventional IC capacitor may be utilized as the linear integrating capacitor in the synapse circuit. Assuming that the required gate voltage swing is about 0.7V and for the film used above where P,=0.17C/cm2, the necessary v’alue of CL may be determined to be 6.07(10-2)pF for a square ferroelectric capacitor measuring Spm on a side. The gate oxide capacitance for the MOSIS 3 p n process ranges from 5.5 to 6.7(104) pF/pm2. Using the more conservative value, a 10 by 1l p n integrating capacitor is required. The ferroelectriccapacitor was modeled by a resistance in parallel with a linear capacitor and simulated using SPICE in order to predict the behavior of an integrated circuit implementation. The devices were sized as calculated above. A source to substrate leakage value of O.lnA [17] was used. The circuit was simulated for a resistance value of 1016!2. This represents a film conductivity of 5.16(10-14) and a capacitor 5 by 5mm, 0.45pm thick capacitor. It was found that varying the leakage current parameter does not significantly affect the results, implying that the film resistivity is high enough to dominate the retention time. The required memory refresh rate is a function of the desired analog weight voltage resolution. Based on the above RC time-constant, a weight will decay approximately 1% in 7s. Assuming a 50011s analog voltage write cycle time, a single analog refresh circuit could be used for as many as 14 million connectionsat 1% resolution. SIMULATION RESULTS A. SPICE Ferroelectric C a D w M o u SPICE is a commonly used circuit simulation program [18]. SPICE performs transient analysis by concatenating a series of DC analyses, with energy storage elements treated using implicit integration. To arrive at the DC solution for a given timepoint, a modified nodal analysis is performed on a linearized equivalent to the circuit under analysis. The Newton-Raphson algorithm [19] is employed to linearize non-linear circuit element current vs. voltage characteristics. An obvious approach to modeling a ferroelectric capacitor is to model the current as a tanh (or similar function) of the voltage. While this is adequate for modeling the hysteresis loop data at fixed frequencies, it will fail in modeling the appropriate current when the ferroelectric capacitor is subjected to inputs of different wave shape and or frequency. Modeling the switching current for a specific input
is also inadequate, since in the case where the circuit has no effect on that driving it, and a specific response is known, simulation is unnecessary. Since models in SPICE are based on the I-V characteristicsof the device, a ferroelectriccapacitor model should generate a current based only on the applied field and polarization state of the ferroelectric material. Consequently, time-domain models are inappropriate. The ferroelectricwas treated as a single domain whose characteristicsrepresent the collective average of those actually in the material. This allows the use of rate equations for polarization reversal based on those described by Cabezuelo et al. [20] for a unaxial material. Here, the ferroelectric consists of elementary dipoles embedded in a local effective field &ff = E 5 PP, where E is the external applied field and b is a mean field coefficient relating the effect of the surrounding dipoles on the one in question. The transition probability of a dipole per unit time may be given by
(4) The exponential form is familiar as commonly appearing in expressions describingtransmission over some energy banier. I% thus represents the probability of a dipole jumping in the direction favored or opposed by the effective field. Rate equations are derived from (4) above by describing the dipoles as either residing in the favored field direction or opposing it. These two values, Na and Nb respectively, add to 2Pr. The rate equations can be written as
and
-(wb- - Na pab - Nb Pba’ &
(6)
V.
where p& = p- and p b = p+ above. It is obvious that for large applied fields, Pba is always negligible. Charge conservation is ensured by explicitly integrating the switching current at each timestep and adjusting Na and Nb accordingly. The linear component of the ferroelectric capacitor current is modeled by a linear capacitor, while leakage is modelled by a parallel resistor. It is obvious from the above discussion that the conductivity of the latter is negligable for short time-scales. A lmm diameter (52/48) PZT thin-film capacitor produced in our lab was measured and subsequently modeled. The experimentally measured pulse switching current, non-switching current and simulated results comprise Fig. 8, where the simulation parameters were tuned to match. The circuit utilized to generate Fig 2 was used here with a pulse amplitude of 1OV. Fig. 9 shows the results for a hysteresis loop, utilizing the same model parameters as those used for Fig. 8, whose close
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agreement with experiment indicates that the model is indeed capable of handling widely varying input waveforms. Charge conservation is demonstrated by the hysteresis loop retracing itself.
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pulses with a 30% duty cycle and 300ns cycle time were applied. The linear capacitor value is 0.5pF. Programming pulses of shorter duration and or lower amplitude will result in greater programming resolution than that apparent in the figure. During the applied pulse, the voltage which appears is due to capacitive voltage division of Vpp between the ferroelectric and linear capacitor. The programming node is then driven to OV as discussed in section IV. Note that some clock feedthrough is apparent. The final value stored is then representative of the amount of polarization change due to the applied pulse. The stored voltage on the programmed node is plotted vs. time for programming pulse amplitudes of 6,8, and 10 volts. The pulse width and spacing is fixed for all four curves. While the smoothly saturating behavior has been demonstrated to be desirable in general [16], and when using the back propagation of errors training algorithm [21J in particular, it may be avoided by increasing the pulse amplitude over time.
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Figure 8. Pulse response of ferroelectric capacitor as measured in the laboratory and simulated using the SPICE ferroelectric capacitor model.
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APPLIED VOLTAGE (VJ Fig. 9. Experimental and SPICE simulated hysteresis loop.
B. Programmine The partial switching behavior has been simulated and demonstrates that programming an analog value onto the synapse circuit is possible by applying short pulses to the programming node. This behavior has been verified experimentally in our lab. Simulation results comprise Fig. 10 which is a plot of the Vw node voltage over time. 15V
VI. SUMMARY AND CONCLUSION A simple physical model has been used as the basis of a SPICE circuit model and preliminary results have been presented. The modified SPICE simulator is currently being utilized in the design of analog synapse and programming circuits, and is suitable for use in ferroelectric NVRAM design. The application of ferroelectric thin-film technology to the construction of electrically-alterable analog synapse elements for ANN applications has been discussed. The circuit described supports continuous valued weights. Experimental and simulation results predict very long analog voltage retention times and high circuit density in an IC implementation, greatly improving performance over that obtained using conventional VLSI SRAM or DRAM circuitry to implement synaptic circuits.
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Nut. Acad. Sei., 79. p. 2554-2558, 1982. D. Rumelhart and J. McClelland, Parallel Distributed Processing Vol. I , MIT Press, Cambridge, Ma, 1986. S . Grossberg,Neural Networkr and Natural Intelligence, MIT Press, Cambridge,MA, 1988. J. Evans and R. Womack, "An experimental 52-bit nonvolatile memory with ferroelectric storage cell," IEEE J. of Solid-state Circuits, 23 p. 1171, 1988. S . Dey and R. Zuleeg, "Integrated sol-gel PZT thinfilms on R,Si, and GaAs for non-volatile memory applications," Ferroelectrics, 108, p. 37, 1990. J. Burfoot and G. Taylor, Polar Dielectrics and Their Applications, UC Press, Berkley, Ca.. 1979. S . Dey, K. Budd, and D. Payne, "Thin-film ferroelectrics of PZT by sol-gel method," IEEE Trans. on Ultrasonics, Ferroelectrics, and Freq. Control, 35. p.80, 1988. L. Clark, R. Grondin, and S. Dey, "Ferroelectric connectionsfor IC neural networks," Proc. 1st IEE Int. Conf. on Artificial Neural Networks, 1989, p. 47. M. Holler, S . Tam, H. Castro, and R. Benson, "An electrically trainable artificial neural network (ETA") with 10240 'floating gate' synapses," Proc. Int. Joint Conf. on Neural Networks, 1989,p. 11-191. C. Mead, Analog VLSI and Neural Systems, AddisonWesley, Reading, Ma., 1989. N. Weste and K. Eshraghian, Principles of CMOS VLSI Design, Addison-Wesley, Reading, Ma., 1985. L. Nagel, "SPICE2: A computer program to simulate semiconductor circuits." Memorandum No. ERL-M520, UC Berkley, 1975. S . Director, Circuit Theory: A Computational Approach, Wiley and Sons, NY,1975. M. Cabezuelo, J. Lorenzo, and J. Gonzalo, "FerroelectricSwitchingRevisited," Ferroelectrics, pp. 353-359, 1988. G. Golvin, "SYNAPSIS: a neural network," C Users Journal, p. 59, April, 1989.
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time (ps) Figure 11. Analog programming behavior of the synapse circuit. ACKNOWLEDGEMENTS The authors would like to thank their colleagues at ASU for many helpful discussionsand especially the members of the Advanced Ceramics Laboratory for producing the PZT thin-films used in the measurements.
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REFERENCES M. Sivilotti, M. Emerling, and C. Mead, "A novel associative memory implemented using collective computation," Proc. 1985 Chapel Hill Conf.on VLSI, p. 329, 1985. L. Akers and M. Walker, "A limited interconnect synthetic neural IC," Proc. I988 Conf. on Neural Networks, p. 11-151, 1988. H. Graf, L. Jackel, R. Howard, B. Straughn,J. Denker, W. Hubbard, D. Tennant, and D. Shwartz, "VLSI implementation of a neural network memory with several hundreds of neurons," AIP Cog. Proc. 151: Neural Networks for Computing, J. Denker, ed., AIP, N.Y., p. 182, 1986. J. Sage, K. Thompson, and R. Whithers, "An artificial neural network integrated circuit based on MNOS/CCD principles, "AIP Conf.Proc. 151: Neural Networks for Computing, J. Denker, ed., AIP, N.Y., p. 182, 1986. A. Kulkarni, G. Rohrer, S . Narayn, and L. McMillan, "A circuit model for a thin-film ferroelectric memory device," Ferroelectrics, 116, p. 95, 1991. S. Miller, R. Nasby, J. Schwank, M. Rodgers, and P. Dressendorfer, "Device modelling of ferroelectric capacitors," J. Applied Phys., 68, p. 6463, 1990. J. Hopfield, "Neural networks and physical systems with emergent collective computational abilities," Proc.
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