Integrated low noise low power interface for neural bio-potentials recording and conditioning Emanuele Bottinoa , Sergio Martinoiaa and Maurizio Vallea a Dept.
of Biophysical and Electronic Engineering, University of Genoa – Via Opera Pia 11A, 16145, Genova, ITALY ABSTRACT
The recent progress in both neurobiology and microelectronics suggests the creation of new, powerful tools to investigate the basic mechanisms of brain functionality. In particular, a lot of efforts are spent by scientific community to define new frameworks devoted to the analysis of in-vitro cultured neurons. One possible approach is recording their spiking activity to monitor the coordinated cellular behavior and get insights about neural plasticity. Due to the nature of neurons action-potentials, when considering the design of an integrated microelectronics-based recording system, a number of problems arise. First, one would desire to have a high number of recording sites (i.e. several hundreds): this poses constraints on silicon area and power consumption. In this regard, our aim is to integrate–through on-chip post-processing techniques–hundreds of bio-compatible micro-sensors together with CMOS standard-process low-power (i.e. some tenths of µW per channel) conditioning electronics. Each recording channel is provided with sampling electronics to insure synchronous recording so that, for example, cross-correlation between signals coming from different sites can be performed. Extra-cellular potentials are in the range of [50 − 150] µV , so a comparison in terms of noise-efficiency was carried out among different architectures and very low-noise pre-amplification electronics (i.e. less than 6.5 µV rms ) was designed. As spikes measurements are made with respect to the voltage of a reference electrode, we opted for an AC-coupled differential-input preamplifier provided with band-pass filtering capability. To achieve this, we implemented large time-constant (up to seconds) integrated components in the preamp feedback path. Thus, we got rid also of random slow-drifting DC-offsets and common mode signals. The paper will present our achievements in the design and implementation of a fully integrated bio-abio interface to record neural spiking activity. In particular, preliminary results will be reported. Keywords: Bio-abio interface, neural spikes recording, standard CMOS technology, chip post-processing, biopotential noise floor, low-noise low-power preamplifier, band-pass filtering, Sample and Hold, analog Multiplexer, noise analysis.
1. INTRODUCTION The idea of a direct interaction between the human brain and artificial devices is fascinating and discloses a number of intriguing applications (e.g. neuroprostheses, artificial limbs control 1, 2 ). Unfortunately, few is known yet about brain functionality, in particular with respect to the organisation of neurons networks (i.e. neural plasticity) and to the learning mechanisms. Today, investigations in these fields regard disciplines such as biology, physics, chemistry, electronics and involve a remarkable portion of the international scientific community. Among other approaches, one can gather informations about the central nervous system (CNS) functionality by recording the extra-cellular action potentials (i.e. spikes) of biological neural-cells networks cultured in-vitro. This technique offer the possibility both to get insight about a single neuron and, at the same time, to monitor the emerging cellular collective behavior as the culture grows and develops its own interconnections (i.e. dendrites and axons). Today, commercial solutions–based on arrays of microelectrodes (MEAs)–are available to perform the recording task.3 These tools let monitoring the electrical activity of 60 and up to 120 sites simultaneously inside the culture, thus making feasible neural signal characterisation (both in time and frequency domains) and analysis (e.g. spikes occurrence frequency, signals correlation among different sites). Furthermore, these devices Corresponding author additional informations: E-mail:
[email protected], telephone: +39 010 353 2287, fax: +39 010 353 2777.
allow to evaluate the neural network response due to electrical stimulations, which the user can send–although to a limited extent–to some of the recording sites. The main problems of commercial devices are the limited number of recording sites and the even smaller number of stimulating electrodes (e.g. four). Moreover, as the acquisition electronics (namely, amplifiers) is realised with discrete components (i.e. not integrated in the MEA structure), their overall performance can be compromised by enviromental noise sources–such as electromagnetic interference4 (EMI)–and the presence of parasitic elements along electrode-to-electronics wiring. To overcome this kind of problems, ad-hoc recording systems can be designed, in which low-noise electronics is integrated together with sensor arrays. In this case, anyhow, a number of additional issues–mainly regarding silicon area occupation–must be properly addressed, whereas amplifying electronics has still to satisfy a number of contrasting requirements (i.e. low noise performances, DC filtering, low power consumption). In this paper we present preliminary results on the design of an integrated low noise interface, devoted to record extra-cellular action-potentials of in-vitro cultured neurons network. One of the imperative we followed during its development was keeping the electronics area occupation as small as possible. 5 In fact, when considering the integration of a several-hundreds channel recording system, silicon area occupation is the main issue to address. Another fundamental aspect we dealt with is the power consumption of the preamplifier stage, which–being very close to the culture– needs to be minimized not to damage biological tissue. 6 At the moment, the interface is designed to work with commercial MEAs, but we are working towards its integration together with bio-compatible microelectrodes, obtained through post-processing techniques. These ones involve, among other steps: (a) the deposition of a thick, bio-compatible insulating layer over the conditioning complementary metaloxide-semiconductor (CMOS) electronics; (b) the drilling of insulator on specific locations (corresponding to the recording sites); (c) the deposition of proper conductive material inside the drilled holes. Other approaches for realising integrated sensors have been proposed,7 but they use a non-standard CMOS process which is, instead, a stringent requirement for us. The paper is organised in sections, as follows. In Section 2 we analyse the action-potential signal, recorded employing a commercial system, and we define its time-domain features (noise floor, minimum and maximum spike amplitude) and we determine its frequency bandwidth. These data will be of primary importance in defining our interface specifications, in particular regarding the preamplifier front-end. In Section 3 we report recent implementations of recording interface and/or neuro-potential preamplifiers having a function as similar as possible to the architecture described here . Their main features are briefly mentioned and compared; some comments are done with respect to our application. Section 4 describes our recording interface, explaining the function of its stages. Section 5 deals with the interface core block: the low-noise low-power (LNLP) preamplifier, focusing on some of its design aspects. Simulation results and design estimations are reported and compared with the state of the art. Conclusion and future project milestones are outlined in Section 6.
2. NEUROSIGNAL CHARACTERISATION In order to define detailed specifications which our interface must comply with, we characterized the neural signal using the commercial system already cited in Section 1. The analysis was performed both in time and frequency domain, in order to determine the noise floor, the signal average amplitude and its bandwidth.
2.1. Measurement setup The experimental set-up is based on MEA60 System 3 : it is routinely used for conducting experiments on neuronal networks. Measurements are performed with respect to a reference electrode dipped in a physiological solution (N a+ and K + based) used as a growing environment for the colture. Solution is kept at a constant temperature of 37 o C. In the laboratory experiments, dissociated primary cultures of cortical neurons from day 21 embryonic rats were used. Neurons were plated on arrays of 60 planar microelectrodes pre-coated with adhesion promoting molecules (Poly-D-lysine) and kept alive in healthy conditions for weeks. The network electrophysiological activity was recorded starting form the second week of culture, to allow synaptic connections among the nerve cells to be formed.8
2.2. Time and frequency analysis We carried out several measurements at different environmental conditions (i.e. culture age, electrical and chemical stimuli before recording) and varying the sampling frequency as well as the recording time duration. We observed that spikes occurrence frequency is dependent from stimuli (both electical and chemical), whereas their minimum amplitude is about independent from recording conditions (it is only fairly sensitive to different chemical environments). As we are interested in worst-case conditions, we focused on signals deriving from spontaneous activity (i.e. no chemical nor electrical stimuli).
µ
In Figure 1 a typical extra-cellular signal sample is shown. In this case a sampling frequency of 10 KHz was employed.
Figure 1: A 20 seconds extra-cellular signal sample due to neuron spontaneous activity.
Pulses from −50 µV and up to −90 µV are visible (i.e. action potentials), usually followed by 20 − 30 µV waveforms of opposite polarity lasting about 1 − 4 ms (i.e. resting potentials). While it was easy to determine a spike amplitude minimum value, it is not trivial to define a maximum, as a large spread of values can be found due to inherent complexity of the considered biological systems, where it is virtually impossible to claim two different experiments are the same (see for example the work of Bove, Grattarola and Verreschi 9 ). In our case, observed spike maximum amplitude was about |150| µV . The overall signal presents an average value of about 4.4 µV : this is because the recording and the reference microelectrodes experience a time-varying offset due to a slow, random drift in the physiological solution biasing. Anyhow, as its variation is so slow, we ragard it as a DC component–whose maximum reported amplitude is 100 mV pp 10 –which must be properly managed to avoid preamplifying stage saturation. A noisy component is also present, mainly deriving from two sources: (a) a “secondary” activity of neurons–usually regarded as noise–; (b) the recording-site neighbor cells activity, interfering with measurements. Noise maximum amplitude is about 18 µV rms . Actually, because of the distance between recording sites and amplification electronics, a third source of noise is expected (as explained in Section 1). Again, to put ourselves in a worst-case situation, when considering fully integrated systems design, a noise estimation between 5 − 10 µVrms is more correct (in this case, in fact, design noise specifications become more stringent). To determine the bio-potential bandwidth we considered shorter sections (i.e. some tens of mV ) of the time-domain signal and performed power spectral density (PSD) estimations through the use of the Welch’s method .11 In Figure 2a the action-potential portion used for the estimation is shown: it has a duration t of 51.2 ms and has been sampled at a frequency fs of 10 KHz. The choice of t and fs is justified by considerations on the signal characteristics which should maximize the spectral resolution.12 The action-potential PSD is depicted in Figure 2b, where two peaks are distinguishable. The presence of the base-band peak can be justified by two main factors: (1) the signal DC component and (2) the 1/f noise. 13
µ" # !
µ
(a)
(b)
Figure 2: Time and frequency domain analysis of neuron spontaneous electro-physiological activity. (a) An extra-cellular action-potential followed by a resting-potential; noise activity is visible as well. (b) Signal PSD estimation; although fs /2 = 5 KHz, the X axis is limited to 3 KHz, as the waveform remainder tail would have been poorly meaningful.
Though, the base-band peak exact value is not trivial to determine due to inherent numerical approximations and windowing issues. The main power contribution delivered by the action potential is in the range [40 − 500] Hz, whereas the signal bandwidth–by definition corresponding to the 98% of its total power–is [10 − 1900] Hz. Again, due to the long wiring between the MEA and preamplifiers, one can suppose the presence of parasitics could act as a R − C filter before the signal can reach the conditioning electronics. So, to be conservative, we assume the neurons bio-potential spectum to be in the range [10 − 3000] Hz. Signal bandwidth evaluation consistency was checked by estimating PSD of neuro-potential signals sampled at fs = 50 KHz, in order to investigate waveform harmonics up to 25 KHz. No useful information was added to previous analyses.
3. NEURO-SIGNAL INTERFACES STATE OF THE ART Many proposals of an integrated neuro-potentials recording interface have been advanced so far. In the remainder of the section we will briefly summarize the main features of some of the most interesting architectures. While some of the following systems record signals of in-vivo cells∗ , all of them amplify the input differential signals–the measures are performed with respect to a reference–of each recording channel. Moreover, they provide some sort of signal conditioning, in order to filter away the meaningless harmonics–usually the signal bandwidth (BW) goes from few Hz up to few KHz– and DC offset blocking capability. Finally, systems are designd optimizing noise performances. Dabrowski, Grybos and Litke14 employ a preamplifier splitted in two AC coupled stages to avoid differential input offset propagation. Moreover, a band-pass filter cascaded to the preamplifier is provided with external current-based control to tune separately lower and upper corner frequency. Harrison and Charles15 exploit the sub-threshold properties of lateral BJTs–whose terminals are properly connected– to realize very large resistive elements,16 employed in a closed-loop configuration together with a cascoded operational transconductance amplifier (OTA). The OTA is dimensioned in order to maximize the noise efficincy factor.17 Patterson et al.18 realize the connection between a commercial three-dimensional microelectrodes array and the conditioning electronics by employing a conductive silver epoxy. Band-pass filtering capability is achieved ∗
This is not a problem, as extra-cellular in-vivo action potentials are very similar to their in-vitro counterparts.
through a R − C network, where high value resistors are diode-connected N-type MOS (NMOS) properly linearized. A DC compensation feedback is provided by means of a feedback loop which adjust DC preamplifier inputs imbalances. Mojarradi et al.19 interface microelectro-mechanical systems (MEMS)-based microelectrodes with amplifying electronics (i.e. folded-cascode OTA) realized through partially depleted silicon-on-insulator (PDSOI) and standard CMOS processes. DC offset is eliminated using a ditgital-to-analog converter at the preamplifiers battery output. Uranga, Navarro and Barniol20 address the electronics flicker-noise generation implementing a chopper technique, while an electrodes-electronics AC-coupling and a band-pass filter cascaded to preamplifiers are the chosen methods to cope with DC blocking and bandwidth requirements, respectively. In Table 1 the main features of the above implementations are reported for comparison. Table 1: Performances summary of five recent interface implementations for neuro-potential recording. To offer a fair comparison between these proposals and our achievements, we reported–whenever possible–simulated data instead of on-chip measurements. Besides, ¦ indicates an experimental, measured value. If not stated otherwise, data regard a single recording channel, whereas a † indicates the value is relative to the lone premplifier. ‘Noise BW’ is the noise bandwidth and represents the frequency range used for the input-referred noise voltage calculation. ‡ means a PDSOI technology has been employed instead of a standard CMOS process.
Referenece
Dabrowski14
Harrison15
Patterson18
1.5
1.5
1.5
Technology (Lmin ) [µm] Supply voltage [V ] Area occupation [mm2 ] Power consumption [µW ] IN-referred noise [µVrms ] Noise BW [KHz]
5 0.35 ¦
†
0.35; 0.5; 0.5
0.7
5
3.3
3.3; 5; 5
5
≈ 0.3
n.a.
2.7
†
¦†
†
[0.03 − 2]
‡
Uranga20
0.16
1700 3
Mojarradi19
80
†
2.1
†
[10−4 − 7.2]
52
6.8
[0.005 − 7.5]
†¦ ¦†
9.9; † 60; † 15 †
†
8.2; 3.9; 8.7 [10−3 − 10]
¦† ¦†
965
4.53 · 10−1
[n.a. − 3]
As per our application figures, a similar bandwidth is chosen only by Dabrowski and Uranga. While the latter reports both large area occupation and power dissipation (but it’s well comprehensible, as his conceived recording channel includes a band-pass filter, a post-amplifier and a low-pass filter), the former end up with reasonable values (the power dissipation reported is relative to a whole recording channel). In fact, constraints evaluations regarding the maximum area occupation and consumption for a fully integrated preamplifier–to be employed in a 1000-channels recording interface–indicate that it should not dissipate more than 80 µW and occupies an area comprised between 0.1 and 0.2 mm2 .5 Unfortunately, we know neither the Dabrowski’s preamplifier sizes, nor Mojarradi’s, nor Patterson’s ones. While Patterson offers probably the best trade-off from our point of view, Mojarradi uses a non standard CMOS process to obtain his best figures, but he doesn’t report even sizes estimation for his recording channel. Harrison, finally, achieves very nice figures regarding both noise and power consumption. With respect to the noise floor and signal bandwidth determined in Section 2, it seems that literature proposals tend to emphasize too much noise performances over a too large portion of the frequency spectrum. In fact, such very low-noise performances can only be reached trading off power and, mainly, area occupation. Moreover, if one limits the bandwidth of interest, noise figure will be anyway smaller.
4. SYSTEM OVERVIEW Our aim is to implement a 1000 channel interface, capable of recording extra-cellular spiking activity coming from a neural-cells in-vitro colture. As stated in Section 1, one of the main directive we followed during system design was simplicity, in order to minimize silicon area occupation. Thus, we conceived an architecture comprised by simple-concept stages which were specifically tailored for our application; in this regard, a fundamental step was
the signal analysis descripted in Section 2. We avoided designing an interface which performs complete signal conversion and conditioning (e.g. analog-to-digital conversion or ADC, spike sorting), delegating this task to off-chip implementations. In fact, the underlying design concept was to preserve as much as possible the neural signal characteristics, to mantain as much generality as possible. In this way, at the interface output, maximum freedom is let to perform any kind of signal conditioning and analysis, both in time and frequency domain. The proposed architecture–providing n recording channels–is comprised by four stages: n LNLP preamplifiers which feed the S&H battery, an analog multiplexer (MUX) and an output amplifier. While the first two stages are conceived to be placed as close as possible to the electrodes, the MUX and the output amplifier don’t have to meet stringent area occupation constraints. 1
Vin
2
Vin
MUX
OTA
Nx1
Vout
n
Vin
Vreference CONTROL SIGNALS
Figure 3: Proposed interface-system diagram.
The core block of the proposed interface (Figure 3) is represented by the preamplifying stage. A brief description of this block is given in Section 5. The other key stage of the system is the sample and hold (S&H) battery. It allows the recording of electrophysiological events located at different sites, which occurs exactly at the same moment, making feasible, e.g., the extrapolation of cross-correlation functions and other statistical analysis among channels. Circuitry takes in account impedance adaptation between its input (i.e. preamplifier output) and its output (i.e. the analog multiplexer) through the use of buffers (not shown in the figure). These ones are easily implemented through differential pairs connected to form a unity-gain buffer configuration. Charge injection effects on the sample-and-hold capacitor are reduced by dummy devices in series with the switch transistor. The analog multiplexer provides merging over time of the n sampled waveforms. Supposing to sample at frequency fsamp (i.e. about 3 KHz), the multiplexer scans periodically each channel (every 1/f samp seconds) and transfers every channel sample to its output, keeping it stable for tstable = 1/n · fsamp seconds (circular buffer structure). In our case, given n = 1000, tstable would be about 300 ns. The MUX output signal, is fed into an output amplifier, which provides an appropriate gain to make the signal suitable for further processing (i.e. ADC, time and frequency domain analyses). The design requirements of third and fourth stages comprise low power consumption and reliability. Proper synchronizating electronics for the S&H and MUX must be provided as well. An about 3 MHz, 10-bit counter coupled with a demultiplexer can drive MUX switches (i.e. pass-transistors), while S&H switching logic is–in this case–3 orders of magnitude slower.
5. LOW-NOISE PREAMPLIFIER This block is comprised by differential LNLP amplifiers (one for each recording channel), directly connected with the microsensors array; beside providing proper signal enhancement, it has not to degrade it, that is, it must
not increase the noise floor. Moreover it has to: (a) insure a proper filtering against DC component due to measurement set-up requirements; (b) offer a very high input impedance, as microelectrode inherent resistance is not negligible (commercial MEAs range is [20 − 400] KΩ3 ); (c) minimize power dissipation in order to comply with biological tissue temperature requirements; (d) occupy a small silicon area. A detailed analysis of the preamplifier is reported elsewhere5 ; in the Section reminder we will limit ourselves to describe the noise analysis comparsion we performed among different OTAs, in order to choose the best implementation for our scopes. Designed preamplifier performances will be reported as well.
5.1. Preamplifier overview The action-potential preamplifier is basically a differential input, single-ended output OTA provided with a resistive-capacitive feedback loop. The R − C loop insures the high-pass filter functionality required to filter off bio-potential DC-components. The overall transfer function of the preamplifier is a band-pass one, where both the base-band and frequencies greater than some KHz are filtered away. Given the spikes BW, one can see the lower-corner frequency has to be extremely low (i.e. high τ = R · C constants). Realizing large time-contant integrated elements is a main issue in analog design: for this reason we employed a dedicated component, the MOS-Bipolar.16 The OTA offers also a high open-loop gain in order to insure a precise closed-loop gain. LNLP performances and small area occupation are insured by a careful determination of architecture parameters (i.e. devices transconductances, W/L, bias current, mirroring-factors, etc.) and a consistent performance trade-off.
5.2. OTAs noise performance comparison We have seen in Section 2.2 that extra-cellular action-potentials minimum amplitude is about 50 µV , whereas the maximum noise floor is 10 µV . Thus, the preamplifier root-mean-square noise voltage must be lower than the latter value to avoid unwelcome increase of the noise floor, which could result in a signal degradation. In this perspective, we performed a detailed noise analysis on four OTA architectures to determine the best solution in terms of gain, noise and complexity (see Figure 4). Given the signal BW, the flicker noise (1/f noise) component dominates over the thermal one. For this reason we employed for all the structures a P-type MOS (PMOS) differential pair, as–in the two technological processes we used–PMOSes offered better 1/f noise performances than their NMOS counterparts. 2 21 For the analysis we evaluated the low-frequency PSD input-referred noise Virn for each OTA topology. 2 We report briefly, herewith, the results obtained for the different OTA topologies. The terms V ni represent the equivalent noise voltage generators (actually, the PSD value of the equivalent noise voltage generator in series to each device gate) used to model the noise contributions coming from each MOS. The following equations are valid assuming: (a) small-signal equivalent circuits are ideal linear systems; (b) devices are properly matched (e.g. differential pair MOSes width and length are equal) and their mathcing is ideal; (c) noise sources are uncorrelated. For additional informations regarding analog circuit noise analysis, see for example these references. 22, 23
Symmetrical OTA: 2 Virn
where: 2 2 • ro,I ≈ 1/gm4 ; 2 2 • rdN ≈ 1/gdN ; 2 2 • rdP ≈ 1/gdP .
≈
2 Vn1
1 + 2 2 gm1 ro,I
µ
2 2Vn3
+
2 Vn6
+
2 Vn8
+
2 Vn5
+
2 Vn7
V2 V2 + 2 nN2 + 2 nP2 gm6 rdN gm8 rdP
¶
(1)
M7
M8
M8
VP
MP
M 10
M9
M6
M7
vOUT
I BIAS
v−
M1
M5
v+
M2
M3
v−
VN
MN
M4
M1
M4
M3
M6
I BIAS
v+
M9
M10
v−
VB1
M6
M1
M2
I BIAS
IB
vOUT
M7
M8
M4
M3
M2
M1
M5
(b) M4
v−
vOUT
I BIAS
(a) M3
v+
M2
M12
M13
M10
M11
v+
M8
VB1 vOUT
M9
VB2
VB2
M5
M5
M6
(c)
M7
(d)
Figure 4: The four operational transconductance amplifiers chosen for the noise performance evaluation. (a) A symmetrical configuration provided with an inverting, cascoded output stage. (b) A Miller, transconductance amplifier. (c) A singlestage cascode OTA. (d) A folded cascode.
Due to the symmetrical configuration (i.e. M3 and M4 mirror their current externally with respect to the first stage), the main noise contribution come from the differential pair only, whereas other sources are scaled at least 2 2 ). by a factor equal to the first stage gain (gm1 ro,I Miller OTA: 2 2 Virn ≈ 2Vn1 +2
2 gm3 1 2 2 Vn3 + g 2 r 2 gm1 m1 o,I
µ
2 Vn5 +
2 gm6 2 2 Vn6 gm5
¶
(2)
with: 2 2 • ro,I ≈ 1/gm4 ;
In this case M3 mirrors its current in M4 and both belongs to the first stage. Thus, their contribution to noise is comparable to the one given by the differential pair. OTA Cascode: 2 2 +2 ≈ 2Vn1 Virn
2 gm6 2 2 Vn6 gm1
(3)
For the OTA Cascode and the Folded Cascode circuit, we avoid reporting the complete input-referred noise equation, as other devices contribution is negligible. OTA Folded cascode: 2 2 Virn ≈ 2Vn1 +2
2 2 gm6 gm12 2 2 V + 2 n6 2 2 Vn12 gm1 gm1
(4)
In this case the cascaded devices contribution is about double than in the OTA Cascode. From the above results it should be clear that the best configuration is the first one (Equation 4a), as its noise come from the differential pair only. For this reason, the symmetrical OTA architecture was chosen to design the preamplifier. Actually, considerations on gain performances supported by several simulations demonstrated that it was possible to eliminate the two output-stage cascaded devices. In this way, we avoided adding at least other six transistors needed to properly bias the cascode MOS, with a substantial gain with respect to area saving.
5.3. Performances The preamplifier was designed using two different technologies in order to evaluate benefits and defects of each realisation and perform a comparison between them. In Table 2 performances are shown. Table 2: Designed preamplifiers performances using two different processes. previous layout design24 and should be regarded as an upper limit.
Technology
∗
indicates an estimated value derived from
AMS 0.35 µm
TSMC 0.35 µm
Supply voltage [V ]
±1.65
±1.65
Supply current [µA]
1.36
1.35
fL [Hz]
1.96
7.8
fH [KHz]
3.6
5
Virn [µVrms ]
6.23
8.51
Preamp power consumption [µW ] 2
Channel area occupation [mm ]
4.49 ∗
4.46 ∗
0.15
Channel power consumption [µW ]
∗
0.15
90.05
As one can see, these figures respect both BW and noise floor specifications. Moreover, both the area accupation and the power consumption are smaller than any other solution previously reported (see Table 1).
6. CONCLUSIONS In this paper we presented our achievements in designing a fully integrated LNLP interface for in-vitro neurons extra-cellular action potential recording. After having defined bio-signal properties, we offered an overview on recent state of the art, outlining the main issues regarding our specific application. A recording interface is presented and its main component stages as well as its features are briefly described. A more detailed explanation of the preamplifier noise analysis follows and overall circuit figures are shown. As previously stated, the interface is tailored on application specifications and prefer a simple, power-saving small design instead of a complex, very low-noise, heavy-conditioning one. In this regard our system performances appear to be better than previously reported implementations. At the moment, a test chip is ready to be sent to fabrication. Measurements will hopefully confirm simulated results and will allow high resistive elements characterisation. The next steps will include: the design of a 1000 channels system provided with preamplifiers, S&H, the analog MUX and the relevant control logic; the integration of the interface together with the microelectrodes in the same silicon chip, by means of post-processing techniques.
ACKNOWLEDGMENTS Authors would like to thank Dr. Antonio Novellino for the precious help and the useful discussions about measurements of electro-physiological neurons activity. This work is part of a project funded by the Education, University and Research Italian Minister (PRIN 03).
REFERENCES 1. D. R. Kipke, “Implantable probe systems for cortical neuroprostheses,” in Proc. IEEE International Joint Conference on Neural Networks, 3, p. 1747, 2004. 2. M. J. Osborn and S. Wolpert, “A vlsi-based biological interface for prosthetic devices,” in Proc. IEEE Eighteenth Annual Northeast Bioengineering Conference, pp. 75-76, Mar 1992. 3. Multi Channel Systems, “MEA-System.” On-line. http://www.multichannelsystems.com. 4. K. H. Kim and S. J. Kim, “Noise performance design of CMOS preamplifier for the active semiconductor neural probe,” IEEE Transactions on Biomedical Engineering 47, pp. 1097-1105, Aug 2000. 5. E. Bottino and M. Valle, “Integrated low noise preamplifier for biologic-electronics interfaces,” in Proc. European Conference on Circuit Theory and Design (ECCTD ’05), submitted. 6. T. M. Seese, G. M. Saidel, and C. R. Davies, “Characterization of tissue morphology, angiogenesis and temperature in the adaptative response of muscle tissue to chronic heating,” Lab. Invest. 78(12), pp. 15531562, 1998. 7. B. Eversmann et al., “A 128×128 CMOS biosensor array for extracellular recording of neural activity,” IEEE Journal of Solid-State Circuits 38, pp. 2306-2317, Dec 2003. 8. M. Valle, ed., Smart adaptive systems on Silicon, Kluwer Academic Publishers, 2004. 9. M. Bove, M. Grattarola, and G. Verreschi, “in-vitro 2-d networks of neurons characterized by processing the signals recorded with a planar microtransducer array,” IEEE Transactions on Biomedical Engineering 44, pp. 964-977, Oct 1997. 10. Q. Bai and K. D. Wise, “Single-unit neural recording with active microelectrode array,” ”IEEE Transactions on Biomedical Engineering” 48, pp. 911-920, Aug 2001. 11. P. D. Welch, “The use of fast fourier transform for the estimation of power spectra: a method based on time averaging over short modified periodograms,” ”IEEE Transactions on Audio and Electroacoustic” 15, pp. 70-73, 1967. 12. A. V. Oppenheim and R. W. Schafer, Elaborazione Numerica dei Segnali – original title: Digital Signal Processing, Prentice-Hall, C. Braccini and G. Gambardella, FrancoAngeli 2003, Italian ed., 1975. 13. S. W. Smith, The Scientist and Engineer’s Guide to Digital Signal Processing, California Technical Publishing, electronic ed., 1997. 14. W. Dabrowski, P. Grybos, and A. M. Litke, “A low noise multichannel integrated circuit for recording neuronal signals using microelectrode arrays,” Biosensors and Bioelectronics 19, pp. 749-761, Feb 2004. 15. R. R. Harrison and C. Charles, “A low-power low-noise CMOS amplifier for neural recording applications,” IEEE J. Solid-State Circuits 38, pp. 958-965, Jun 2003. 16. T. Delbr¨ uck and C. A. Mead, “Analog vlsi adaptive, logarithmic, wide-dynamic-range photoreceptor,” in Proc. IEEE Int. Symp. Circuits and Systems, 4, pp. 339-342, 1994. 17. M. S. J. Steyaert, W. M. C. Sansen, and C. Zhongyuan, “A micropower low-noise monolithic instrumentation amplifier for medical purposes,” IEEE J. Solid-State Circuits SC-22, pp. 1163-1168, Dec 1987. 18. W. R. Patterson, Y.-K. Song, C. W. Bull, I. Ozden, A. P. Deangellis, C. Lay, J. L. McKay, A. V. Nurmikko, J. D. Donoghue, and B. W. Connors, “A microelectrode/microelectronic hybrid device for brain implantable neuroprosthesis applications,” IEEE Transactions on Biomedical Engineering 51, pp. 1845-1853, Oct 2004. 19. M. Mojarradi, D. Binkley, B. Blalock, R. Anderson, N. Ulshoefer, T. Johnson, and L. D. Castillo, “A miniaturized neuroprosthesis suitable for implantation into the brain,” IEEE Transactions on Neural Systems and Rehabilitation Engineering 11, pp. 38-42, Mar 2003. 20. A. Uranga, X. Navarro, and N. Barniol, “Integrated CMOS amplifier for ENG signal recording,” IEEE Transactions on Biomedical Engineering 51(12), pp. 2188-2194, 2004.
21. K. R. Laker and W. M. C. Sansen, Design of Analog Integrated Circuits and Systems, McGraw-Hill International Editions, 1994. 22. S.-C. Liu, J. Kramer, G. Indiveri, T. Delbr¨ uck, and R. Douglas, Analog VLSI: Circuits and Principles, MIT Press, 2002. 23. B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001. 24. E. Bottino, S. Martinoia, and M. Valle, “Integrated low-noise signal conditioning interface for neuroengineering applications,” in Proc. European Symposium on Artificial Neural Networks (ESANN ’04), pp. 513-518, Apr 2004.
