Integrated Recirculating Optical Hybrid Silicon Buffers

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Geza Kurczveil*, Martijn J. R. Heck, John M. Garcia, Henrik N. Poulsen, Hyundai Park, , Daniel J. Blumenthal, John E. Bowers. Department of Electrical and ...
Integrated Recirculating Optical Hybrid Silicon Buffers Geza Kurczveil*, Martijn J. R. Heck, John M. Garcia, Henrik N. Poulsen, Hyundai Park, , Daniel J. Blumenthal, John E. Bowers Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA, USA 93106 ABSTRACT We present our work on fully integrated hybrid silicon optical buffers capable of holding 40 byte packets at 40 Gb/s. These devices consist of low loss silicon waveguides and cascaded amplifiers to overcome passive losses in a 1.1 m long delay line. Since cascading multiple gain elements leads to ASE (noise) accumulation, reshaping elements in the form of saturable absorbers are integrated in the delay. Noise filtering in the buffer is investigated by simulating the eye diagram for a delay line with 1R regenerators and comparing it to that of a 2R regenerator. Finally, preliminary experimental data from the optical buffer is shown. Keywords: Optical buffers, semiconductor optical amplifiers (SOAs), hybrid silicon platform

1. INTRODUCTION While internet traffic today is mostly transmitted in the optical domain over optical fibers, routing is still done in the electrical domain. Converting the optical signal into an electrical signal and back into an optical signal requires power which an all optical router could save [1]. In an electrical router, memory in the form of random access memory (RAM) is necessary for contention resolution. Unfortunately, photons are inherently more difficult to store than electrons. A big challenge in realizing an all optical router is making optical memory. There are several approaches to store light. While slow light approaches are compact [2], [3] they have an inherent bandwidth-delay limit [4] making them uninteresting for practical applications where 40 byte and larger packets have to be stored at 40 Gb/s and beyond. Another approach is to use delay line buffers, but so far the only practical delay line buffers that were demonstrated used fiber delays [5, 6, 7]. Ultra-compact fiber delay buffers have been shown [8], but they require additional packaging. Integrated delay line buffers capable of holding 40 byte packets at 40 Gb/s have yet to be demonstrated. One previous approach towards an integrated buffer was the hybrid integrated buffer shown in Figure 1 (a). It consisted of an InP 2×2 switch butt-coupled to a low loss silica delay. The switch had a high extinction ratio (>40 dB), low cross talk (