Integrated System Development for 3-D VLSI L. Schaper1, S. Burkett1, M. Gordon2, L. Cai1, Y. Liu1, G. Jampana3, and I. U. Abhulimen1 University of Arkansas 1 Electrical Engineering, 2Mechanical Engineering, 3Microelectronics-Photonics Fayetteville, AR 72701
[email protected] Abstract A great deal of work has been done in creating 3-D VLSI by wafer stacking and through silicon via (TSV) processing for dense Z-axis interconnects. Various methods for wafer attachment have been used, including polymer glue, oxideoxide bonding, and direct metallic bonding. Yet these wafer attachment methods may not be the best way to assemble 3-D systems from VLSI elements. Systems consist of more than silicon ICs. Many systems, particularly those designed for RF or sensor applications, may need to assemble both III-V and silicon layers with TSVs, remove significant amounts of heat, provide integrated decoupling and power distribution, and avoid cumulative yield issues by pretesting individual die layers before assembly. Typically, each layer may be a miniature subsystem, so that Z-axis interconnect demand can be satisfied by connections on 100 - 200 µm pitch. This paper describes an advanced 3-D packaging concept using die stacking rather than wafer bonding. To deal with the CTE mismatch of different materials, compliant copper posts are used to join individual layers. The copper is also used to form a fluid dam around the resulting channel between each pair of die. Circulating fluid is pumped through these channels for heat removal. Sequential attachment of pretested layers is accomplished by forming copper/tin intermetallics. Decoupling and power distribution are provided by thin film capacitors between copper distribution planes on dedicated silicon layers. The results of process development on the various aspects of this approach will be presented. TSVs of 20 µm diameter on 100 µm pitch have been fabricated in wafers thinned to 100 µm thick. Copper posts 30 µm in diameter and 80 µm high have been demonstrated. The results of tests on via and post daisy chains will be presented. Decoupling layers based on thin-film Ta2O5 dielectric capacitors will be described. The design of a complete test vehicle intended to demonstrate the integration of these methods will be presented. This novel concept for packaging miniature 3-D VLSI systems appears well-suited to high power RF and other system applications. Background Many efforts worldwide are working to create 3-D VLSI die by wafer stacking [1]. Wafers are bonded by polymer glue or other processes, before or after thinning, depending on wafers being joined face to face or back to face. An example of face to face bonding using BCB as glue is the RPI process shown in Figure 1 [2]. In this process no handle wafer is used, as the upper wafer is not thinned until it is joined to the bottom wafer. After thinning, “reach-through” vias are used to connect circuits on
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Figure 1. RPI wafer bonding and via process. the two wafers. The stacking can continue with additional wafers. All processing is sequential. An example of a back to face process is the Fraunhofer IZM Vertical System Integration (VSI) process shown in Figure 2 [3].
Figure 2. Fraunhofer VSI wafer process. In this case a handle wafer is attached to the upper wafer front surface, and then the back surface is thinned before attachment. In a similar process developed at MIT Lincoln Labs [4], SOI wafers are used and the backside silicon is etched using the buried oxide layer as an etch stop. An advantage of that process is that the via is made only through the SiO2, so that no additional insulation is required, as is the case if the via goes through silicon.
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2007 Electronic Components and Technology Conference
In all of these wafer attachment processes, extremely small (~ 2 µm diameter) vias can be fabricated through the thin (
