Integration of metallic source/drain (MSD) contacts in nanoscaled CMOS technology Mikael Östling*, Jun Luo, Valur Gudmundsson, Per-Erik Hellström, and B. Gunnar Malm School of Information and Communication Technology, Royal Institute of Technology (KTH), Electrum 229, SE-164 40 Kista, Sweden, *E-mail:
[email protected] Abstract An overview of metallic source/drain (MSD) contacts in nanoscaled MOSFET technology is provided in this paper. MSD contacts offer several benefits for nanoscaled CMOS, i.e., extremely low S/D parasitic resistance, abruptly sharp junctions between S/D and channel and preferably low temperature processing. In order to achieve high performance MSD MOSFETs, many design parameters such as Schottky barrier height (SBH), S/D to gate underlap, top Si layer thickness, oxide thickness and so on should be optimized. Recently, a lot of efforts have been invested in MSD MOSFETs based on Pt- and Ni-silicide implementation and several promising results have been reported in literature. The experimental work as well as the results of Monte Carlo simulations by this research team and by other research teams is discussed in this paper. It will be shown that the present results place MSD MOSFETs as a competitive candidate for future generations of CMOS technology. 1. Introduction The future demands on ultra scaled MOSFETs are very challenging. The 2009 edition of the technology roadmap ITRS [1] predicts that alternative device structures, such as ultra-thin-body silicon on insulator (UTB-SOI) or FinFET, will eventually be needed in order to control the ever-deteriorating short channel effects (SCEs). The thickness of top Si layer (tSi) of UTB-SOI substrates will have to be shrunk to few nm in order to achieve desired device performance. Consequently, the required ultra-shallow S/D junction
depth and the limitation of dopant solubility, however, indicate that the S/D parasitic resistance is almost a show stopper for conventional MOSFETs with highly doped S/D. In table I, the required contact resistivity and S/D sheet resistance for MOSFETs formed on fully depleted SOI (FD-SOI) substrates in accordance with the ITRS are summarized. How to achieve such low max contact resistivity and S/D sheet resistance is a real challenge. Recently, MSD MOSFETs have been extensively studied as a promising replacement of conventional highly doped source/drain (S/D) MOSFETs for sub-30 nm CMOS technology [2]-[4]. Metal silicides are of particular interest as the MSD material as a result of the
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Table I ITRS 2009: Focus on source/drain for FDSOI substrate Year of production
2015
2016 2017 2018 2019 2020 2021
Technology node (nm)
22
20
17.7
15.7
14.0 12.5
11.1
Physical gate length (nm)
17
15
14
12.8
11.7 10.7
9.7
Max contact resistivity for FDSOI (10-8 :cm2)
4.0
2.0
1.0
0.8
0.7
0.5
Max S/D extension sheet resistance for FDSOI (: :/sq)
730
752
809
890
983 1104 1199
0.6
self-aligned silicide (SALICIDE) process, low parasitic S/D series resistance and so on. Among the suitable silicides, PtSi and NiSi are exceptionally favorable due to their low resistivity, low Si consumption (1.28 and 1.83 nm-thick Si consumed per nm of Pt, Ni), and low thermal budget (500-600 oC) during silicidation [5], [6]. Although the parasitic S/D resistance of a MSD MOSFET is greatly reduced, the intrinsic large Schottky barrier heights (SBH) of most silicides, limit the device performance. Furthermore, to simplify CMOS fabrication, a desirable silicide giving low SBHs for both n- and p-type polarities would be the ultimate solution. Since no silicide fulfills this requirement, the SBH engineering technique is therefore needed. This paper mainly deals with MSD MOSFETs in the following aspects; in section 2, a design approach to achieve high performance MSD MOSFETs is first addressed. A discussion on the SBH engineering and device fabrication with PtSi and NiSi as MSD follows in Section 3. Section 4 concerns both the performance of MSD MOSFETs and the comparison between MSD MOSFETs and conventional MOSFETs by advanced simulation. 2. Design of high performance MSD MOSFETs Various issues concerning the design are required to be optimized in order to achieve MSD MOSFET with sufficient performance, according to Table 1. Details will be discussed with the assistance of a cross-sectional
transmission electron microscope (TEM) image along with the key design parameters of a MSD-MOSFET in Fig. 1 (a). The energy band diagram of a p-type MSD MOSFET at “on state” mode is also shown in Fig. 1(b) in order to facilitate the understanding of the operation principles.
Vg=-Vdd
Vds=-Vdd
Fig. 1. (a) Cross-sectional TEM of a PtSi MSD MOSFET formed on UTB-SOI [19], the key design parameters are also shown; (b) Band diagram of the device at “on-state”. For a high performance MSD MOSFET, the utmost important parameter is the SBH at the source, since the contact between the source and the channel is characterized by a Schottky junction instead of a p-n junction of conventional MOSFET. Simulation studies indicate that the effective SBH has to be smaller than 0.1 eV in order to outperform conventional MOSFETs [7]. The simulation results in section 4 of this paper also support this assumption. The main transport mechanism of MSD MOSFETs is by tunneling through the SB, in the on-state, though drift-diffusion will dominate if the SB becomes thin enough. Since lower SBH leads to thinner SB width at the source, the tunnel probability increases exponentially as SBH is decreased. As a result, the on-current of MSD MOSFETs is greatly enhanced by reducing the SBH. Another parameter that strongly affects the performance of MSD MOSFETs is the underlap (WUL) between the S/D fronts and the channel. The existence of a large WUL, arising from non-optimized silicidation process, not only leads to a drastically increased parasitic
channel resistance, but also results in a poor gate control over the underlap regions below spacers. For a high performance MSD MOSFET, WUL must be avoided, hence requires a precise control of the silicidation process. If the precision in the silicidation process is not accurately adjusted, either WUL or the overlap (WOL) will take place. The effect of WOL, on the other hand, will cause significant gate leakage. Other parameters such as the gate length (Lg), the thicknesses of SOI (tsi) and gate oxide (tox) as shown in Fig.1 (a) also have impact on the device performance mainly by affecting the width of SB at the source. For a MSD MOSFET with small Lg, the penetration of drain potential will lead to a thinner SB width at the source which is called drain induced barrier thinning (DIBT) [8]. For a MSD MOSFET with thin tox or high-k gate dielectrics, the SB width at the source is also thinned by the enhanced gate control. The reduction of tSi, once again, lead to a thinned SB width and minimized short channel effects. All these parameters can be optimized in the design of a MSD MOSFET in order to achieve high performance. As for the gate material; instead of traditional Poly-gate, metal gate (MG) with proper work function for both n- and p-type devices should also be implemented for the purpose of high performance MSD MOSFETs. The employment of MG in traditional MOSFETs has been shown to substantially improve the device performance. Because of the low temperature process when fabricating MSD MOSFETs, the integration of MG in MSD MOSFETS is well-adapted and completely feasible. Novel device structures, such as double gate, tri-gate and gate all-around devices, are other attempts to improve the gate control in the channel by enhanced thinning the SB width at the source. Thanks to the additional SB thinning from 3D effects, a 5-nm gate all-around NiSi MSD MOSFET with superior device performance has been reported [9]. 3. SBH engineering and device fabrication SBH engineering is necessary when we use the aforementioned promising silicides PtSi, NiSi or NiPtSi for MSD MOSFETs, since the intrinsic SBH to electrons (Ibn) is large for PtSi and the SBHs to both electrons and holes (Ibp) are large for NiSi [10-11]. Many techniques, such as surface passivation, alloying, silicidation induced dopant segregation (SIDS), and silicide as dopant source (SADS), have been proposed to engineer the intrinsic large SBHs of silicides [12]. Among them, SADS is a reproducible and CMOS process compatible way. In our previous study, the SBHs of PtSi and NiSi for both electrons and holes have been successfully modified to a0.1 eV by SADS. Besides, the
effects of C and N on the SBHs of NiSi are also investigated, which are summarized in Fig. 2 (a) and (b).
(a)
(iii)
4. Device and simulation results Fig. 3. shows the IDS-VGS characteristic of an n-type PtSi MSD MOSFET of LG= 90 nm with and without As DS. The IDS-VGS characteristic is successfully transformed from p-type without DS to typical n-type behavior with As DS.
Ref. 1·1015 cm-2 C 5·1015 cm-2 C 1·1015 cm-2 N 5·1015 cm-2 N
1.0
Ibn (eV)
(ii)
It is found that both C and N themselves take part in the modification of SBHs but they have each different roles. The C implantation causes a substantial increase in SBHs for electrons (i.e., carbon moves the effective work function closer to the valance band) while the N implantation causes an observable decrease in SBHs for electrons (i.e., nitrogen moves the effective work function closer to the conduction band). Furthermore, with B and As DS, it is found that the presence of both C and N yields positive effects in helping reduce the effective SBHs to 0.1-0.2 eV for both conduction polarities [12], [13]. After managing a successful SBH engineering scheme, the next step is to implement and fabricate MSD MOSFETs with low SBHs at the source. The fabrication process is described in Fig. 2 (c). Lightly doped p-type SOI wafers with a 150-nm-thick Si on top of a 400-nm-thick buried oxide were used as the starting material. The surface Si was thinned down to about 20 nm by several cycles of thermal oxidation and subsequent SiO2 removal in dilute hydrofluoride (HF) solution. After the formation of a MESA structure, a 3-nm-thick gate oxide was grown by dry oxidation. This was followed by the deposition of a 120-nm-thick in situ phosphorous doped poly-Si as the gate electrode material. An I-line stepper was employed to define gate lengths LGt0.3 Pm. A sidewall transfer lithography (STL) technology was used [14], [15] to fabricate devices of LG=55 nm. After the formation of a slim 15-nm wide spacer, either a Ni or Pt SALICIDE process is performed to form NiSi/PtSi MSD. B or As is then implanted into as-formed NiSi/PtSi. Upon a drive-in annealing, B or As segregates at the interface between NiSi/PtSi and Si which leads to the SBH modification. The device fabrication was completed with Al metallization followed by forming gas annealing at 400 oC for 30 min.
0.8
0.6
Schottky Barrier Height (eV)
450
1.0
500
550
600
Silicidation Temperature ( oC)
650
Ec
(b) B As Ref. 1·1015 cm-2 C 5·1015 cm-2 C 1·1015 cm-2 N 5·1015 cm-2 N
0.8 0.6 0.4 0.2 0.0
500
550
600
650
700
Drive-in Temperature ( oC)
750
Ev
(c) Thinning SOI wafers
(i)
Form MESA structure SiO2/Poly-Si deposition 15 nm spacer formation Ni/Pt deposition NiSi/PtSi formation (a) B/As ion implantation (b) Drive-in annealing (c) Metallization Forming-gas annealing Fig. 2. (a) Effects of C and N on the SBH tuning of NiSi, (b) Effects of C and N on the SBH tuning of NiSi by DS, and (c) Process flow for the fabrication of MSD MOSFETs (left), and a low-temperature SADS technique to tune SBHs for PtSi and NiSi (right).
Fig. 3. IDS–VGS for a UTB MSD MOSFET of LG = 90 nm with and without As I/I for DS. The arsenic dose is 5 · 1015 cmí2. A p-type device without DS is turned to an n-type one by As DS [14].
SS= 126 mV/ dec
Id (PA/Pm)
1032 (a) SS=164 mV/dec 101 Vd=1.2 V 100 10-1 10-2 10-3 10-4 10-5 10-6 Vd=0.1 V 10-7 As DS 10-8 No As DS 10 -2 -1 0 1 2
since the drive current is significantly limited by the injection at the SB of the source, regardless of scattering, the performance is poor.
VG (V)
Id (PA/Pm)
dec mV/ 134 SS=
1021 100 10 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8
(b)
SS=175 mV/dec
Vd=-0.1 V with B DS No B DS -2 -1 0
Vd=-1.2 V
VG (V)
1
2
Fig. 5. Simulated ID-VG characteristics for VDS=1 V [17].
Fig. 4. Id-VG for UTB-SOI (a) n-type MSD MOSFET with and without As DS, and (b) p-type MOSFET with and without B DS [16]. Fig. 4 shows the Id-VG characteristics of both n(Fig.4a) and p-type (Fig. 4b) NiSi MSD MOSFETs of LG=55 nm with and without As and B DS. The current is normalized to the width of the devices. Without B or As DS, the control device shows the typical ambipolar behavior, and this behavior is attributed to the large Schottky barrier height (SBH) of NiSi to both electrons (Ibn) and holes (Ibp) since the work function of NiSi lies close to the middle of Si energy bandgap. With As or B DS, it is apparent that the Id-VG characteristics are altered successfully from ambipolar to n-type or p-type behavior respectively [16]. However, as MSD MOSFET technology progresses to smaller dimensions, it is necessary to understand the performance of future nodes. Conventional drift-diffusion models cannot be used since the transport is far from equilibrium. To understand transport in nanoscaled MSD MOSFETs, the multi-subband Monte Carlo (MSMC) method has recently been used to study the performance of MSD MOSFETs compared to conventional highly doped S/D MOSFETs [17]. In that study, an effective potential method was used as a simple way to treat tunneling in the SB contacts. Fig. 5 shows the simulated ID-VG characteristics of a MOSFET with LG=32 nm , tSi=7 nm, and EOT =1.2 nm, using either highly doped S/D or MSD. The results show MSD MOSFETs can provide drive current similar to the one of highly doped S/D MOSFETs only if SBH is less than 50 meV. Furthermore, Fig. 6 shows that devices with large SBHs operate closer to the ballistic limit, but
Fig. 6. Ballistic ratio ION/IBL for VG=VD=1 V computed by comparing fully ballisctic simulations with simulations with scattering activated [17].
5. Conclusions The issues concerning the integration of metallic source/drain (MSD) contacts in nanoscaled CMOS technology are presented in this paper. A guideline for designing high performance MSD MOSFETs is provided. Many parameters such as SBH, WUL or WOL, tSi and tox, etc., can and must be optimized in order to achieve high performance. SADS was adopted to engineer the SBHs of PtSi and NiSi for both conduction polarities successfully. The effects of both C and N on the SBH engineering of NiSi by DS are discussed and experimentally displayed. Following the design guidance and successful
engineering of SBH, both PtSi and NiSi MSD MOSFETs are fabricated in KTH which demonstrate reasonable device performance. Meanwhile, the results of Monte Carlo simulation, together with the latest experimental results from other research groups, indicate that MSD MOSFETs present promising device architecture implementation in extremely scaled CMOS technology.
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Acknowledgments
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This work was supported by the EU Network of Excellence NANOSIL and the Swedish Foundation for Strategic Research (SSF) Nanoelectronic MOSFET program. Funding from the European Research Council ERC Advanced Researcher grant OSIRIS (MÖ) is greatly acknowledged. References [1] International Technology roadmap for Semiconductor (ITRS), 2009 update, http://public.itrs.net/ [2] J. M. Larson and J. P. Snyder, IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1048-1058, May. 2006. [3] M. Fritze, C. L. Chen, S. Calawa, D. Yost, B. Wheeler, P. Wyatt, C. L. Keast, J. Snyder, and J. Larson, IEEE Electron Device Lett., vol. 25, no. 4, pp. 220-222, Apr. 2004. [4] J. Kedzierski, P. Xuan, E. H. Anderson, J. Bokor, T. J. King, and C. Hu, in IEDM Tech. Dig., 2000, pp. 57-60. [5] C. Lavoie, F. M. d’Heurle, and S.-L. Zhang, in Handbook of Semiconductor Manufacturing Technology, 2nd Edition, edited by Y. Nishi, and R. Doering [6] S.-L. Zhang and U. Smith, J. Vac. Sci & Technol. A, vol. 22, Issue 4, pp. 1361-1370, Jul. 2004. [7] S. Xiong, T.-J. King and J. Bokor, IEEE Trans. Electron Devices, 52, p.1859 (2005)
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