Intel Presentation Template Overview

TSD Towards Complete Embedded System Modeling and Generation Dr.-Ing. Klaus Uhl Dr.-Ing. Kay-Ulrich Scholl Intel Corporation, GENIVI Charter Member GENIVI 14th All Member Meeting, Paris, April, 28th, 2016

Overview The present

• Component modeling and code generation • Intel demo system The future • System modeling and code generation • Data streaming 2

TSD

Component Modeling and Code Generation

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Motivation for a component generator Most components share common patterns of code  Configuration parameter processing  IPC initialization  Interface instantiation  Consolidate information from multiple interfaces  etc.

Manually maintaining this code is tedious and error-prone

Code generation helps to  Find bugs in the generated code faster because the same code is used in many components

 Fix bugs simultaneously in many components by just updating the generator  Roll out implementation improvements or adpations to API changes simultaneously to many components by just updating the generator 4

TSD

Intel Component Generator Features  Component startup and shutdown handling  Trigger other generators depending on the component definition

 Configuration parameter handling

 Communication interface instantiation and initialization  Multiple channels  Multiple IPC mechanisms

 Event and worker thread initialization  Forwarding of calls from multiple interfaces to a single handler class  DLT application and context registration  Link to GENIVI lifecycle 5

TSD

Example

package calculator.example.server import calculator.example.* from "Calculator.fidl" module CalculatorServer { dlt context use parent; communication channel mainChannel; provides interface Calculator calculator on mainChannel; } component CalculatorServerApp { dlt app id ICES "Calculator Example Server“; dlt context _CSC "Calculator Server Context“; contains CalculatorServer calculatorServer communication channel MainBus { type UFIPC; maps to calculatorServer.mainChannel; } event thread mainThread { processes MainBus; } use genivi_lifecycle; }

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Example

package calculator.example.server import calculator.example.* from "Calculator.fidl"

 Change only the type of a communication channel

module CalculatorServer { dlt context use parent; communication channel mainChannel; provides interface Calculator calculator on mainChannel; } component CalculatorServerApp { dlt app id ICES "Calculator Example Server“; dlt context _CSC "Calculator Server Context“; contains CalculatorServer calculatorServer calculatorServer; communication channel MainBus { type UFIPC; Dbus; maps to calculatorServer.mainChannel; } event thread mainThread { processes MainBus; } use genivi_lifecycle; }

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Example

package calculator.example.server import calculator.example.* from "Calculator.fidl"

 Change only the type of a communication channel  Component generator instructs the build system to  Generate different proxy and stub adapters  Link against a different IPC binding runtime library

module CalculatorServer { dlt context use parent; communication channel mainChannel; provides interface Calculator calculator on mainChannel; } component CalculatorServerApp { dlt app id ICES "Calculator Example Server“; dlt context _CSC "Calculator Server Context“; contains CalculatorServer calculatorServer; communication channel MainBus { type Dbus; maps to calculatorServer.mainChannel; } event thread mainThread { processes MainBus; } use genivi_lifecycle; }

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ICDL Workflow Intel CDL

references

Intel Component Generator

Component Startup/Shutdown

IPC Runtime Libraries

Interface Initialization

Common API Runtime Library

GENIVI Lifecycle Integration Compiler/ Linker

triggers Common API Generator

Common API

IPC Binding Generators

IPC Bindings

SW Component

Franca IDL Libraries required by the component logic

uses State Machine Model

State Machine Generator

State Machine Implementation

extends

Component Logic

Generator Manually written code

State Machine Integration

Reduce the amount of manually maintained code

Model generated code 9

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Intel Demo System

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System Architecture  Multiple UI runtimes possible (GUI, Cluster, Speech, etc.)  Inter-process communication API defined by Franca IDLs

Presentation Layer

System Logic Layer

 API syntax is UI runtime specific Middleware Layer

IVI GUI

A

BC

...

External Application

Controller B

...

Controller X

B

Controller A

Audio

Cluster GUI

Media

Phone

...

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X

TSD

Code generation on all layers

Common API Stub

State Chart Generator

State Machine

Component Generator

Component Logic

Common API Generator

Common API proxy

Interface Definition

Common API Generator

Common API Stub

State Chart Model

State Chart Generator

State Machine

Model

Component Definition

Component Generator

generated code

Service

Common API Generator

Controller

Common API Proxy

HMI

Manually written code

Common API to Qt

Common API Generator

Interface Definition State Chart Model Component Definition

Generator

QML Objects

QML

Common API Qt Generator

Visualization

Component Logic

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System Modeling and Code Generation

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Vision – Code Generation

System architect can quickly re-configure, re-build and redeploy a complete system

System Model Abstract System Structure Scheduling Constraints

Safety Requirements

Actual Hardware Resources Actual Operating Systems Implementation Variants

Test and Verification Requirements ...

Abstract model

Hardware Dependent Resource Consumption

Generated

Security Configurations

Safety Configurations

Scheduling Configurations

Deployment

Component Implementation

Maintained by Developer

...

Test and Validation Support

Generators Generator Code Generator

Interface Implementation

Component Configurations

IPC Binding 14

TSD

Vision – Model Analysis

...

System Model Abstract System Structure Scheduling Constraints

Safety Requirements

Actual Hardware Resources Actual Operating Systems Implementation Variants

Test and Verification Requirements ...

Abstract Model

Hardware Dependent Resource Consumption

Deployment

Model Analysis Model Tool Analysis Model Tool Analysis Tool

Missing Constraints V-Model Traceability

Code Generation Properties

Check model completeness

Analyse Resource Consumption

Analyse Communication Patterns

Optimize Scheduling Evaluate Trade Studies 15

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Facilitate Technology Reuse  Link system model entities to models that are defined in other languages

System Model

Model Transformation

 Extend the system model to subsume the external models  Re-use existing code generators

Intermediate Model

 Export external models from system model on the fly during code generation if possible  Use import/export only if needed

Existing Code Generator

 Only implement new code generators if no usable alternative exists Generated Code

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System Modeling and Generation Approach SysML

Franca Profile

ICDL Profile

Systemd Profile

Data Streaming Profile

Scheduling Profile

YAMAICA-EA

ICDL Connector

Systemd Generator

Data Streaming API Generator or Connector

RTOS Scheduling Generator

Franca IDL

Component Definition

Systemd Service File

Data Streaming Code

RTOS Scheduling Configuration

UML

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Intel Demo System Example

Model Generated model Generated code

Common API Proxy

Common API Generator

Common API Stub

State Chart Generator

State Machine

Component Generator

Component Logic

Common API Generator

Common API proxy

Interface Definition

Common API Generator

Common API Stub

State Chart Model

State Chart Generator

State Machine

Component Definition

Component Generator

Interface Definition State Chart Model Component Definition

Service File Container Config

Service File Container Config

Component Logic

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Service

Manually written code

Common API Generator

Container Config

Controller

Generator

Generator / Generator / Transformation Generator / Transformation Transformation

Common API to Qt

Service File

HMI

System Model

QML Objects

QML

Common API Qt Generator

Visualization

TSD

Data Streaming

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Data Streaming Data synchronization

• •

input queuing

•

processing trigger C&C

Sensor A

A B

Sensor B

•

Algorithm command & control

•

Scheduling •

Real-time constraints

•

High frequency algo might process multiple steps at once C&C

Algo

Proc: on A and B Out: every proc

C&C

A B

Sensor C

A

Algo

Proc: on B, queue A Out: every proc

Decoder

Proc: on A Out: sporadic

Far more complex than command & control

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Differences to CommonAPI Franca/CommonAPI

Data Streaming API

Client/server communication model

Publish/subscribe communication model

• • •

Attributes Remote function calls with return value Events with subscription

• •

No attributes required No remote function calls required

Only one IPC mechanism per interface supported

Multiple IPC mechanisms per interface required

Mostly low-frequency transfer of small data chunks

High-frequency mass data streaming

Scheduling policy definition left to the IPC binding implementation

Scheduling policy definition API required

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Processing Trigger

Challenge 1: Optimized data driven scheduling

Queued Dropped

C&C

Sensor A A

Sensor B

B

Activity

Proc: on A Out: every proc

C&C

Sensor A A

Sensor B

B

Activity

Proc: on B, min jitter Out: every proc

C&C

Sensor A A

Sensor B

B

Activity

Proc: on B, min jitter, queue on A Out: every proc 22

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Challenge 2: Efficient multi-binding support  Activities / algorithms can be implemented using different technologies, e.g.

Activity CPU, C++

 C++ on CPU for decision steps  OpenVX graph on CPU, GPU, image processing accelerator or a mix of these for massively parallel image processing

Activity

Activity OpenVX

 Custom accelerator code for highly optimized accelerator usage

 Streaming data from a single producer has to be forwarded to multiple consumers inside the same process using different transport technologies

Reduce copy operations to the technical limit (zero-copy if possible)

Activity Custom Accelerator

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