energies Article
Interleaved High Step-Up DC-DC Converter Based on Voltage Multiplier Cell and Voltage-Stacking Techniques for Renewable Energy Applications † Shin-Ju Chen 1, * Meng-Jie Shen 1 1 2
* †
ID
, Sung-Pei Yang 2
ID
, Chao-Ming Huang 1 , Huann-Ming Chou 2 and
Department of Electrical Engineering, Kun Shan University, Tainan 710, Taiwan;
[email protected] (C.-M.H.);
[email protected] (M.-J.S.) Green Energy Technology Research Center, Kun Shan University, Tainan 710, Taiwan;
[email protected] (S.-P.Y.);
[email protected] (H.-M.C.) Correspondence:
[email protected]; Tel.: +886-6-205-0323; Fax: +886-6-205-0298 This paper is extended version of paper published in Shin-Ju Chen, Sung-Pei Yang, Chao-Ming Huang, Huann-Ming Chou, Meng-Jie Shen. Interleaved high step-up DC-DC converter based on voltage multiplier cell and voltage-stacking techniques for renewable energy applications. In proceedings of 2018 IEEE International Conference on Applied System Innovation (IEEE ICASI 2018), Chiba, Tokyo, Japan, 13–17 April 2018.
Received: 30 May 2018; Accepted: 20 June 2018; Published: 22 June 2018
Abstract: A novel interleaved high step-up DC-DC converter based on voltage multiplier cell and voltage-stacking techniques is proposed for the power conversion in renewable energy power systems. The circuit configuration incorporates an input-parallel output-series boost converter with coupled inductors, clamp circuits and a voltage multiplier cell stacking on the output side to extend the voltage gain. The converter achieves high voltage conversion ratio without working at extreme large duty ratio. The voltage stresses on the power switches are significantly lower than the output voltage. As a result, the low-voltage-rated metal-oxide-semiconductor field-effect transistors (MOSFETs) can be employed to reduce the conduction losses and higher conversion efficiency can be expected. The interleaved operation reduces the input current ripple. The leakage inductances of the coupled inductors act on mitigating the diode reverse recovery problem. The operating principle, steady-state analysis and design guidelines of the proposed converter are presented in detail. Finally, a 1-kW prototype with 28-V input and 380-V output voltages was implemented and tested. The experimental results are presented to validate the performance of the proposed converter. Keywords: high step-up DC-DC converter; interleaved operation; coupled inductor; voltage multiplier cell
1. Introduction Nowadays, demand for clean or renewable energy sources has dramatically increased with population growth and the depletion of fossil fuel. Much effort has been made to explore renewable energy sources, such as photovoltaic (PV), fuel cell and wind energy systems [1–3]. The renewable energy grid-connected system with PV and fuel cells calls for high voltage-gain and high-efficiency dc-dc converters because the low voltage generated by the PV and fuel cells needs to be raised to a high voltage for the input of grid-connected inverter as shown in Figure 1. If the energy needs to be converted to a single-phase 220 V ac voltage utility grid, a 380–400 V dc bus voltage is required for the inverter. However, the outputs of PV and fuel cells are generally lower than 40 V [4] due to safety and
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reliability considerations in home applications. Thus, a front-end DC-DC converter with about ten times voltage necessary Energies 2018, 11, gain x FORis PEER REVIEWto satisfy the requirement. 2 of 16 Low DC Voltage Renewable Energy Sources PV Panels/Fuel Cells
High Voltage DC Bus High Step-Up DC/DC Converter
DC/AC Inverter
Load or Grid
Figure system. Figure 1. 1. Diagram Diagram of of aa renewable renewable energy energy power power system.
In order to achieve high voltage gain, a conventional boost converter or an interleaved boost In order to achieve high voltage gain, a conventional boost converter or an interleaved boost converter can be employed with operating an extreme large duty ratio. However, it causes several converter can be employed with operating an extreme large duty ratio. However, it causes several problems of high switching losses, severe output diode reverse-recovery losses, and electromagnetic problems of high switching losses, severe output diode reverse-recovery losses, and electromagnetic interference (EMI) [5]. Furthermore, for a high output-voltage converter, therefore, the high-voltageinterference (EMI) [5]. Furthermore, for a high output-voltage converter, therefore, the high-voltage-rated rated MOSFETs and diode with large conduction resistance are necessary due to the voltage stresses MOSFETs and diode with large conduction resistance are necessary due to the voltage stresses on the on the power devices are equal to the output voltage. It will result in large conduction and switching power devices are equal to the output voltage. It will result in large conduction and switching losses. In losses. In practice, the voltage gain of boost converters is limited due to the parasitic parameters effect practice, the voltage gain of boost converters is limited due to the parasitic parameters effect [5]. These [5]. These problems are the main limitations of disadvantages for the boost converters. problems are the main limitations of disadvantages for the boost converters. In the literature, a lot of converter topologies have been proposed to obtain high step-up voltage In the literature, a lot of converter topologies have been proposed to obtain high step-up voltage gain [6–22]. For coupled inductor-based converters [6–10], the high voltage gain can be achieved by gain [6–22]. For coupled inductor-based converters [6–10], the high voltage gain can be achieved by adjusting the turns ratio of the coupled inductor and duty ratio. However, the power loss and high adjusting the turns ratio of the coupled inductor and duty ratio. However, the power loss and high voltage stress on the power switches occur owing to the leakage inductance of the coupled inductor. voltage stress on the power switches occur owing to the leakage inductance of the coupled inductor. The switched-capacitor converters [11,12] can also obtain high voltage conversion ratio. However, The switched-capacitor converters [11,12] can also obtain high voltage conversion ratio. However, many switches are required for these converters, and thus it leads to complexity of design for the many switches are required for these converters, and thus it leads to complexity of design for the driving circuit. The high step-up converters without a coupled inductor or transformer are proposed driving circuit. The high step-up converters without a coupled inductor or transformer are proposed in [13,14]. Several kinds of interleaved high step-up converters with voltage multiplier cells have been in [13,14]. Several kinds of interleaved high step-up converters with voltage multiplier cells have been proposed in [15–19]. The interleaved converters with three-winding coupled inductors are proposed proposed in [15–19]. The interleaved converters with three-winding coupled inductors are proposed to achieve high voltage conversion ratio and low input current ripple [20–22]. However, they are a to achieve high voltage conversion ratio and low input current ripple [20–22]. However, they are a little complex and difficult to design, which results in the circuit complexity and cost problems. little complex and difficult to design, which results in the circuit complexity and cost problems. A novel interleaved high step-up converter based on voltage multiplier cell and voltage-stacking A novel high step-up based voltage multiplier cell and voltage-stacking techniques is interleaved proposed herein for highconverter voltage gain andonhigh-power applications, as shown in Figure techniques is proposed herein for high voltage gain and high-power applications, as shown in Figure 2a. 2a. The topology utilizes the two-phase interleaved boost converter with parallel-input series-output The topology the two-phase interleaved boost converter with parallel-input series-output connection andutilizes introduces dual clamp circuits and a voltage multiplier cell stacking on the output connection and introduces dual clamp circuits and a voltage multiplier cell stacking on the output side side to obtain the higher voltage conversion ratio. The converter has the following features: to obtain the higher voltage conversion ratio. The converter has the following features: (1) The converter has high step-up voltage gain without operating at extreme large duty ratio. (1) Thevoltage converter hason high voltage gain without operating at extreme large duty ratio. (2) The stress thestep-up power switches is significantly lower than the output voltage. The low(2) voltage-rated The voltage stress on the with powerlow switches is significantly lower than the outputtovoltage. MOSFETs on-resistances can thereby be adopted reduce The the low-voltage-rated MOSFETs with low on-resistances can thereby be adopted to reduce the conduction losses. conduction losses. (3) The diode reverse-recovery problem can be alleviated by the leakage inductances of the coupled (3) inductors The diodefor reverse-recovery problem can be alleviated by the leakage inductances of the coupled most of the diodes. inductors for most the diodes. (4) Dual passive clampofcircuits help to recycle the leakage energy of the coupled inductors and the voltage of the switches to a lower level. (4) clamp Dual passive clampstress circuits helppower to recycle the leakage energy of the coupled inductors and clamp (5) The input current reduces is minimized to the current ripple cancellation in the the voltage stress ofripple, the power switches to a lowerdue level. Additionally, powerdue level increased duecancellation to the current(5) interleaved The input operation. current ripple, reduces increases is minimized tocan thebecurrent ripple in sharing performance in high current applications. the interleaved operation. Additionally, increases power level can be increased due to the current-sharing performance in high current applications. This paper is organized as follows. The proposed converter and its operating principle are illustrated in Section 2. The steady-state design guidelines of This paper is organized as follows.analysis, The proposed converter and andperformance its operatingcomparison principle are the proposed converter are presented in Section 3. The experimental results on a 1000 W prototype illustrated in Section 2. The steady-state analysis, design guidelines and performance comparison of circuit are provided to validate the performance converter in Section 4. Finally, some the proposed converter are presented in Sectionof 3.the Theproposed experimental results on a 1000 W prototype conclusions are made in the last section.
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circuit are provided to validate the performance of the proposed converter in Section 4. Finally, some 2. Proposed Converter and Operating Principle conclusions are made in the last section. The proposed converter circuit is shown in Figure 2a, where S1 and S 2 are the power switches, 2. Proposed and Operating D and D Converter are the clamp diodes, CPrinciple and C are the clamp capacitors, D and D are the C1
C2
C1
C2
1
2
C1 and C2 arecircuit D4 Sare C3 and the output capacitors, theSswitched output diodes, The proposed converter is shown in FigureD32a,and where power switches, 2 are the diodes, 1 and D and D are the clamp diodes, C and C are the clamp capacitors, D and D are the output C4C1are the switched capacitors, and RC1 There are two coupled inductors in 2 the proposed 1 C2 C2 o is the load. diodes, C1The andcoupling C2 are the output capacitors, D3by and are“the diodes, are the 3 and ∗ ”. switched ” 4and The circuit modelCof eachC4coupled converter. references are marked “ D switched capacitors, and R is the load. There are two coupled inductors in the proposed converter. The inductor includes an idealo transformer with the original turns ratio, which is in parallel with a coupling references are marked by “in·”series and “∗with ”. The circuit model of eachThe coupled inductor includes an magnetizing inductance and then a leakage inductance. equivalent circuit of the ideal transformer with the original turns which in parallel with magnetizinginductance, inductance and Lm1 isand Lm 2 are Lk 1 proposed converter is shown in Figure 2b,ratio, where the amagnetizing then in series with a leakage inductance. The equivalent circuit of the proposed converter is shown in and Lk 2 are the inductance, N p and N s are the primary and secondary windings of the coupled Figure 2b, where Lm1 and Lm2 are the magnetizing inductance, Lk1 and Lk2 are the inductance, Np and inductors, respectively, and the turns ratio of the coupled inductor is defined as n = N s1 / N p1 Ns are the primary and secondary windings of the coupled inductors, respectively, and the turns ratio N p 2 . Theinductor = Nthe dual passive clampas circuits used to recycle the leakage energy and suppress the of is defined n = Nare s 2 / coupled s1 /Np1 = Ns2 /Np2 . The dual passive clamp circuits are usedoff to voltage recycle spikes the leakage suppress turnmultiplier off voltagecell spikes on theby power switches. turn on theenergy power and switches. The the voltage is realized the secondary The voltage cellinductors is realizedwith by the secondary windings of the coupled inductors series windings of multiplier the coupled series connection, the switched diodes and thewith switched connection, switched diodes and the switched capacitors to increase the voltage gain. capacitors tothe increase the voltage gain. Voltage multiplier cell D4
C4
D4 *
*
N p1
N s1
Ns2
D3
DC1
+ Vin −
CC1
S1
C3
(a)
+ Ro Vo −
D2
Clamp circuit
S2
CC 2 DC 2
Lm1
*
N p2
iin
C4
C2
C1 D1
N p1 Lm 2
N p2
Lk1
Lk 2
DC1
iin
N s1
Ns2 *
D3
C3 + Ro Vo −
D2
C2
+ Vin −
CC1
S1
S2
CC 2 DC 2
C1 D1
(b)
Figure 2. Proposed converter and its equivalent circuit. (a) Proposed converter; (b) Equivalent circuit. Figure 2. Proposed converter and its equivalent circuit. (a) Proposed converter; (b) Equivalent circuit.
In the operational analysis, the proposed converter operates in continuous conduction mode In the analysis, proposed converter operates with in continuous conduction mode (CCM), andoperational the gate signals of thethe power switches are interleaved the same duty ratio greater (CCM), and the gate o signals of the power switches are interleaved with the same duty ratio greater than 0.5 and a 180◦ phase shift. The key waveforms are shown in Figure 3. There are six operating than 0.5 and a 180 phase shift. The key waveforms are shown in Figure 3. There are six operating modes in one switching period. The equivalent circuits for each mode are shown in Figure 4. modes in one switching period. The equivalent circuits for each mode are shown in Figure 4. Mode 1 [ t0 , t1 ]: At t = t0 , the power switch S1 is turned on, and the power switch S 2 remains Mode 1 [t0 , t1 ]: At t = t0 , the power switch S1 is turned on, and the power switch S2 remains in the turn-on state. The leakage current iLk 1 rises quickly and its increasing rate is limited by Lk 1 . in the turn-on state. The leakage current i Lk1 rises quickly and its increasing rate is limited by Lk1 . still transfers transfers energy energy to to the The m1 still The magnetizing magnetizing inductance inductance LLm1 the secondary secondary side side of of the the coupled coupled inductors inductors DCC1 DC2 diodes are reverse-biased, reverse-biased, and charging chargingthe theswitched switchedcapacitor capacitorCC3 3. .The The diodesDD D D4 4,, D and D and 1 , 1 ,D 2 ,2 , D 1 and C 2 are D is conducting as shown in Figure 4a. The current falling rate through only the switched diode only the switched diode D33 is conducting as shown in Figure 4a. The current falling rate through the switched diode D3 isDcontrolled by the leakage inductances Lk1 and alleviates the diode Lk 1 Land Lk 2 , which alleviates the the switched diode k2 , which 3 is controlled by the leakage inductances reverse recovery problem. This mode ends when the current through the diode D decreases to zero at 3 D3 decreases diode reverse recovery problem. This mode ends when the current through the diode the instant t , and the diode D3 is turned off automatically. At the same time, the current through Lk1 diode D3 is turned off automatically. At the same time, the current to zero at the1 instant t1 , and the becomes equal to that of the magnetizing inductance Lm1 . through Lk 1 becomes equal to that of the magnetizing inductance Lm1 . Mode 2 [t1 , t2 ]: During the time interval, both the switches S1 and S2 conduct, and all diodes S1 and SL2 conduct, theintime interval, both the switches and all diodes Mode 2 [ t1 , t2 ]:asDuring are reverse-biased depicted Figure 4b. The magnetizing inductances m1 and Lm2 as well as the are reverse-biased as depicted in Figure 4b. The magnetizing inductances Lm1 and Lm 2 as well as
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the leakage inductances Lk 1 and Lk 2 are linearly charged by the input voltage Vin . This mode ends
t2 , when off. by the input voltage V . This mode ends at the at the instant 2 is turned leakage inductances Lk1the andswitch Lk2 areSlinearly charged in t = tS2 ,2 the S 2 is turned off, which makes the diodes DC 2 and D2 turn t3 ]: At switchoff. Mode 3 [ t2 , the instant t2 , when switch is turned
iLk 2 . off, S1 remains Thewhich switchmakes in the as on due to the of tthe leakage switchcurrent S2 is turned the diodes DC2turn-on and D2state, turn on Mode 3 [tcontinuity 2 , t3 ]: At t = 2 , the due to the continuity of theenergy leakage current i Lk2magnetizing . The switch S remains in the turn-on state, as shown in L is transferred not only to shown in Figure 4c. The kept by the inductance 1 m2 Figure 4c. The energy kept by the magnetizing inductance L is transferred not only to the secondary the secondary side of the coupled inductors but also to m2 the output capacitor C2 and the clamp side of the coupled inductors but also to the output capacitor C2 and the clamp capacitor CC2 . The capacitor CC 2 . The current through Lk 2 decreases and flows through two paths. One path is through current through Lk2 decreases and flows through two paths. One path is through CC1 , D2 , C2 and C , D2 , C2 and S 2 , so that the clamp capacitor CC1 is discharged and the output capacitor C2 is S2C,1 so that the clamp capacitor CC1 is discharged and the output capacitor C2 is charged. The other CC 2 clamp CC 2 ends and Dcapacitor theisclamp capacitor is charged. charged. The other is through C 2 , so that path is through CC2 path and D CC2 charged. This mode when SThis 2 is C2 , so that the mode ends turned on. when S 2 is turned on. Ts
v gs1
t 1 Ts 2
v gs 2
t
vds1
vds 2
t
i Lk1 iLk 2
t
iD1 iD 2
t
vD1
t
vD 2 t
iD 3 iD 4
t
vD 3
t
vD 4 t
iDC1 iDC 2
t
vDC1
t
vDC 2
t
t 0 t1 t 2 t3 t 4
t5
t6
Figure 3. Key waveforms of the proposed converter. Figure 3. Key waveforms of the proposed converter.
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iLk1
iLk 2
D3
iDC1 DC1 − VCC1 +
iin + Vin −
Ns2
+ VC 3 iD 3 − − vD 2 +
iD 2 D2
+ VC 2 −
CC1 + VCC 2 −
S2
S1
C4
N p2
N p1 Lm 2
Lm1
*
+ Lk 2 vD 3 − − vDC1 +
Lk1
+ VC 4 −
CC 2 + vDC 2 −
+ v D1−
DC 2 iDC 2
+ VC1 −
+ Lk 2 vD 3 − − vDC1 +
Lk1
C3 + VO − C2
iLk1
iLk 2
+ Vin −
N p2
iLk1
iLk 2
+ Vin −
+ VC 4 −
CC 2 + vDC 2 −
C1
C4
iD 2 D2
+ VC 2 −
CC 2 + vDC 2 −
+ VC1 −
+ vD1−
DC 2 iDC 2
N p1 Lm 2
Lm1
*
+ VCC 2 −
S2
N p2
Lk1
C3 + VO − C2
iLk1
iLk 2
+ Vin −
Lk1
iLk1
iLk 2
S2
S1
+ Vin − S1
S2
+ VC 4 −
CC 2 + vDC 2 −
DC 2 iDC 2
(e)
iD 2 D2
C3 + VO −
+ VC 2 −
C2
+ VC1 −
C1
+ vD1−
D1 iD1
DC 2 iDC 2
C4
Ns2
iD 2 D2
+ VC 2 −
+ VCC 2 − CC 2 + vDC 2 −
*
(d)
+ + Lk 2 vD 3 D3 VC 3 i D3 − − − vDC1 + − vD 2 +
CC1
C4
Ns2
+ VCC 2 −
D1 iD1
+ i vD 4 D4 D 4 − N s1
iDC1 DC1 − VCC1 +
iin
C1
+ VC 4 −
CC1
C1
+ vD1−
+ VC1 −
D1 iD1
Lk1
C3 + VO − C2
C1
N p2
N p1 Lm 2
Lm1
*
N p2
+ VC1 −
D1 iD1
+ i vD 4 D4 D 4 − N s1
iDC1 DC1 − VCC1 +
iin
*
*
N p1 Lm 2
+ VO − C2
+ + Lk 2 vD 3 D3 V C3 iD 3 − − − vDC1 + − vD 2 +
(c)
Lm1
C3
+ VC 2 −
+ vD1−
DC 2 iDC 2
Ns2
CC1 S1
+ VC 3 − − vD 2 +
iD 3
iD 2 D2
C4
(b)
+ i vD 4 D4 D 4 − N s1
iDC1 DC1 − VCC1 +
iin
Ns2
+ VCC 2 −
S2
S1
D1 iD1
+ + Lk 2 vD 3 D3 V C3 iD 3 − − − vDC1 + − vD 2 +
Lk1
+ VC 4 −
CC1
*
*
N p1 Lm 2
D3
iDC1 DC1 − VCC1 +
iin
(a)
Lm1
+ i vD 4 D4 D 4 − N s1
*
N p2
+ i vD 4 D4 D 4 − N s1
*
*
N p1 Lm 2
Lm1
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iLk1
iLk 2
+ i vD 4 D4 D 4 − N s1
+ Vin −
CC1 S1
S2
*
iD 2 D2
DC 2 iDC 2
C3 + VO −
+ VC 2 −
C2
+ VC1 −
C1
+ VCC 2 − CC 2 + vDC 2 −
C4
Ns2
+ + Lk 2 vD 3 D3 VC 3 i D3 − − − vDC1 + − vD 2 + iDC1 DC1 − VCC1 +
iin
+ VC 4 −
+ vD1−
D1 iD1
(f)
Figure 4. Operating modes of the proposed converter. (a) Mode 1; (b) Mode 2; (c) Mode 3; (d) Mode 4; Figure 4. Operating modes of the proposed converter. (a) Mode 1; (b) Mode 2; (c) Mode 3; (d) Mode 4; (e) Mode 5; (f) Mode 6. (e) Mode 5; (f) Mode 6.
Mode 4 [ t3 , t4 ]: At t = t3 , the power switch S 2 is turned on, and the power switch S1 remains in the turn-on state. The diodes D1 , D2 , D3 , DC1 and DC 2 are reverse-biased, and only the switched diode D4 is conducting as shown in Figure 4d. The current through the leakage inductance
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Mode 4 [t3 , t4 ]: At t = t3 , the power switch S2 is turned on, and the power switch S1 remains in the turn-on state. The diodes D1 , D2 , D3 , DC1 and DC2 are reverse-biased, and only the switched diode D4 is conducting as shown in Figure 4d. The current through the leakage inductance Lk2 rises quickly, and the current through the leakage inductance Lk1 falls quickly. The stored energy in the magnetizing inductance Lm2 still transfers to the secondary side of the coupled inductors charging the switched capacitor C4 . As the current through the leakage inductance Lk2 increases, the secondary side current of the coupled inductors decreases. The of the current through the switched diode D4 decreases and its falling rate controlled by the leakage inductances Lk1 and Lk2 , which alleviates the diode reverse recovery problem. This mode ends when the diode current i D4 decreases to zero at t = t4 , and D4 is turned off automatically. At the same time, the current through Lk2 becomes equal to that of the magnetizing inductance Lm2 . Mode 5 [t4 , t5 ]: The operating state of modes 5 and 2 are similar. During this interval, all diodes are turned off, as shown in Figure 4e. The magnetizing inductances Lm1 and Lm2 as well as the leakage inductances Lk1 and Lk2 are charged linearly by the input voltage Vin . This mode is terminated as the switch S1 is turned off. Mode 6 [t5 , t6 ]: The switch S1 is turned off at t = t5 , which turns on the diodes DC1 and D1 . The switch S2 remains in turn-on state. The current-flow path of this mode is shown in Figure 4f. The energy stored in the magnetizing inductance Lm2 begins to transfer to the secondary side of the coupled inductors charging the switched capacitor C3 via the switched diode D3 . The current through the diode D3 is controlled by the leakage inductances Lk1 and Lk2 . The leakage current i Lk1 decreases and flows to the clamp capacitor CC1 via DC1 and S2 , meanwhile it flows to the output capacitor C1 and the clamp capacitor CC2 via D1 and S2 . The time t6 is the ending of a switching period Ts when the power switch S1 is turned on again. 3. Steady-State Analysis and Design Guidelines In order to simplify the performance analysis of the proposed converter, the following assumptions are made. (1) (2) (3) (4)
Voltages on the capacitors are regarded as constant over one switching period due to their sufficiently large capacitances. All of the power devices are ideal. The on-resistance Rds(ON) and parasitic capacitances of the power switches are ignored, and the forward voltage drops of the diodes are neglected. The leakage inductances of the couple inductors are much smaller than the magnetizing inductances, and, therefore, they are neglected. ◦ The switching period is Ts . The power switches operate with the same duty ratio D and 180 out of phase.
3.1. Voltage Gain Since the time intervals of modes 1 and 4 are very short, only modes 2, 3, 5 and 6 were considered for the steady-state analysis. Based on the operating principle discussed in the aforementioned section, the charging voltage of the magnetizing inductance Lm is the input voltage Vin during the switch is in the turn-on state for time DTs , and the discharging voltage is the clamp voltage VCC1 or VCC2 minus the input voltage Vin during the switch is in the turn-off state for time (1 − D ) Ts . By applying the voltage-second balance to the magnetizing inductance, the voltages on the clamp capacitors CC1 and CC2 can be calculated analogously to the output voltage of the conventional boost converter, which can be derived from 1 VCC1 = VCC2 = V . (1) 1 − D in
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At modes 3 and 6, the voltages on the output capacitors C2 and C1 can be derived from Figure 4c,f, respectively. They can be expressed as 2 VC 2 =VCC1 + VCC 2 = Vin , (2) 1 −2D Vin , (2) VC2 = VCC1 + VCC2 = 1−D 2 VC1 =VCC1 + VCC 2 = 2 Vin . (3) D Vin . 1 − VC1 = VCC1 + VCC2 = (3) 1−D Moreover, the voltage on the switched capacitors C4 and C3 can also be derived from Figure Moreover, the voltage on the switched capacitors C4 and C3 can also be derived from Figure 4c,f, 4c,f, respectively. The results are given respectively. The results are given by by
n − n(Vin −VVCC 2))== nVin V , , C 4 =nV VC4 = VnV CC2 in −inn (Vin − 1 −1 D − D in
(4) (4)
n VC3 = VnVin − n(Vin − VCC1 ) = n Vin . (5) (5) C 3 =nVin − n(Vin − VCC1 )= 1 −V in . 1− D D From Figure 4b,e, it can be found that the output voltage is the sum of VC1 , VC2 , VC3 and VC4 . From Figure 4b,e, it can be found that the output voltage is the sum of V , VC 2 , VC 3 and VC 4 . With the results of Equations (2)–(5), the output voltage can be derived from C1 With the results of Equations (2)–(5), the output voltage can be derived from 2n + 4 Vo = VC1 + VC2 + VC3 + VC4 =2n + 4 Vin . (6) Vo = VC1 + VC 2 + VC 3 + VC 4 = 1 − D Vin . (6) 1− D Therefore, Therefore, the the voltage voltage gain gain of of the the proposed proposed converter converter is is given given by by Vo Vo 2n 2n++44 == .. VinVin 11−− D D
(7) (7)
Equation Equation (7) (7) confirms confirms that that the the proposed proposed converter converter has has aa high high step-up step-up voltage voltage gain gain without without adopting an extremely large duty ratio. The curve of the voltage gain related to the turns ratio adopting an extremely large duty ratio. The curve of the voltage gain related to the turns ratio of of the the coupled inductor n and duty ratio D is shown in Figure 5. As the turns ratio of the coupled inductors coupled inductor n and duty ratio D is shown in Figure 5. As the turns ratio of the coupled increases, voltagethe gain is extended When the duty ratio only ratio 0.6, the voltage inductors the increases, voltage gain issignificantly. extended significantly. When theisduty is only 0.6,gain the reaches 15 with the turns ratio n = 1. voltage gain reaches 15 with the turns ratio n = 1 . 80
Voltage Gain (Vo/Vin)
70 60
n=1 n=3 n=5
50 40 30 20 10 0 0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
0.95
Duty Ratio (D) Figure 5. Voltage gain of the proposed converter verse duty ratio for several turns ratio n. Figure 5. Voltage gain of the proposed converter verse duty ratio for several turns ratio n.
3.2. Voltage Stresses on Semiconductor Devices The voltage ripples on the capacitors are neglected to simplify the voltage stress analysis of the power switches and diodes. From Figure 4c,f, the power switch S1 or S2 is turned off and the drain-source voltages of S1 and S2 is equal to the voltages on the clamp capacitors CC1 and CC 2 , respectively. Thus, the voltage stresses on the power switches S1 and S2 can be derived from
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3.2. Voltage Stresses on Semiconductor Devices The voltage ripples on the capacitors are neglected to simplify the voltage stress analysis of the power switches and diodes. From Figure 4c,f, the power switch S1 or S2 is turned off and the drain-source voltages of S1 and S2 is equal to the voltages on the clamp capacitors CC1 and CC2 , respectively. Thus, the voltage stresses on the power switches S1 and S2 can be derived from VS1−stress = VS2−stress =
1 1 Vin = Vo . 1−D 2n + 4
(8)
It can be seen that the switch voltage stress is greatly lower than the output voltage and it decreases greatly as the turns ratio of the coupled inductor increases. As a result, the low-voltage-rated MOSFETs with low on-resistance can be employed and the conversion efficiency can be improved. From the operating modes of the proposed converter, the voltage stresses of the output diodes D1 and D2 are equal to the voltages VC1 and VC2 , respectively. The voltage stresses of the switched diodes D3 and D4 are the voltage VC3 plus the voltage VC4 . The voltage stresses of the output and switched diodes can be expressed as VD1 −stress = VD2−stress =
2 1 V = Vo , 1 − D in n+2
(9)
VD3 −stress = VD4−stress =
2n n V = Vo . 1 − D in n+2
(10)
At mode 3, the voltage stress of the clamp diode DC1 can be obtained as the sum of the voltages VCC1 and VCC2 . On the other hand, the voltage stress of the clamp diode DC2 is equal to the voltage VCC2 from Figure 4f. Therefore, the voltage stresses of the clamp diodes can be given by VDC1−stress =
2 1 V = Vo , 1 − D in n+2
(11)
VDC2−stress =
1 1 Vin = Vo . 1−D 2n + 4
(12)
Equations (8)–(12) show that the proposed converter has the property of low voltage stresses on the semiconductor devices. The relationship between the normalized semiconductor-device voltage stresses and the turns ratio is depicted in Figure 6. It can be seen that the voltage stresses on S1 , S2 , D1 , D2 , DC1 and DC2 decreases as the turns ratio n increases. The voltage stress on D3 and D4 increases as the turns ratio n increases, but it is always lower than the output voltage. Therefore, the low-voltage-rated MOSFETs with low on-resistance Rds(ON) and Schottky diode without reverse-recovery time can be used to improve the efficiency.
stresses and the turns ratio is depicted in Figure 6. It can be seen that the voltage stresses on S1 , S2 ,
D1 , D2 , DC1 and DC 2 decreases as the turns ratio n increases. The voltage stress on D3 and D4 increases as the turns ratio n increases, but it is always lower than the output voltage. Therefore, the low-voltage-rated MOSFETs with low on-resistance Rds (ON ) and Schottky diode without reverserecovery can Energies 2018,time 11, 1632
be used to improve the efficiency.
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1
VS1,VS2,VDC2 VDC1,VD1,VD2 VD3,VD4
0.9 0.8
Vstress/Vo
0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
0
1
2
3
4
5
6
7
8
9
10
n Figure6.6.Normalized Normalizedsemiconductor-device semiconductor-devicevoltage voltagestresses stressesversus versusturns turnsratio ration.n. Figure
3.3. Design Guidelines 3.3.1. Turns Ratio Design The voltage gain expression is given in Equations (7). A proper turns ratio n can be obtained once the voltage gain is assigned and the duty ratio D is designed, which is given by n=
(1 − D )Vo − 2. 2Vin
(13)
3.3.2. Power Switches and Diodes Selection According to Equations (8)–(12), the voltage stresses of the semiconductor devices are obtained, which can be employed to select the power devices. In practice, voltage spikes may occur during the switching transition process due to the effect of the leakage inductance and parasitic capacitor. Therefore, a reasonable margin of safety is necessary for the voltage rating of the selected power devices. 3.3.3. Coupled Inductor Design A good criterion for designing the magnetizing inductance is to maintain the continuousconduction mode (CCM) and set an acceptable current ripple in the magnetizing inductance of the coupled inductor. Assume that the coupled inductors have the same magnetizing inductance, that is Lm1 = Lm2 = Lm . The magnetizing inductance current ripple can be expressed as ∆i Lm =
Vin DTs . Lm
(14)
Vo2 . 2Vin Ro
(15)
The average magnetizing current is given by ILm =
For the CCM operation of the proposed converter, the following condition holds 1 ILm − ∆i Lm > 0. 2
(16)
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Substituting Equations (14) and (15) into Equation (16), the magnetizing inductance can be determined for the CCM operation, which is given by Lm >
D (1 − D )2 R o 4( n + 2)2 f s
,
(17)
where f s is the switching frequency and Ro is the load. 3.3.4. Capacitor Design In the preceding analysis, the capacitors are assumed to be very large to keep their voltages constant. In practice, the voltages cannot be kept constant with a finite capacitance. An acceptable voltage ripple is the main consideration in designing the capacitors. The relationship of the voltage ripple and the capacitance is given by ∆VC = ∆Q/C, (18) where ∆Q is the change in charge or discharge, and ∆VC is the voltage ripple on the capacitor C. The output capacitor C1 is discharged by the load current Io during modes 2, 3 and 5. The total time is equal to DTs . Therefore, the voltage ripple can be obtained as ∆VC1 =
Io DTs DVo = . C1 C1 Ro f s
(19)
Substituting Equation (3) into Equation (19), it can be expressed by the following equation. ∆VC1 =
(n + 2) DVC1 . C1 Ro f s
(20)
It is useful to rearrange the equation to express required capacitance in terms of specified voltage ripple for the output capacitor C1 , which is given by C1 =
( n + 2) D . (∆VC1 /VC1 ) Ro f s
(21)
Similarly, the output capacitor C2 , switched capacitors C3 and C4 , and clamp capacitors can be derived to express required capacitance in terms of specified voltage ripple, which are given by C2 =
( n + 2) D , (∆VC2 /VC2 ) Ro f s
(22)
C3 =
(2n + 4) D , (∆VC3 /VC3 )nRo f s
(23)
C4 =
(2n + 4) D , (∆VC4 /VC4 )nRo f s
(24)
CC1 =
2n + 4 , (∆VCC1 /VCC1 ) Ro f s
(25)
CC2 =
2n + 4 , (∆VCC2 /VCC2 ) Ro f s
(26)
where ∆VC2 , ∆VC3 , ∆VC4 , ∆VCC1 and ∆VCC2 are the tolerant voltage ripples on the capacitors C2 , C3 , C4 , CC1 and CC2 , respectively.
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3.4. Performance Comparison The performance comparison between the converters published in [20–22] and the proposed converter is shown in Table 1. The relationship between the voltage gain and the duty ratio in these converters with the turns ratio n = 1.5 is shown in Figure 7. It can be seen that the voltage gain of the proposed converter is higher than the other converters. In fact, if the turns ratio n of the coupled inductor is designed by less than 3, then the voltage gain of the proposed converter is the highest. Moreover, the voltage stress on the switches and the highest voltage stress on diodes of the proposed converter are the lowest among the compared converters. The component number of the proposed Energies 2018, 11 of 16 converter is 11, lessx FOR thanPEER thatREVIEW of the converter published in [21]. Clearly, the proposed converter is suitable for the high step-up and high voltage applications. Table 1. Converter performance comparison. TableConverter 1. Converter performance comparison. Converter Converter Proposed Published in [20] Published in [21] Published in [22] Converter Converter Converter Converter Proposed 2n+2 3n+1 2n+2 2n+4 Topology Voltage gainPublished in [20] Published in [21] Published in [22] Converter
Topology
1− D
2n+2 Voltage gain 1− D Vo Voltage stress Voltage stress on on switches Vo 2n+2 2n+2 switches n (2 +1)Vo The highest voltage The highest voltage (2n+1)Vo 2n+2 stress onstress diodes on diodes 2n+2 SwitchesSwitches 2 2 Diodes Diodes 6 6 Capacitors 5 Capacitors 5 Coupled inductors 2 Coupled inductors 2
80
2nVo 3n+1
2 8 7 2
1− D Vo 3n+1 2nVo 3n+1
1− D Vo 2n+2 (2 n (2n+1)Vo +1)Vo 2n+2 2n+2 2n+2 1− D Vo 2n+2
2 6 5 2
2 8 7 2
2 6 5 2
1− D
2n+4 1− VDo Vo 2n++4 2n 4
2 nV 2nV o o 2n+4
2n+4 22 66 6 6 2 2
Converters in [20] and [22] Converter in [21] Proposed converter
70
Voltage Gain (Vo/Vin)
3n+1 1− D Vo 3n+1
60 50 40 30 20 10 0 0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
0.95
Duty Ratio (D) Figure 7. Voltage gains versus duty ratio with turns ratio n = 1.5. Figure 7. Voltage gains versus duty ratio with turns ratio n = 1.5.
4. Experimental Verifications 4. Experimental Verifications To validate the performance and effectiveness of the proposed converter, a 1000 W laboratory To validate the performance and effectiveness of the proposed converter, a 1000 W laboratory prototype with 28-V input and 380-V output voltages was built and tested with the specifications and prototype with 28-V input and 380-V output voltages was built and tested with the specifications and parameters shown in Table 2. The experimental results shown in the Figures 8–15 are measured under parameters shown in Table 2. The experimental results shown in the Figures 8–15 are measured under full-load conditions 1000 W. full-load conditions 1000 W. Table 2. Components and parameters of the prototype.
Components Input voltage Vin Output voltage Vo Maximum output power Po
Parameters 28 V 380 V 1000 W
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Table 2. Components and parameters of the prototype. Components
Parameters
Input voltage Vin 28 V Output voltage Vo 380 V Maximum output power Po 1000 W Switching frequency fs 50 kHz Magnetizing inductances Lm1 and Lm2 245 µH 0.9 µH Leakage inductances Lk1 and Lk2 Turns ratio n 1 Switches S and S IRFP4321 1 2 Energies 2018, 11, x FOR PEER REVIEW 12 of 16 30CPQ200 Diodes DC1 , DC2 , D1 , D2 , D3 , D4 Energies 2018, 11, x FOR PEER REVIEW 12 of 16 10 µF Clamp capacitors CC1 and CC2 Clamp capacitors CC1 and CC2 10 µF Output capacitors C1 and C2 100 µF Outputcapacitors capacitorsCC and C CC2 2 100 µF Clamp C11 and 10 µF Switched capacitors C3 and C4 100 µF Switched capacitors C 3 and C 4 100 µF Output capacitors C1 and C2 Switched capacitors C3 and C4 signals 100 vµF and v , the input voltage Figure 8 shows t waveforms of the interleaved PWM Figure 8 shows t waveforms of the interleaved PWM signals v gs1 gs1 the input voltage and v gs 2 ,gs2
Vin = 28 V and the output voltage Vo = 380 V. The duty ratio is about 0.58. Thus, the high step-up v 2 , the 8 shows t waveforms interleaved PWM signals v gs1 0.58. voltage and Thus, V =Figure 28 V and the output voltageofVthe theinput high step-up o = 380 V. The duty ratio is about voltagein gain is realized without operating at an extremely large duty ratio. gsThe waveforms of gate Vin = 28gain Vo = 380 V and the output voltage duty ratio is duty aboutratio. 0.58. The Thus, the high step-up voltage is realized without operating at V. an The extremely large waveforms of gate signals and the drain-source voltages vds1 and vds2 are shown in Figure 9. It can be seen that the voltage v v signals and the drain-source voltages are shown in Figure 9. It can be seen that the and voltage gain is realized without operating at an extremely large duty ratio. The waveforms of gate stresses on the power switches are about 63ds1V, whichds 2is only one-sixth of the output voltage. Thus, one vds1 about vds 2V,are signals and the on drain-source shown in Figure 9. Itofcan seen voltage. that the and 63 voltage stresses the power voltages switches are which is only one-sixth thebe output can adopt low-voltage-rated devices to reduce the conduction and switching losses. Thus, one can adopt low-voltage-rated devices to63 reduce the conduction and switching losses. voltage stresses on the power switches are about V, which is only one-sixth of the output voltage. Thus, one can adopt low-voltage-rated devices to reduce the conduction and switching losses.
v gs1: 20V/div v gs1: 20V/div v gs 2 : 20V/div v gs 2 : 20V/div Vin : 20V/div Vin : 20V/div Vo : 400V/div Vo : 400V/div
Time : 10us/div Time : 10us/div
Figure 8. Measured waveforms of the gating signals and the input and output voltages.
Figure 8. Measured waveforms of the gating signals and the input and output voltages. Figure 8. Measured waveforms of the gating signals and the input and output voltages.
Figure 9. Measured waveforms of the gating signals and the drain-source voltages of power switches. Figure 9. Measured waveforms of the gating signals and the drain-source voltages of power switches.
Figure 9. Measured waveforms of the gating andon thethe drain-source voltages of power switches. Figure 10 depicts the waveform of thesignals voltages output capacitors and the switched VC1 switched VC 3 and VC 4 are capacitors. the ratio n is of equal one, the voltages half of the and Figure 10 depicts the waveform ofthe thetovoltages voltages on capacitors and the switched Figure 10 Because depicts theturns waveform on the theoutput output capacitors and
V capacitors. Because turns rationare nisisequal equal to one, the areanalysis half VC 2 . The experimental results in a good agreement withVV the theoretical in V . C 3C3and 4 are 1 and capacitors. Because thethe turns ratio to one, thevoltages voltages and VVCC4 halfofof given VCC1 and C2 VC 2 . The (2)–(5). experimental results a goodonagreement with the theoretical analysis in Equations Figure 11 showsare thein voltages the clamp capacitors. It can be seen that thegiven voltage ripple is small, clamp the thevoltages voltage on stress of thecapacitors. power switches. 12 the shows the Equations (2)–(5).which Figurecan 11 shows the clamp It can beFigure seen that voltage waveforms of thewhich input can current andthe the voltage currentsstress through As can seen, the ripple is small, clamp of the the leakage power inductances. switches. Figure 12be shows currents through the leakage are interleaved such that the input current ripple is very waveforms of the input currentinductances and the currents through the leakage inductances. As can be seen, the small. The averagethe current of inductances similar to iLk 2 , which is athe halfinput of thecurrent input current. iLk1 is quite are currents through leakage interleaved such that ripple isThus, very small. The average of iLk1is is quite similar is a half of the input current. Thus, iLk 2 , whichinterleaved the current sharing current performance good due to thetosymmetrical structure.
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The experimental results are in a good agreement with the theoretical analysis given in Equations (2)–(5). Figure 11 shows the voltages on the clamp capacitors. It can be seen that the voltage ripple is small, which can clamp the voltage stress of the power switches. Figure 12 shows the waveforms of the input current and the currents through the leakage inductances. As can be seen, the currents through the leakage inductances are interleaved such that the input current ripple is very small. The average current of i Lk1 is quite similar to i Lk2 , which is a half of the input current. Thus, the current sharing performance is good due to the symmetrical interleaved structure. Energies 2018, 11, x FOR PEER REVIEW 13 of 16 Energies 2018, 11, x FOR PEER REVIEW Energies 2018, 11, x FOR PEER REVIEW VC1: 100V/div
13 of 16 13 of 16
VC1: 100V/div VC1: 100V/div VC 2 : 100V/div VC 2 : 100V/div VC 2 : 100V/div
VC 3: 40V/div VC 3: 40V/div 40V/div VVCC34:: 40V/div VC 4 : 40V/div VC 4 : 40V/div
Time : 10us/div Time : 10us/div Figure 10. Measured waveforms of the voltages on the switched capacitors and the output capacitors. Time : 10us/div Figure 10. Measured waveforms of the voltages on the switched capacitors and the output capacitors. Figure 10. Measured waveforms of the voltages on the switched capacitors and the output capacitors. Figure 10. Measured waveforms of the voltages on the switched capacitors and the output capacitors.
VCC1: 100V/div VCC1: 100V/div VCC1: 100V/div VCC 2 : 100V/div VCC 2 : 100V/div VCC 2 : 100V/div
Time : 10us/div Time : 10us/div Figure 11. Measured waveforms of the voltages on theTime clamp capacitors. : 10us/div
Figure 11. Measured waveforms of the voltages on the clamp capacitors.
Figure 11. Measured waveforms of the voltages on the clamp capacitors. Figure 11. Measured waveforms of the voltages on the clamp capacitors.
iin : 50A/div iin : 50A/div iin : 50A/div
iLk 1: 20A/div iLk 1: 20A/div iLk 1: 20A/div
iLk 2 : 20A/div iLk 2 : 20A/div iLk 2 : 20A/div
Time : 10us/div Time : 10us/div Figure 12. Measured waveforms of the input current and the currentsTime through the leakage inductances. : 10us/div
Figure 12. Measured waveforms of the input current and the currents through the leakage inductances. Figures depict the voltage and current waveforms on the clampthe diodes, output diodes and Figure 12.13–15 Measured waveforms of the input current and the currents through leakage inductances.
Figure 12. Measured waveforms of the input current and the currents through the leakage inductances. switched diodes, One can see that the reverse recovery currents are very small because Figures 13–15respectively. depict the voltage and current waveforms on the clamp diodes, output diodes and Figures 13–15 depict the voltage and current waveforms on the clamp diodes, output diodes and and Figures 13–15 depict the voltage and current waveforms on the clamp diodes, output diodes the current falling rates are controlled by the leakage inductances. As a result, the reverse recovery switched diodes, respectively. One can see that the reverse recovery currents are very small because switched respectively. One cansee see thatleakage the reverse recovery currents are very small because DC 2 is As D losses arediodes, alleviated. Theare voltage stress onthe the clamp diode half that on clamp diode the current falling rates controlled by inductances. a of result, the reverse recovery switched diodes, respectively. One can that the reverse recovery currents are very small because C1 the current falling rates are controlled by the leakage inductances. As a result, the reverse recovery DC 2 (11) losses are stress onanalysis the clamp is half that The on clamp diode , which is alleviated. consistent The withvoltage the theoretical in diode Equations andof(12). voltage stressDon C1 DC 2 (11) Don losses are The stress theare clamp is of(12). thatratio on clamp diode Cis 1 D on diodes and switched diodes – Danalysis almost identical tohalf the nvoltage of one, which ,output which is alleviated. consistent withvoltage the theoretical in diode Equations andturns The stress 1
4
,output is consistent with theoretical analysis in Equations (11) andturns (12). The nvoltage stress on Danalysis diodes andwith switched diodes identical to(10). the ratio of one, which is inwhich agreement well thethe theoretical in almost Equations (9) and The overvoltage and ringing 1 – D4 are D D output diodes and switched diodes – are almost identical to the turns ratio n of one, which is 4 1 D theoretical D with onagreement the diodeswell and the are largeranalysis than to the other diodes, as shown in Figure 15. This is ringing a result in in Equations (9) and (10). The overvoltage and 3
4
in with analysis in Equations (9) and (10). The overvoltage and D4theoretical D3equivalent on the simplified diodeswell and the are larger than the other diodes, as shown in Figure is ringing a result of agreement the circuit with theto leakage inductance introduced only on15. theThis primary side
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the current falling rates are controlled by the leakage inductances. As a result, the reverse recovery losses are alleviated. The voltage stress on the clamp diode DC2 is half of that on clamp diode DC1 , which is consistent with the theoretical analysis in Equations (11) and (12). The voltage stress on output diodes and switched diodes D1 –D4 are almost identical to the turns ratio n of one, which is in agreement well with the theoretical analysis in Equations (9) and (10). The overvoltage and ringing on the diodes D3 and D4 are larger than to the other diodes, as shown in Figure 15. This is a result of the simplified equivalent circuit with the leakage inductance introduced only on the primary side such that the clamp circuits are ineffective, to limit the overvoltage on D3 and D4 . Furthermore, the voltage stresses of all the diodes are much lower than the output voltage. In order to obtain a regulated and constant output voltage in spite of input voltage variation and output load disturbance, the closed-loop control with type III compensator is implemented [23]. There are three poles (one at the origin) and two zeros provided by this compensation. The experimental result under the step load change from half load 500 W to full load 1000 W and vice versa is illustrated in Figure 16. It can be seen that the transient voltage ripple of the output voltage is small and insensitive to the load change. This means that the compensator design can deliver a dynamic performance. The Energies 2018, 11, x FOR PEER REVIEW 14 of 16 experimental efficiency of the presented converter is given in Figure 17, which is measured Energies 2018, 11,conversion x FOR PEER REVIEW 14 of 16 by the power analyzer (HIOKI 3390). The full-load efficiency is about 86% and the peak value of such that the clamp circuits are ineffective, to limit the overvoltage on D3 and D4 . Furthermore, efficiency is 94.5% obtained at the output power of 200 W. D D such that the clamp circuits are ineffective, to limit the overvoltage on and . Furthermore, 3 4 the voltage stresses of all the diodes are much lower than the output voltage.
the voltage stresses of all the diodes are much lower than the output voltage.
iDC1: 20A/div iDC1: 20A/div
iDC 2 : 20A/div iDC 2 : 20A/div vDC1: 100V/div vDC1: 100V/div
vDC 2 : 100V/div vDC 2 : 100V/div
Time : 10us/div Time : 10us/div
Figure 13. Measured waveforms of the voltages and currents on the clamp diodes. Figure 13. Measured waveforms of the voltages and currents on the clamp diodes. Figure 13. Measured waveforms of the voltages and currents on the clamp diodes.
iD1: 10A/div iD1: 10A/div iD 2 : 10A/div iD 2 : 10A/div
vD1: 100V/div vD1: 100V/div
vD 2 : 100V/div vD 2 : 100V/div
Time : 10us/div Time : 10us/div
Figure 14. Measured waveforms of the voltages and currents on the output diodes. Figure 14. Measured waveforms of the voltages and currents on the output diodes. Figure 14. Measured waveforms of the voltages and currents on the output diodes.
iD 3: 20A/div iD 3: 20A/div iD 4 : 20A/div iD 4 : 20A/div
vD1: 100V/div
vD 2 : 100V/div
Time : 10us/div
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Figure 14. Measured waveforms of the voltages and currents on the output diodes.
iD 3: 20A/div
iD 4 : 20A/div
vD 3: 100V/div Energies 2018, 11, x FOR PEER REVIEW Energies 2018, 11, x FOR PEER vD 4 : REVIEW 100V/div
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Time : 10us/div
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is small and insensitive to the load change. This means that the compensator design can deliver a is small and insensitive to the load change. This means that the compensator design canisdeliver a dynamic performance. The experimental conversion efficiency of the converter given in Figure 15. Measured waveforms of the voltages and currents onpresented the switched diodes. Figureis15. Measured waveforms of the voltages and currents on thefull-load switched diodes. dynamic The experimental conversion efficiency of the presented converter is given in Figure 17,performance. which measured by the power analyzer (HIOKI 3390). The efficiency is about Figure which isvalue measured by the power (HIOKI 3390). The efficiency is about 86% and the peak efficiency is constant 94.5%analyzer obtained at the output power of 200 W. variation In17, order to obtain a of regulated and output voltage in spite offull-load input voltage and 86% andload the peak value of the efficiency is 94.5% obtained the output power of 200 W. output disturbance, closed-loop control withattype III compensator is implemented [23]. There are three vpoles (one at the origin) and two zeros provided by this compensation. The o : 200V/div experimental result under the step load change from half load 500 W to full load 1000 W and vice vo : 200V/div versa is illustrated in Figure 16. It can be seen that the transient voltage ripple of the output voltage
io : 1A/div io : 1A/div Time: 10ms/div Time: 10ms/div
Figure 16. Output voltage response with step load change. Figure 16. Output voltage response with step load change. Figure 16. Output voltage response with step load change.
Figure 17. Experimental conversion efficiency of the implemented converter. Figure 17. Experimental conversion efficiency of the implemented converter. Figure 17. Experimental conversion efficiency of the implemented converter.
5. Conclusions 5. Conclusions A new interleaved high step-up DC-DC converter based on voltage multiplier cell and voltage5. Conclusions A new interleaved high step-up convertervoltage based on voltage multiplier cell and voltagestacking technique is proposed. TheDC-DC high step-up conversion can be achieved without A new interleaved high step-up DC-DC converter based on voltage multiplier cell and stacking is proposed. conversion canlower be achieved working technique at extremely large duty The ratio.high Thestep-up switch voltage stress is much than thewithout output voltage-stacking technique is proposed. The high step-up voltage conversion can be achieved without working at extremely large duty ratio. The switch voltage is much lower than the output voltage such that the low-voltage-rated power devices withstress low on-resistance can be adopted to voltage such that the low-voltage-rated power devices with on-resistance can be adopted to reduce the conduction losses. Dual passive clamp circuits helplow to recycle the leakage energy of the reduce conduction passive stress clampofcircuits help to to recycle the level. leakage energy of the coupledthe inductors andlosses. clampDual the voltage the switches a lower The interleaved coupled andinput clamp the voltage of the switches to a lower level. The interleaved operationinductors reduces the current ripple. stress The diode reverse-recovery problem is alleviated by the operation reduces theofinput current ripple. Thefor diode reverse-recovery problem is alleviated by the leakage inductances the coupled inductors most of the diodes. The operating principle,
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working at extremely large duty ratio. The switch voltage stress is much lower than the output voltage such that the low-voltage-rated power devices with low on-resistance can be adopted to reduce the conduction losses. Dual passive clamp circuits help to recycle the leakage energy of the coupled inductors and clamp the voltage stress of the switches to a lower level. The interleaved operation reduces the input current ripple. The diode reverse-recovery problem is alleviated by the leakage inductances of the coupled inductors for most of the diodes. The operating principle, the steady-state analysis and design guidelines of the proposed converter are presented. Finally, a 1000 W prototype converter was built and tested to validate the converter’s performance. Author Contributions: S.-J.C. and S.-P.Y. conceived and designed the converter circuit. M.-J.S. performed the experiments. C.-M.H. and H.-M.C. analyzed the performance. S.-J.C. wrote the manuscript. Funding: The authors gratefully acknowledge financial support from the Ministry of Science and Technology, Taiwan, under the grant number MOST 106-2632-E-168-001. Conflicts of Interest: The authors declare that there is no conflict of interest.
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