Introducing Hardware Emulation in the ECE Curriculum Mark G. Faust, Haera Chung, Hoon Park
Joe Rodriguez
ECE Department Portland State University Portland, OR USA
[email protected]
Mentor Graphics Corporation Wilsonville, OR USA
[email protected] to introduce the techniques incrementally into an existing course instead of creating and getting approval for a new course. We then introduced a project-oriented course focusing on transaction-based simulation and hardware emulation that could draw on those students who had recently completed the two augmented courses and who now had a better appreciation for the subject.
Abstract—This paper describes a collaborative effort between Mentor Graphics and Portland State University to introduce hardware emulation into the undergraduate and graduate electrical and computer engineering curriculum. We detail several parallel approaches that address a need for both broad exposure to the concepts of hardware emulation and more indepth experience with transaction-based verification. Keywords-hardware verification, emulation, acceleration, simulation, education, curriculum, transaction-based verification
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III.
INTRODUCTION
Undergraduate and graduate programs in electrical and computer engineering (ECE) have responded to the need for engineers trained in verification techniques with verification courses covering topics such as functional simulation, static timing verification, and formal techniques likes assertion checking. Techniques such as simulation acceleration (particularly hardware emulation) and transaction-based verification are becoming increasingly important as the rising complexity of SOC designs has resulted in prohibitively long simulation runtimes [1]. With functional verification responsible for 40% to 70% of the effort of the verification team on large chip designs [2] functional simulation has become a bottleneck, affecting cost, time-to-market, and quality. Yet design verification courses in the ECE curricula have not usually included these topics and few ECE students graduate with experience in these techniques. This paper describes efforts to introduce these topics into design and verification courses in the ECE curriculum to better prepare graduates for design verification in an environment where large SOC designs are increasingly common and traditional software-based simulation can take weeks or longer. II.
IV.
PROJECT COURSE
We restricted enrollment in the project-oriented course to graduate students who had completed at least one of the two courses into which we’d introduced hardware emulation labs. This was done for several reasons. First, our undergraduate curriculum has few electives beyond those that are chosen to fulfill a particular track’s requirements. Secondly, because of the learning curve we wanted to include only students already familiar with the basics of the hardware emulator environment and tool flow so that the quarter could be devoted to building simulation models and the transaction-based testbenches to test them. Students were encouraged to focus on the verification part of the project, leveraging existing designs (e.g. open
HYBRID APPROACH
Our objective was to expose as many students as possible to the technology of hardware emulation while affording students the opportunity to do more in-depth projects employing transaction-based verification. This desire for a combination of breadth and depth guided our initial efforts. Rather than offer a single specialized elective course in hardware emulation that might appeal to few students we first introduced hardware emulation into two existing courses in the ASIC design and verification curriculum. This ensured that the broadest number of students have at least some familiarity with hardware emulation. It also allowed us
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COURSE CHANGES
Some of our undergraduates and many of our graduate students take an ASIC design (modeling and synthesis) course (ECE 481/581) and many of the graduate students follow that with an ASIC verification course (ECE 582/682). We chose these two courses to introduce hardware emulation into the curriculum because hardware emulation is a natural fit with their current content and because of the relatively large enrollments. We introduced additional labs into the Fall 2009 and Winter 2010 quarters for these courses, respectively. In Fall 2010 we also added coverage of hardware emulation in a graduate course in high-level synthesis and design automation (ECE 590/690). In the ASIC design course students were given a tutorial and assigned a lab in which they created an RTL-level HDL model for an adder and a synthesizable testbench for verification. In the ASIC verification course students completed a lab in which they verified a design for a digital combination lock using a non-synthesized testbench, exploiting the emulator’s HDL-Link mode (see below). The labs were intended to introduce the concept of hardware emulation, the attendant constraints, and the tool flow. They were not intended to demonstrate the potential for speedup achievable by hardware emulator over software simulation.
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source, examples from textbooks) where possible and concentrating on transaction-based testbench creation and verification using the hardware emulator. Typical projects included pipelined and non-pipelined MIPS data paths, and cache controllers. V.
VII. RESULTS AND FUTURE WORK Approximately 45 (graduate and undergraduate) students enrolled in the ASIC design course and completed the newly introduced labs. About 20 graduate students (who had previously taken the ASIC design course) then took the verification course. Integrating complex design and verification tools and methodology was challenging. In addition to the course changes and creating labs, we spent considerable effort on infrastructure, involving our IT department for integration of host servers and networks, account administration and privileges, remote access tools, and site-specific tutorials. We were fortunate to have both a dedicated college IT team and the assistance of Mentor Graphics. However, we easily expended more time in creating and documenting the environment than in creating the new lab assignments. Students have been enthusiastic about the addition of the hands-on hardware emulation labs to the curriculum and feedback from industry partners has validated the interest among employers for students with a broad range of verification methodology experience, including hardware emulation. We intend to continue to broadly introduce students to hardware emulation but our experience has shown a need for greater depth as well. Consequently, we’re developing two new elective courses that we expect to offer for the first time in summer 2011: one introducing SystemVerilog, and the other a course on design verification focusing on advanced verification methodologies, using object-oriented approaches to create reusable testbenches, and providing more experience with transaction-based verification.
THE TOOLS
The Mentor Veloce hardware emulation environment [4] that we used supports three styles, each with their advantages and disadvantages: standalone, HDL-Link, and TBX. In standalone mode, the testbench is synthesized along with the device model and executes with the device model on the emulation hardware. This eliminates the need for communication between the host and the emulator during emulation and permits significant speedup over softwarebased simulation. However, the testbench must be synthesizable, complicating testbench creation. HDL-Link allows the use of existing testbenches without modification, and reduces the time to bring up models and testbenches on the emulator but at a trade-off in emulation speed because the testbench executes on a workstation that must communicate with the emulator. TBX mode requires more attention to the testbench/device model interface but facilitates transaction-based verification and affords the largest potential speedups. Mentor’s Questa simulator supports all three modes, so students can debug the interface between their testbench and models as well as the testbench before migrating their designs to the hardware emulator. The simulator supports VHDL, Verilog, and SystemVerilog. Because they require no further knowledge than existing HDL constructs and some simple guidelines on synthesizability, we chose to use standalone and HDL-Link for the first two labs. This allowed students to focus on new aspects of hardware emulation and the tool flow rather than learning new procedures or methodology. Once students had taken the courses that included these labs we introduced selected students to transaction-based verification using TBX in the project course. VI.
ACKNOWLEDGMENTS We gratefully acknowledge Mentor Graphics’ generous donation of a Veloce Solo hardware emulation system, software and workstations. We also acknowledge the financial support of Gregory Hinckley. Finally, thanks to the CAT team for their diligence and flexibility.
INFRASTRUCTURE
[1]
Commercial design and verification tools, while capable and robust, are very complex and the learning curve is steep. We created a web site with links to all available training manuals, documentation, and training videos as a resource to students. To support the project course, we created a Wiki, so students could create project pages and post descriptions of their proposed projects with links to SVN repositories for maintaining their source code and testbenches to facilitate collaborative work. We created discussion threads that students could check when encountering problems to see if solutions had already been posted, and to post a problem or question that could be answered by other students or the course TAs who monitor the Wiki.
[2]
[3]
[4]
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REFERENCES M. Wannemacher, M. Munteanu, S. Perret, R. Singer, "Taking the best out of two worlds: prototyping and hardware emulation," Seventh IEEE International High-Level Design Validation and Test Workshop (HLDVT'02), 2002, pp.156-161. P. Rashinkar, P. Paterson, and L. Singh, System-On-AChip Verification: Methodology and Techniques, Kluwer, 2000, p. 153. I. Mavroidis and I. Papaefstathiou. “Efficient testbench code synthesis for a hardware emulator system,” Proceedings of the Conference on Design, Automation and Test in Europe (DATE '07). EDA Consortium, San Jose, CA, USA, pp. 888-893. Mentor Graphics, “The Target Platform Methodology for HW/SW Debugging Before Silicon”, White Paper, url: www.mentor.com
