Introduction to Deep Submicron CMOS Device ...

Introduction to Deep Submicron CMOS Device Technology & Its Impact on Circuit Design Alvin Loke, Tin Tin Wee, Mike Gilsdorf, Tom Cynkar & Jim Pfiester Imaging Solutions Division, Fort Collins, Colorado

IEEE Solid-State Circuits Society Seminar Vancouver Chapter February 23, 2006

Loke et al. Avago Technologies

Slide 1

Outline • Part 1 • CMOS Technology Trends • MOSFET Basics • Lithography • Deep Submicron FET Fabrication Sequence • Enabling Device & Equipment Technologies • Part 2 • FET Non-idealities & Second-Order Effects • Impact of Technology Advances on Circuit Design • Process Variations in Manufacturing • Conclusions


Slide 2

Evolution of IC Technology I can see Waldo, but where’s the transistor? M9 M5 M4

Al (0.5%Cu)

M8 M7

Cu

M6

M3 oxide (SiO2 ) M2

Low-K

M5 M4 M3 M2

M1

M1 1st Fabricated IC (Texas Instruments, 1958)

0.25µm CMOS (Motorola, 1996)

90nm CMOS (TSMC, 2002)

Is the transistor getting less important? Loke et al. Avago Technologies

Slide 3

CMOS Scaling is Alive & Well Transistors Are Picking Up The Slack • Where are we now? • 130nm & 90nm in volume manufacturing (8-inch wafers) • 65nm early production in progress (12-inch wafers) • Key trends: • Gate CD* scaling is more aggressive than interconnect scaling • Scaling driven by exclusively by digital circuit needs 90nm Technology

59nm Source: Thompson et al., Intel (2002)


Source: Wu et al., TSMC (2002)

* CD = critical dimension Slide 4

Why Aggressive FET Scaling? tdelay ≈

Cload ∆V IFET

• The road to higher digital performance reduce parasitics (largely dominated by wires & gate load) • Cload↓ • ∆V ↓ reduce VDD or logic swing, need for core & I/O FET’s • IFET ↑ all about moving charge quickly • Major hiccup along the way • Interconnect scaling much more difficult than anticipated, especially Cu/low-K reliability

Stress-Induced Voiding

• How to beef up IFET? • Tweak with µ, Cox, L & VT Idsat ≈ ½ µCox (W/L) (VGS – VT)2

Got redundant vias?

• Technology scaling not necessarily compatible with analog design


Slide 5

Why Should Designers Care So Much About Technology Details? • Technology dictates performance limitations • Simulating layout-extracted parasitics now even more critical • Statistical design considerations necessary for circuit functionality • Technology-related surprises keep showing up as we keep scaling • Implementation of accurate models is ALWAYS late • Live with new technology-related effects & issues before they are included in simulations • New model implementations not necessarily accurate or reliable • Meanwhile, learn to either mitigate or exploit these effects • Keeping your foundry partner honest is key to silicon success • Job security ☺


Slide 6

MOS Fundamentals • VT = FET ON voltage, i.e., gate voltage required to form inversion layer connecting source & drain by shorting out back-to-back pn-junctions with substrate depletion charge per unit area Qdep VT = VFB + 2φb + = qNAxdep ∝ NA (xdep ∝1/ NA) Cox Remember ∇ • E = ρ / ε ? bulk potential flatband (offset) voltage due to oxide charge & work function difference

silicon surface n+ source

N kBT ln A q ni

φb =

poly gate +++++++++++++++ ++++++++++++++++ – – – – – – – – – – – – – – – – –

– –

–

– –

–

– –

–

– –

–

p-substrate


oxide capacitance per unit area = εox / tox

–

n– inversion layer n+ drain

–

Qdep depletion charge Slide 7

Electron Energy Band Diagram Formation of Inversion Layer VT = gate voltage required to reverse doping of silicon surface, i.e., move φs by 2φb flatband (no field in silicon) M O S

onset of inversion (surface is undoped) M O S

silicon surface

φs

EF

φb

φs = φb

φb =

N kBT ln A q ni


EC Ei EF EV

onset of strong inversion (VT condition) M O S inversion layer

φb

φb

φs

VT

φs = 0

VT = VFB + 2φb +

φs

φs φs = -φb

Qdep Cox

offset bulk oxide drop drop Slide 8

All the Action is at the Surface

VGS = 0 VDS = 0 (no net current flow) Large source barrier (back-to-back diodes) VGS ≈ VT VDS = 0 (no net current flow) Source barrier is lowered Surface is inverted electron current

VGS > VT VDS > 0 (net source-to-drain current flow) Carriers easily overcome source barrier Surface is strongly inverted

Source: Sze (1981) Loke et al. Avago Technologies

Slide 9

Life’s Never So Perfect Ideal MOSFET = voltage-controlled current source (saturation) Ideal

Reality

IDS

IDS

VGS

VGS

VDS

VDS

We’ll plunge into a lot of neat second-order effects. But first, we need to understand what physical structure we’re dealing with, and how it has evolved with scaling … Loke et al. Avago Technologies

Slide 10

Warp Speed Ahead

Short-Channel Effect (SCE)

VT rolloff at shorter L since less charge must be depleted to achieve surface inversion

poly gate n+

n+

VT

p-substrate depleted by gate charge Drawn Channel Length, L

• Prominent in older CMOS technologies

junction depletion region

poly gate n+

n+ p-substrate

• How to minimize SCE? • Minimize volume of charge depleted by source/drain junctions • Higher substrate doping for thinner junction depletion regions (xdep ∝1/ N ) • Higher VT & junction capacitance not consistent with scaling • Shallower source/drain junctions • Higher source/drain resistance smaller drive currents • Tighter gate coupling to surface potential • Thinner gate oxide of surface potential direct tunneling leakage • Higher K gate dielectrics • Other SCE problems: large electric fields Loke et al. Avago Technologies

carrier vsat & µ degradation Slide 11

Lithography Trends What 1µm Barrier??? Resolution =

k1 λ NA

• • • • •

Refractive projection (4×) optics More aggressive CD’s shorter λ Higher NA lenses $$$ Larger field sizes (increased integration) Now over 25% of total wafer cost

$$$

k1 = ƒ (resist quality, resolution tricks) 436nm 365nm 365nm 436nm

Source: ICKnowledge.com (2003) Loke et al. Avago Technologies

Slide 12

Step-and-Scan Projection Lithography Beyond 0.35µm Technology • Slide both reticle & wafer across narrow slit of light • Aberration-free high-NA optics only required along 1-D but now requires highprecision constant-velocity stages • Still much cheaper than high-NA optics optimized in 2-D • 6” x 6” physical reticle size (4× reduction) • 25 x 33mm or 26 x 32mm field size shorter edge limited by slit width • Relatively weak intensity of deep-UV source required development of very sensitive chemically-amplified resists for throughput

Deep-UV Slit Source Excimer Laser KrF (248nm) or ArF (193nm)

Source: Nikon Loke et al. Avago Technologies

Slide 13

Key Resolution Enhancement Tricks • Sharp features are lost because diffraction attenuates & distorts higher spatial frequencies (mask behaving as low-pass optical filter) • Compensate for diffraction effects when printing feature sizes > VT Idsat ≈ ½ µCox (W/L) (VGS - VT

W/L=0.3/0.3µm 1.2

)2

W/L=1.2/0.3µm W/L=4.8/0.3µm

Gate Overdrive Threshold Voltage

VGS W/L

0.6 0.4 0.2 0.0

Temperature (C) Loke et al. Avago Technologies

Temperature (C)

0 10 20 30 40 50 60 70 80 90 100 110

nom-VT 90nm core nFET

0.8

0 10 20 30 40 50 60 70 80 90 100 110 0 10 20 30 40 50 60 70 80 90 100 110

50µA

Voltage (V)

1.0

Temperature (C) Slide 52

Impact of Halos on rout • Halo at source side suppresses SCE in short-channel devices • Halo at drain side creates Drain-Induced Threshold Shift (DITS) in long-channel devices • Drain bias very effective in modulating drain halo barrier VT ↓ Ids ↑ • Worse DIBL compared to uniform-doped FET • Can degrade FET rout by 10-100×!!! • Critical limitation for building current sources (cascoding difficult with low VDD) uniform-doped • Asymmetric FET’s with only source-side halo shown to improve rout significantly halo

CB

source

drain

VD

Source: Cao et al., UC Berkeley (1999)

• Less degradation for devices with weaker halos • Modeled in BSIM4 not BSIM3, but still need improvement


Slide 53

Impact of Halos on Gate Capacitance • Halo implant increases off-state gate capacitance • Impact is worst for short-channel devices where halos contribute most significantly to channel doping • BSIM3 & BSIM4 models can reasonably account for poly depletion & charge centroid effects, but implementation is largely mathematical fitting

depletion

Gate

Source

halo

edge of depletion region

retrograded well

C-V Characteristics of VCO Varactor 10

inversion

range of interest

Gate

8

inversion layer

C

parallel

(pF)

Source 6

4

2

0 -2.0

Measurement Simulation - Original Fit Simulation - Improved Fit -1.5

-1.0

-0.5

0.0

depletion capacitance modeling error 0.5

1.0

1.5

2.0

relative LOW doping

HIGH

V (V) gs


Slide 54

Contact-to-Poly Capacitance • Can add substantial parasitic capacitive coupling between gate & source/drain • Worse if Miller multiplication exists, i,e, diffusion node is not AC ground & moves in opposite direction to gate signal • Nitride spacer makes matters worse contact-to-poly capacitance contact tungsten contact

STI oxide

poly gate nitride spacer

poly-Si gate

active area

Cross-sectional SEM of 90nm CMOS


ILD0

source/ drain

spacer active

Slide 55

Active Area Mechanical Stress (LOD) Effect • Silicon is piezoelectric – electrical properties (m*, Eg, VT, …) depends on mechanical stress state • Compression slower nFET, faster pFET • Tension faster nFET, slower pFET • STI compression in Si channel due to 10x CTE mismatch between Si & SiO2 and compressive stress of HDP-CVD SiO2 film affects digital device ratios • Ids can easily change by 15-20% • Channel stress is strong function of distance from poly to active edge SA

SB

high compression

SA

SB

lower compression

• Can play tricks with tensile spacer & silicide films to relieve channel stress • Modeled in BSIM4 not BSIM3 Loke et al. Avago Technologies

Source: Xi et al., UC Berkeley (2003)

Slide 56

Layout Implications of LOD Effect Layout Guidelines for Optimal Matching • Same L & W • Same active area size, shape & orientation (SA, SB) • Same environment

BAD!

IOUT

GND IIN

Example: Current Mirror IIN

IIN

CHEAP FIX

IOUT

IOUT GND IIN

85°C

ANAL RETENTION ☺

IOUT

Source: ST Microelectronics (2004)

GND Loke et al. Avago Technologies

Slide 57

Characterizing Process Variations • Statistical variations in IC manufacturing characteristics

variations in FET

• Circuits must function across operating VDD & temperature but also across statistically acceptable process tolerances • Summarized by spread in nFET & pFET VT’s, or in Idsat’s, i.e., use VT or Idsat to summarize cumulative effect of ALL process variances • Consider die-to-die, wafer-to-wafer & lot-to-lot variations Idsat ∝ (VDD–VT) 2 FS

SS

SF

acceptable pFET VT

TT FF

SF nFET VT


pFET Idsat

F = fast T = typical S = slow

FF

TT SS

FS nFET Idsat Slide 58

Correlated vs. Uncorrelated Process Variations • Elliptical 2-D Gaussian distribution from natural variations with no deliberate retargetting of process parameters correlated variations due to common processes e.g., poly photo/etch CD & gate oxide thickness

10/0.13µm pFET Idsat (mA)

4.0

3.5

FF SF

3.0 σ

3.0

2.5 σ

TT

Measurements SPICE Targets

2.5

2.0

SS

FS

uncorrelated variations due to uncommon 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 10/0.13µm nFET Idsat (mA) processes e.g., channel & well ion implants • Tougher to control poly CD than implant doses 1.5


Slide 59

Skew Process for Design Margin Verification • Process wafers with Idsat’s that target SPICE corners of acceptable distribution • Statistical distribution is cumulative result of ALL variations for processes targetted as NOMINAL • Countless possibilities of tweaks to achieve skew nFET/pFET Idsat combination • Fab typically employs SIMPLE means of retargetting nFET & pFET Idsat’s with very few deliberate non-nominal process tweaks • FF vs. SS • Adjust poly CD, no change in gate oxide thickness • Nominal implant doses • FS vs. SF • Adjust surface channel or halo implant dose • Nominal poly CD & gate oxide thickness • Consequences • Nominal & skew results frequently miss intended targets since nominal (by definition) can land anywhere in distribution • Not 100% representative of natural process corners • Decent approximation for vanilla digital circuits • May be bad approximation for some analog & high-speed digital circuits if they are insensitive to selected tweaks Loke et al. Avago Technologies

Slide 60

Impact of FET Mismatch 130nm Differential Amplifier Example

bias

waveforms should be differential

outin+

out+ in-

• Extensive work in FET mismatch modeling, pioneered for data converters • Pelgrom’s basic model (applicable not just to FETs)

σ ∆V

T


1 ∝ WL Slide 61

Technology Options Looking Forward Idsat ≈ ½ µCox (W/L) (VGS – VT)2 • Make faster FETs by increasing Cox or µ • Increase Cox • High-K gate dielectric (e.g., HfSiON) tighter gate coupling, lower gate leakage • Metal/silicided gate (e.g., W) circumvent poly gate depletion • Development is facing tough integration problems (low crystallization temperature, interface quality, hysteresis, mobility) • Likely not ready for initial 45nm production • Increase µ • Apply mechanical strain to channel perturbs m* in E-k diagram • Improved Ion/Ioff performance without sacrificing leakage • Remember: nFET likes tension, pFET likes compression • Emphasis on gate & source/drain straining, not substrate straining • Already used by Intel & IBM at 90nm, TSMC starting at 65nm Loke et al. Avago Technologies

Slide 62

Strain Engineering Basis of High Performance in 65nm & 45nm • IBM example using Dual Stress Liners (DSL) – nitride liners

Tensile nit

Contact

Compr nit

N

P ST

tensile

Compr

N

P

Source: Chan, IBM (CICC 2005)


Slide 63

The Silicon-On-Insulator (SOI) Niche partially-depleted (PD-SOI)

fully-depleted (FD-SOI)

buried oxide

buried oxide

• Only PD-SOI in production so far • Applications: high-end processors (e.g., IBM Cell, AMD) • What’s hot? • Low junction capacitance • No body effect – allows taller FET stack with low VDD • Steeper subthreshold characteristic (FD-SOI only) • What’s not? • Substrate memory effect – substrate hacky-sacked capacitively • Substrate heating – buried oxide is good insulator • Expensive substrate • In most applications, bulk CMOS is still the way to go Loke et al. Avago Technologies

Slide 64

The Near Future of Patterning Immersion Lithography • Remember oil immersion microscopy in biology class? • Extend resolution of refractive optics by squirting water puddle on wafer surface prior to exposure • nwater ~1.45 vs. nair ~ 1 • Tedious but much cheaper than big switch to 157nm reflective optics • Will be mainstream at 45nm Resolution =

k1 λ NA

NA = n sin α = d / 2 f

Source: ICKnowledge.com (2003)


Slide 65

Conclusions • CMOS scaling continues to be driven by digital circuit needs, analog modules available at a premium • New learning expected in 65nm & 45nm CMOS front-end as we cope with design implications of strain engineering • Back-end advances in 65nm & 45nm CMOS are incremental • Always a time lag for SPICE models to include new effects • Huge issue since tapeout mistakes are costlier than ever • Need to work closely with technology providers to quickly find out about these new effects • Account for them or avoid them!!! • Statistical & layout considerations more critical than ever • Designers with intimate knowledge of technology are best positioned to avoid pitfalls & to turn bugs into features Loke et al. Avago Technologies

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References (Part 1) • • • • • • • • • •

International Technology Roadmap for Semiconductors, Front End Processes (2003 Edition), 2003. Technology Backgrounder: Immersion Lithography, ICKnowledge.com, 2003. Technology Backgrounder: Atomic Layer Deposition, ICKnowledge.com, 2003. H.-S. P. Wong, “Beyond the Conventional Transistor,” IBM Journal of Research & Development, vol. 46, no. 2/3, pp. 133-168, Mar. 2002. C. R. Cleavelin, “Front End Manufacturing Technology,” IEEE IEDM Short Course on The Future of Semiconductor Manufacturing, Dec. 2002. D. Harame, “RF Device Technologies,” IEEE IEDM Short Course on RF Circuit Design for Communication Systems, Dec. 2002. S. Thompson et al., “A 90nm Logic Technology Featuring 50nm Strained Silicon Channel Transistors, 7 Levels of Cu Interconnect, Low k ILD, and 1µm2 SRAM Cell,” IEEE IEDM Tech. Digest, pp. 61-64, Dec. 2002. C. C. Wu et al., “A 90nm CMOS Device Technology with High-Speed , General-Purpose, and Low-Leakage Transistors for System on Chip Applications,” IEEE IEDM Tech. Digest, pp. 65-68, Dec. 2002. J. D. Plummer et al., Silicon VLSI Technology– Fundamentals, Practice and Modeling, Prentice-Hall, 2000. S.M. Sze, Physics of Semiconductor Devices (2nd ed.), John Wiley & Sons, 1981.


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References (Part 2) • • • • • • • • • • • • • •

V. W. C. Chan et al., “Strain Engineering for CMOS Performance Improvement,” IEEE Custom Integrated Circuit Conf., Sept. 2005. T. B. Hook et al., “Lateral Ion Implant Straggle and Mask Proximity Effect,” IEEE Trans. Electron Devices, vol. 50, no. 9, pp. 1946-1951, Sept. 2003. J. Assenmacher, “BSIM4 Modeling and Parameter Extraction,” Technical Univ. Berlin Analog Integrated Circuits Workshop, Mar. 2003. X. Xi et al., BSIM4.3.0 MOSFET Model – User’s Manual, The Regents of the University of California at Berkeley, 2003. Y. Taur, “CMOS Design Near the Limit of Scaling,” IBM Journal of Research & Development, vol. 46, no. 2/3, pp. 213222, Mar. 2002. C. R. Cleavelin, “Front End Manufacturing Technology,” IEEE IEDM Short Course on The Future of Semiconductor Manufacturing, Dec. 2002. R. Rios et al., “A Three-Transistor Threshold Voltage Model for Halo Processes,” IEEE IEDM Tech. Digest, pp. 113-116, Dec. 2002. R.A. Bianchi et al., “Accurate Modeling of Trench Isolation Induced Mechanical Stress Effects on MOSFET Electrical Performance,” IEEE IEDM Tech. Digest, pp. 117-120, Dec. 2002. B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001. K. M. Cao et al., “Modeling of Pocket Implanted MOSFETs for Anomalous Analog Behavior,” IEEE IEDM Tech. Digest, pp. 171-120, Dec. 1999. A. Chatterjee et al., “Transistor Design Issues in Integrating Analog Functions with High Performance Digital CMOS,” IEEE Symp. VLSI Technology Tech. Digest, pp. 147-148, June 1999. T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, 1998. D. P. Foty, MOSFET Modeling with SPICE: Principles and Practice, Prentice-Hall, 1996. A. Beiser, Concepts in modern Physics (4th ed.), McGraw-Hill, 1987.


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