Investigations of high-performance GaAs solar cells grown on Ge-Si ...

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 6, JUNE 2005

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Investigations of High-Performance GaAs Solar Cells Grown on Ge–Si1 xGex–Si Substrates Carrie L. Andre, John A. Carlin, John J. Boeckl, David M. Wilt, M. A. Smith, A. J. Pitera, M. L. Lee, Eugene A. Fitzgerald, Member, IEEE, and Steven A. Ringel, Senior Member, IEEE Abstract—High-performance p+ n GaAs solar cells were grown and processed on compositionally graded Ge–Si1 Ge –Si (SiGe) substrates. Total area efficiencies of 18.1% under the AM1.5-G spectrum were measured for 0.0444 cm2 solar cells. This high efficiency is attributed to the very high open-circuit voltages (980 mV (AM0) and 973 mV (AM1.5-G)) that were achieved by the reduction in threading dislocation density enabled by the SiGe buffers, and thus reduced carrier recombination losses. This is the highest independently confirmed efficiency and open-circuit voltage for a GaAs solar cell grown on a Si-based substrate to date. Larger area solar cells were also studied in order to examine the impact of device area on GaAs-on-SiGe solar cell performance; we found that an increase in device area from 0.36 to 4.0 cm2 did not degrade the measured performance characteristics for cells processed on identical substrates. Moreover, the device performance uniformity for large area heteroepitaxial cells is consistent with that of homoepitaxial cells; thus, device growth and processing on SiGe substrates did not introduce added performance variations. These results demonstrate that using SiGe interlayers to produce “virtual” Ge substrates may provide a robust method for scaleable integration of high performance III-V photovoltaics devices with large area Si wafers. Index Terms—Dislocation, GaAs, heteroepitaxy, integration, lattice-mismatch, metamorphic, photovoltaic, Si, SiGe, solar cell.

Manuscript received September 13, 2004; revised December 17, 2004. This work was supported in part by the National Aeronautics and Space Administration under Grant NCC3-974, in part by the National Renewable Energy Laboratory under Grant ACQ-1-30619-06, in part by the Army Research Office under Grant (DAAD 19-01-0588), in part by the National Science Foundation under FRG Grants DMR-007-6362 and DMR-0313468, and in part by an Ohio Space Grant Consortium Fellowship (CLA). The review of this paper was arranged by Editor P. Panayotatos. C. L. Andre was with the Electrical and Computer Engineering Department, The Ohio State University, Columbus, OH 43210 USA. She is now with Akzo Nobel High Purity Metalorganics, Chicago, IL 60607 USA (e-mail: carrie.andre@akzonobel-pc.com). J. A. Carlin is with Amberwave Systems Corporation, Salem, NH 03070 USA. J. J. Boeckl was with the Electrical and Computer Engineering Department, The Ohio State University, Columbus, OH 43210 USA. She is now with the Air Force Research Laboratory’s Materials and Manufacturing Directorate, WrightPatterson AFB, OH 45433 USA. D. M. Wilt is with the Photovoltaic and Space Environment Branch, NASA John H. Glenn Research Center at Lewis Field, Cleveland, OH 44135 USA. M. A. Smith is with the Ohio Aerospace Institute, Cleveland, OH 44135 USA. A. J. Pitera, M. L. Lee, and E. A. Fitzgerald are with the Department of Materials Science and Engineering, Massachusetts Institute of Technology, Cambridge, MA 02139 USA. S. A. Ringel is with the Electrical and Computer Engineering Department, The Ohio State University, Columbus, OH 43210 USA (e-mail: ringel@ece.edu). Digital Object Identifier 10.1109/TED.2005.848117

I. INTRODUCTION

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HE ability to epitaxially integrate III-V compounds with Si substrates has been vigorously investigated for over 20 years. Although the prospect of integrating the complementary technologies of III-V optoelectronics and Si-based very largescale integrated circuitry to address the interconnect bottleneck has fueled much research in the field, the photovoltaic community has also played a major but parallel role in the development of III-V/Si integration due to a separate need for mechanically strong, large area, less expensive solar cells for both space and terrestrial power applications. However, progress in direct epitaxial methods for III-V/Si integration reached a plateau that has persisted since the late 1980s/early 1990s due to the inability to further reduce the residual threading dislocation density (TDD) in the lattice-mismatched GaAs layers [1]–[5]. The problem of obtaining low dislocation densities is exacerbated by the need to simultaneously inhibit the formation of other defects that may be introduced as a consequence of a given integration approach, such as management of the heterovalent nature of III-V/IV interfaces. This combination of issues, until recently, had presented an apparent roadblock to a robust III-V/Si epitaxial integration solution for device applications. The recent achievement of low TDD, relaxed Ge layers on Ge buffer layers [6], Si via compositionally graded Si combined with the fundamental knowledge base concerning growth nucleation of ideal GaAs–Ge interfaces [7], has provided a breakthrough opportunity. By first accommodating the 4% lattice-mismatch between Si and GaAs in the Group IV, Ge alloy system, a “virtual” Ge substrate is achieved for Si subsequent low lattice-mismatch GaAs epitaxy. The GaAs epitaxial process can then focus on control of the polar/nonpolar low-mismatch GaAs–Ge interface with respect to suppression of both anti-phase domain formation and cross-diffusion with minimal concern over the large lattice mismatch between GaAs and Si. III-V/Si integration using SiGe substrates has achieved cm , which TDDs in relaxed GaAs epilayers of translates to high minority carrier lifetimes in n-type GaAs on Si of 10 ns [8]. In this paper, this integration method is used to demonstrate GaAs–SiGe one-sun solar cell efficiencies in excess of 18%. Moreover, area-independent GaAs–SiGe cell performance up to at least 4.0 cm is shown, demonstrating the scalability of this approach. II. DEVICE GROWTH, PROCESSING, AND MEASUREMENTS Compositionally graded, n-type relaxed SiGe layers were grown on (100) oriented Si substrates with a 6 off-cut toward

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the nearest {111} by ultrahigh vacuum chemical vapor deposition. A chemical mechanical polish was employed at Si Ge followed by growth of the remainder of the Si Ge layers up to 100% Ge, in order to achieve a lower residual TDD [6]. Two separate sets of SiGe substrates were used in this study with the same, nominal buffer design. The first set of SiGe substrates cm 4–in Si wafers with a doping were grown on 0.03 concentration in the epitaxial SiGe layers of cm and resulted in a TDD of cm . The second set of SiGe substrates were grown on 0.01 cm 6-in Si wafers; cm , but the the SiGe layers were again doped final TDD was cm . TDD values in the final Ge layers were measured using etch pit density (EPD) studies [9], [10]. The factor of 2 variation in final TDD is typical of our SiGe growth process at this stage of development, and the influence of such variations on the minority carrier lifetimes of subsequently grown GaAs have been reported [11]. The impact of this change in TDD on device performance characteristics is discussed below. All solar cell structures were grown by low-pressure metal–organic chemical vapor deposition (MOCVD), after deposition of a 0.1- m GaAs nucleation layer by solid source molecular beam epitaxy (SSMBE) on the Ge termination layer of the SiGe substrates. The SSMBE GaAs initiation conditions include the deposition of an epitaxial Ge layer ( 30 nm), a substrate anneal at 640 C, ten periods of migration-enhanced epitaxy of GaAs at 350 C beginning with an As prelayer, and concludes with a 0.1- m layer of GaAs grown at a rate of 0.1 m/h and a substrate temperature of 500 C. This initiation procedure suppresses antiphase domain (APD) formation and minimizes cross-diffusion, which allows the use of thin GaAs buffer layers of less than 200 nm [8]. Further details concerning the SSMBE GaAs initiation can be found in [7], [8], while the influence of MOCVD over growth on these SSMBE initiation layers can be found in [11] and [12]. The horizontal geometry low-pressure MOCVD reactor used for growth of solar cell device layers accommodates a single 2–in wafer, maintains a pressure of 190 torr, and uses RF heating with a thermocouple placed below the susceptor [13]. The GaAs and In Ga P layers were grown at a substrate temperature m/h, and a V/III ratio of 100. of 620 C, a growth rate Silane and diethylzinc were used as n-type and p-type dopant sources, respectively, and the doping concentrations were calibrated by electrochemical capacitance voltage measurements. Fig. 1 shows the standard GaAs heteroface solar cell structure that was used for all devices. Fig. 2 shows a cross-sectional transmission electron microscopy (X-TEM) image of the solar cell structure grown on a SiGe substrate; this image shows the GaAs conIII-V device layers (with the exception of the p tact layer) and the Ge termination layer of the SiGe substrate as well as some of the SiGe step-graded buffer layers. No structural defect formation at the SSMBE/MOCVD regrowth interface was observed by X-TEM; moreover, higher magnification images confirm the suppression of APD disorder at the SSMBE GaAs–Ge interface. The devices were processed using conventional photolithography and wet chemical etching. Ohmic contacts were made to the p-type GaAs contact layer using either unannealed Cr:Au


Fig. 1. p =n GaAs solar cell device structure grown by MOCVD on Ge –Si substrates. Ge–Si

Fig. 2. X-TEM image of a p =n GaAs solar cell grown by MOCVD on a Ge –Si substrate. Ge–Si

or annealed Zn:Au and to the Ge coated back of the SiGe substrates using Al with a 15-min anneal at 400 C or Au:Ag with a 5-min anneal at 400 C. Before depositing the back contact, the front surface was protected and the back surface was etched with NH OH–H O -based and HCl-based etches to ensure the removal of residual III-V layers. The variation in contact metallization resulted from the fact that devices were processed both at The Ohio State University and at NASA Glenn Research Center. The antireflection coating (ARC) consisted of MgF –ZnS–MgF and was deposited in a thermal evaporator. Due to uncontrolled variations in the thickness of ARC layers, the increase in short-circuit current density for solar cells with different ARC depositions varies between 30%–37% and thus

ANDRE et al.: INVESTIGATIONS OF HIGH-PERFORMANCE GaAs SOLAR CELLS

Fig. 3. Illuminated J–V curves under AM0 and AM1.5-G spectra for a GaAs Ge –Si substrate. solar cell (area= 0:0444 cm ) grown on a Ge–Si

the changes in measured short-circuit densities for the cells presented in this paper do not necessarily indicate changes in material quality. Illuminated current density versus voltage (J–V) measurements under AM0 and AM1.5-G spectrums were measured at the NASA Glenn Research Center and the National Renewable Energy Laboratory, respectively, in order to determine the short, the open-circuit voltage , the circuit current density of the solar cells for space fill-factor (FF), and the efficiency and terrestrial applications. The solar cells produced had various areas and grid designs; the devices ranged in size from 0.0444, 0.36, 1.0, to 4.0 cm with metal coverage of 10%, 8%, 4%, and 7%, respectively. III. RESULTS AND DISCUSSION Fig. 3 shows the illuminated J–V response for a GaAs solar cell grown on a SiGe substrate. AM1.5-G results are reported for the first time, with energy conversion efficiencies reaching 18.1%. This is the highest independently verified one-sun efficiency reported to date for a single p n or n p junction GaAs solar cell grown on a Si-based substrate [1], [2]. The AM0 results for the same cell are shown in Fig. 3 for comparison; the reported AM0 efficiency of 15.5% is also the highest independently verified efficiency reported to date under this spectrum [2]. The high performance obtained, in spite of the large lattice mismatch (4%) between the fully relaxed GaAs cell and the Si , which substrate, is attributed to the achievement of a high is the consequence of maintaining a low TDD value of cm while simultaneously eliminating other mismatch related defects such as antiphase domains and autodoping, which [7], [8]. Given that the grid shadcould otherwise lower owing for the GaAs–SiGe cell in Fig. 3 is 10%, a more accurate comparison with previous results is obtained by scaling the data in Fig. 3 for a metal coverage 4.5%, commensurate with the GaAs–Si cell from [1] and [2]. This yields efficiencies for GaAs–SiGe of 18.8% and 16.5% at AM1.5-G and AM0, respectively, more than 1% absolute higher than other verified reports. values obtained in this work are responsible for The high the high cell efficiency. Compared with [1] where a TDD of

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cm produced an AM1.5-G of 891 mV, the cm reduction in the TDD in SiGe substrates to reduced the dislocation-mediated depletion region recombination in GaAs–SiGe solar cells and thus increased the to 973 cm mV. The inability to reduce the TDD below using other direct III-V/Si integration methods [5] had been the primary impediment to achieving higher efficiency GaAs-on-Si solar cells which stalled research in this area. Modeling of this values that recombination process has predicted theoretical track the experimental results as a function of TDD for various GaAs–Si and GaAs–SiGe cell structures [1]–[5], [18], [19]. cm is needed Such models predict that a TDD of values in for heteroepitaxial GaAs p n cells to achieve excess of 1000 mV, which would closely match state of the art homoepitaxial GaAs cells. Calculating the TDD tolerance of solar cell performance deobtained as well as the device models pends heavily on the and input parameters used. For example, due to the dislocation-enhanced depletion region recombination in GaAs solar cells grown on SiGe as opposed to GaAs–GaAs, the measured , near , is between 2 and 2.2 compared to ideality factor 1.8 or 1.9 for GaAs–GaAs solar cells of the same cell design are predicted and processing. Ideality factors higher than if the voltage dependence of the depletion width is taken into consideration [20]; however, typical analysis of TDD dependent contributions to the reverse satmodels include only the uration current density [4]. This model fundamentally breaks and down at lower TDD since the diffusion component can both conthe depletion recombination component tribute, resulting in extracted ideality factors of less than 2 when using a single exponential fit to the J–V relation. Moreover, deviations in may also be explained by changes in the deep level characteristics between the homoepitaxial and heteroepitaxial GaAs junctions [20]. Nevertheless, it is of interest to consider the impact of ideality factor variations on GaAs–SiGe cell performance. Here, we calculate the fill-factor (FF) for two cases, and , given a of 973 mV and a of 23.6 mA/cm from Fig. 3. This results in predicted values for the FF and , respectively. Thereof 79.9% and 79.1% for fore, it is fair to conclude that the device performance shown in and FF Fig. 3 agrees with the suggested models and that the is close to the expected limit for this TDD. values obtained for this GaAs solar Considering the high cell and the above analysis, we conclude that the total cell efficiencies presented in Fig. 3 for a GaAs-on-SiGe solar cell are which resulted from a large primarily limited by a reduced grid obscuration (10%), a nonoptimum antireflection coating and poor back surface field [14]. For GaAs–SiGe solar cells with a more optimum ARC and lower grid coverage, we have values of 29.6 and 24.5 mA/cm for AM0 and obtained AM1.5, respectively. Moreover, since the diffusion length of holes in the n-type base are expected to be 2.7 m at this TDD and other GaAs–Si solar cells with higher TDD (lower diffuvalues [1]–[3], increases sion length) have achieved higher in for GaAs–SiGe due to improvements in these factors that are external to the fundamental issue of carrier collection, are cm , practiexpected. Therefore, at a TDD of cally achievable AM1.5-G efficiencies in excess of 20.3% are

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TABLE I PERCENT DEVIATION OF THE MEAN FOR SOLAR CELL PERFORMANCE CHARACTERISTICS MEASURED ON 1.0 cm SOLAR CELLS GROWN ON GaAs AND SiGe SUBSTRATES UNDER AM0 ILLUMINATION

Statistics based on the measurement of eight solar cells grown on GaAs with mean AM0 performance parameters of 1043 mV, 30.3 mA/cm , 81.8%, and 18.9% and six solar cells grown on SiGe with mean AM0 performance parameters of 969.5 mV, 29.4 mA/cm , 69.4%, and 14.4%. The lower FF for GaAs–SiGe is unrelated to crack density, as seen by the low variation.

expected for GaAs–SiGe solar cells. This projection is based on and FF values demonstrated in this paper the experimental value of 26.5 mA/cm , which was reported in [3] for a and a cm based on an empirical fit to AM1.5-G TDD of values for a GaAs solar cells as a function of TDD. Any further reduction in TDD due to the evolution of SiGe substrate technology will serve to decrease minority carrier recombinaand decrease depletion region recomtion that will increase and FF, all bination, which translates directly to increased of which increase the overall cell efficiency. Hence, GaAs–SiGe cell performance will directly track the TDD of the SiGe substrate, with no other parasitic effects. There has been concern whether the thermal expansion mismatch between GaAs and Si, which can cause microcracks in the GaAs epilayer, will limit device area and increase performance variations [14], [15]. To demonstrate the robust nature of the GaAs–SiGe integration method at our current state of development, the variation in the average performance characteristics for six 1.0-cm single-junction GaAs cells grown on SiGe and eight 1.0-cm single-junction GaAs cells grown on GaAs with the same device structure and processing are compared in Table I. We find that the variations in the individual cell perfor, FF, and ) for cells grown on mance characteristics ( , GaAs and on SiGe are comparable and thus the use of a SiGe substrate instead of a GaAs substrate does not lead to added device variation, even though microcracks are present at densities in these GaAs–SiGe cells ranging from 3–72 cm . To consider the impact of microcracks on cell performance more directly, Fig. 4 shows the AM0 illuminated J–V performance for GaAs solar cells with areas of 0.36, 1.0, and 4.0 cm grown on a single SiGe substrate; this represents a factor of ten increase in cell area [14]. These cells were subject to the same substrate, growth, and processing conditions and had an average cm . As seen, the illuminated J–V microcrack density of characteristics are virtually independent of cell area, which indicates that the total number of cracks per cell has not introduced a significant degradation mechanism for large area devices at this point in testing. This large area demonstration, up to 4.0 cm , is an important step toward technological applications where solar cell areas of cm are currently used in tercm are typically used restrial concentrators and areas of in space solar panel arrays. It should be noted that the cell data presented in Fig. 4 were obtained using SiGe substrates with a

Fig. 4. AM0 illuminated J–V curves for GaAs solar cells grown on Ge –Si substrates. The performance characteristics for the 4.0-cm Ge–Si solar cell are included in the figure. There is no systematic variation in cell performance with a ten-old increase in cell area.

TDD of cm , two times higher than the TDD for the cells described earlier. As mentioned above, this variation is typical of our SiGe growth process at present, which reduces the GaAs minority carrier lifetime by a factor of 2 [9], and is not a device area-related effect. This lifetime reduction values from 980 mV shown in Fig. 3 translates into reduced to 940 mV shown in Fig. 4, consistent with theoretical expectations for these TDDs [4], [19]. The reduction in FF to 73% is partly attributed to the slight increase in TDD and to a series resistance source introduced in the processing of these particular cells. FF values of greater than 78% have been achieved for 0.36 cm cells; thus, this reduction in FF is not a fundamental limitation of the GaAs–SiGe integration method and high efficiencies for large area solar cells are expected. However, while this paper does not reveal significant effects related to microcrack density for the scope of this initial work, continued investigations are both necessary and ongoing to explore the relation between microcrack formation and cell characteristics, as well as procedures to completely eliminate their presence for large area III-V/SiGe devices [21]. IV. CONCLUSION GaAs solar cells grown on SiGe substrates with efficiencies of 18.1% under AM1.5-G illumination were demonstrated. The values were achieved by the reduction in depletion rehigh gion recombination that resulted from the lower residual TDD compared with previous GaAs–Si integration methods. The low TDD achieved in the “virtual Ge” substrates was maintained in the GaAs solar cell via controlled III-V epitaxy with no introduction of other efficiency limiting defects. Thus, improvements in cell performance should continue to track decreases in TDD with future advancements in SiGe substrate technology. Moreover, an increase in cell area by a factor of 10 (from 0.36 to 4 and has also cm ) without fundamental degradation in been achieved on identical SiGe substrates, with performance variation consistent with that of companion homoepitaxial cells. This data suggests that there is great promise for the use of SiGe metamorphic buffers for III-V/Si photovoltaics.

ANDRE et al.: INVESTIGATIONS OF HIGH-PERFORMANCE GaAs SOLAR CELLS

ACKNOWLEDGMENT The authors would like to thank E. B. Clark at the NASA Glenn Research Center and R. T. Clark at The Ohio State University for contributions to the growth of these structures, and D. Scheiman at the Ohio Aerospace Institute for AM0 characterization and K. Emery and T. Moriarty at the National Renewable Energy Laboratory for AM1.5 characterization.

REFERENCES [1] S. M. Vernon, S. P. Tobin, V. E. Haven Jr., C. Bajar, and T. M. Dixon, “Efficiency improvements in GaAs-on-Si solar cells,” in Proc. 20th Photov. Spec. Conf., 1988, pp. 481–485. [2] S. P. Tobin, “Progress in gallium arsenide solar cell research,” in Proc. 4th Photov. Science Engineering Conf., 1989, Paper 4.1. [3] S. M. Vernon and S. P. Tobin, “Experimental study of solar cell performance versus dislocation density,” in Proc. 12th Photov. Spec. Conf., 1990, pp. 211–216. [4] M. Yamaguchi and C. Amano, “Efficiency calculations of thin-film GaAs solar cells on Si substrates,” J. Appl. Phys., vol. 58, no. 9, pp. 3601–3606, Nov. 1985. [5] M. Yamaguchi, C. Amano, and Y. Itoh, “Numerical analysis for highefficiency GaAs solar cells fabricated on Si substrates,” J. Appl. Phys., vol. 66, no. 2, pp. 915–919, Jul. 1989. [6] M. T. Currie, S. B. Samavedam, T. A. Langdo, C. W. Leitz, and E. A. Fitzgerald, “Controlling threading dislocation densities in Ge on Si using SiGe layers and chemical-mechanical polishing,” Appl. Phys. Lett., vol. 72, no. 14, pp. 1718–1720, Apr. 1998. [7] R. M. Sieg, S. A. Ringel, S. M. Ting, S. B. Samavedam, M. T. Currie, T. A. Langdo, and E. A. Fitzgerald, “Toward device-quality GaAs Ge = growth by molecular beam epitaxy on offcut Ge/Si = substrates,” J. Vac. Sci. Technol. B, Microelectron. Process. Phenom., vol. 16, no. 3, pp. 1471–1474, May/Jun. 1998. [8] J. A. Carlin, S. A. Ringel, E. A. Fitzgerald, M. Bulsara, and B. M. Keyes, “Impact of GaAs buffer thickness on electronic quality of GaAs grown on graded Ge–GeSi–Si substrates,” Appl. Phys. Lett., vol. 76, no. 14, pp. 1884–1886, Apr. 2000. [9] M. T. Currie, “SiGe virtual substrate engineering for integration of III-V materials, microelectromechanical systems, and strained silicon MOSFETs with silicon,” Ph.D. dissertation, Dept. Mater. Sci. Eng., Mass. Inst. Tech., Cambridge, 2001. [10] J. M. Baribeau, T. E. Jackman, D. C. Houghton, P. Maigne, and M. W. Denhoff, J. Appl. Phys., vol. 63, p. 5738, 1988. [11] C. L. Andre, D. M. Wilt, A. J. Pitera, M. L. Lee, E. A. Fitzgerald, B. M. Keyes, and S. A. Ringel, “Impact of dislocations on minority carrier electron and hole lifetimes in GaAs grown on metamorphic SiGe substrates,” Appl. Phys. Lett., vol. 84, no. 18, pp. 3447–3449, May 2004. [12] J. J. Boeckl, “Microstructural investigations of defects in epitaxial GaAs materials grown on mismatched Ge and SiGe–Si substrates,” Ph.D. dissertation, Dept. Elect. Comput. Eng., The Ohio State Univ., Columbus, 2005. [13] D. M. Wilt, N. S. Fatemi, R. W. Hoffman, P. P. Jenkins, D. J. Brinker, D. Scheiman, R. Lowe, M. Fauer, and R. K. Jain, “High efficiency indium gallium arsenide photovoltaics devices for thermophotovoltaic power systems,” Appl. Phys. Lett., vol. 64, no. 18, pp. 2415–2417, May 1994. [14] J. A. Carlin, M. K. Hudait, S. A. Ringel, D. M. Wilt, E. B. Clark, C. W. Leitz, M. T. Currie, T. A. Langdo, and E. A. Fitzgerald, “High efficiency GaAs-on-Si solar cells with high V using graded GeSi buffers,” in Proc. 28th IEEE Photov. Spec. Conf., 2000, pp. 1006–1011. [15] S. A. Ringel, J. A. Carlin, C. L. Andre, D. M. Wilt, E. B. Clark, P. Jenkins, D. Scheiman, C. W. Leitz, A. A. Allerman, and E. A. Fitzgerald, “Single-junction InGaP/GaAs solar cells grown on Si substrates with SiGe buffer layers,” Prog. Phot., vol. 10, pp. 417–426, Sep. 2002. [16] S. P. Tobin, S. M. Vernon, V. E. Haven Jr., C. Bajar, M. M. Sanfacon, and S. J. Pearton, “Factors controlling efficiency of GaAs-on-Si solar cells,” in Proc. 19th IEEE Photov. Spec. Conf., 1987, pp. 338–344. [17] R. P. Gale, B. Tsaur, J. C. C. Fan, F. M. Davis, and G. W. Turner, “GaAs shallow-homojunction solar cells on epitaxial Ge grown on Si substrates,” in Proc. 15th IEEE Photov. Spec. Conf., 1981, pp. 1051–1055.

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[18] S. A. Ringel, C. L. Andre, M. K. Hudait, D. M. Wilt, E. B. Clark, A. J. Pitera, M. L. Lee, E. A. Fitzgerald, M. Carroll, M. Erdtmann, J. A. Carlin, and B. M. Keyes, “Toward high performance n/p GaAs solar cells grown on low dislocation density p-type SiGe substrates,” in Proc. 3rd World Conf. Photov. Energy Conv., vol. 1, 2003, pp. 612–615. [19] C. L. Andre, A. Khan, M. Gonzalez, M. K. Hudait, E. A. Fitzgerald, J. A. Carlin, M. T. Currie, C. W. Leitz, T. A. Langdo, E. B. Clark, D. M. Wilt, and S. A. Ringel, “Impact of threading dislocations on both n/p and p/n single junction GaAs cells grown on Ge/SiGe/Si substrates,” in Proc. 29th IEEE Photov. Spec. Conf., 2002, pp. 1043–1046. [20] C. T. Sah, R. N. Noyce, and W. Shockley, “Carrier generation and recombination in P-N junctions and P-N junction characteristics,” Proc. IRE, pp. 1228–1243, Sep. 1957. [21] D. M. Wilt, E. B. Clark, A. Pal, S. A. Ringel, C. L. Andre, M. A. Smith, D. Scheiman, P. P. Jenkins, E. A. Fitzgerald, and R. J. Walters, “LEO flight testing of GaAs on Si solar cells aboard MISSE5,” in Proc. 31st IEEE Photov. Spec. Conf., 2004, pp. 3602–3605.

Carrie L. Andre received the B.S. degree from the Cooper Union for the Advancement of Science and Art, New York, in 1998, and the M.S. and Ph.D. degrees from The Ohio State University (OSU), Columbus, in 2000 and 2004, respectively, all in electrical engineering. She received the University Fellowship, the Ohio Space Grant Consortium Doctoral Fellowship, and the Presidential Fellowship while attending OSU. She has also performed research at the Stanford Linear Accelerator Center, the Center for Nonlinear Dynamics at the University of Texas at Austin, and the Cooper Union, before beginning her graduate research at OSU. Her research interests include lattice-mismatched epi-layer growth and material characterization for photovoltaics and optoelectronics devices. Her special area of expertise involves the design and realization of lattice-mismatched multijunction photovoltaic devices that account for dislocation densities. She is currently with Akzo Nobel High Purity Metalorganics, Chicago, IL.

John A. Carlin received the B.S. degree in electrical and computer engineering from The Ohio State University (OSU), Columbus, in 1995, and the Ph.D. degree in electrical engineering from OSU in 2001 while researching the application of high-quality GeSi graded buffers for the integration of III-V minority carrier devices on Si, specifically high efficiency III-V space photovoltaics grown by both molecular-beam epitaxy and chemical vapor deposition. His current research interests include the integration of mismatched materials for device applications. He is a Research Scientist at Amberwave Systems Corporation, Salem, NH.

John J. Boeckl received the B.S. and M.S. degrees in electrical engineering from Cleveland State University, Cleveland, OH, in 1989 and 1997, respectively, where he is currently pursuing the Ph.D. degree on the structural and electrical characterization of III-V on group IV heteroepitaxy. From 1989 to 1996 he was a Civilian Employee with the U.S. Air Force at Newark Air Force Base, Newark, OH, managing and operating a failure analysis laboratory for semiconductor components. In 1996, he was awarded a Palace Knight position through Wright Patterson Air Force Base (WPAFB), Dayton, OH. Currently, he is a Research Scientist at the Air Force Research Laboratory’s Materials and Manufacturing Directorate, WPAFB, where his studies focus on the development of nanomaterials and their characterization with electron microscopy.

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David M. Wilt received the B.S. degree in physics in 1984 from Kent State University, Kent, OH, and the M.S. degree in reliability engineering from Cleveland State University, Cleveland, OH, in 1998. Since 1984, he has been a Researcher in the Photovoltaic and Space Environments Branch, NASA John H. Glenn Research Center, Cleveland, where he has focused on the organo–metallic vapor phase epitaxy of III-V semiconductor materials, primarily for photovoltaic applications. He has authored or coauthored more than 90 papers and has three issued U.S. patents. Since 1998, he has served as the Lead for the Advanced III-V Photovoltaic Group at NASA. His current research interests include thermophotovoltaic energy conversion, alpha voltaic energy conversion, lattice mismatched epitaxy, polycrystalline III-V epitaxy, and micropower systems.


Eugene A. Fitzgerald (M’01) received the B.S. degree from Massachusetts Institute of Technology (MIT), Cambridge, in 1985, and the Ph.D. degree from Cornell University, Ithaca, NY, in 1989, both in materials science and engineering. He was a Researcher in lattice-mismatched materials and devices at AT&T Bell Laboratories from 1988 to 1994. In 1994, he became an Associate Professor, Department of Materials Science and Engineering, MIT, where he is currently a Full Professor. In 1998, he co-founded AmberWave Systems Corporation, Salem, NH. He has coauthored or authored more than 150 papers, predominately in the field of lattice-mismatched materials and devices, and he has 28 issued U.S. patents. His interests include engineered substrates and devices, in particular strained SiGe and III-V-based devices. . Dr. Fitzgerald is a member of APS, MRS, TMS, and ECS. He is the recipient of the TMS 1994 Robert Lansing Hardy Medal Award. In 2000, he received a Lord Career Development Chair, and in 2003 became the Merton C. Flemings—SMA Professor of Materials Engineering. He became a Fellow in the Singapore-MIT Alliance in 1999

M. A. Smith, photograph and biography unavailable at the time of publication.

A. J. Pitera, photograph and biography unavailable at the time of publication.

M. L. Lee, photograph and biography unavailable at the time of publication.

Steven A. Ringel (M’86–SM’97) received the B.S. degree in electrical engineering and the M.S. degree in engineering science from Pennsylvania State University, University Park, in 1984 and 1986, respectively, and the Ph.D. degree in electrical engineering from the Georgia Institute of Technology, Atlanta, in 1991. In 1991, he joined the Department of Electrical Engineering, The Ohio State University (OSU), Columbus, as an Assistant Professor, was promoted to Associate Professor in 1997, and to Full Professor in 2000. He has coauthored or authored more than 175 papers in the fields of lattice-mismatched materials and devices, photovoltaics, and defects in semiconductors. His interests include lattice-mismatched materials and devices, wide bandgap semiconductors, engineered substrates, and alternative energy applications of advanced semiconductor technology. Dr. Ringel is a senior member of AIAA and a member of APS, AAAS, and MRS. He was the recipient of an NSF National Young Investigator Award in 1994. In 1999, he received OSU’s Harrison Award for Excellence in Engineering Education and Research. In 2004, he became the Neal A. Smith Endowed Chair in Electrical Engineering at Ohio State.