Student paper
Isolation Method for Bulk FinFET without Using CMP Process Il Hwan Cho, Junsoo Kim, Il Han Park, Hyungcheol Shin, Byung-Gook Park, Jong Duk Lee, and Jong-Ho Lee# School of Electrical Engineering and Computer Science, Seoul National University, San 56-1, Shinlim-dong, Kwanak-ku, Seoul 151-742, Korea # School of Electronic and Electrical Engineering, Kyungpook National University, Sangyuk-dong, Buk-Gu, Daegu 702-701,Korea Phone: +82-53-950-6561 Fax: +82-53-950-6561 E-mail:
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Chemical mechanical polishing (CMP) process has been widely used to planarize dielectrics, which can apply to the integrated circuits for sub-micron technology.Especially in the process technology below 0.35 µm, the wide range of global planarization[1] is required to secure sufficient depth of focus with the process margin of exposure equipment for fine pattern of process technology. Therefore, the technology of CMP is widely used as an essential process. Such CMP technology must be the essential process which is prospective, but there are a lot of problems to be solved for planarization. For example, nitride residue [2], dishing problems, and generation of various contaminations [3] such as mobile ions produced after the post-CMP process cleaning can be pointed out.In this work, a planarization process for bulk FinFET [4] isolation without using CMP was demonstrated. This isolation process does not use slurry and have no mechanical stress. Therefore it can be free of problems mentioned above. Process steps and features will be presented. Fig. 1 shows a schematic diagram of the fabrication. First, Si trench is formed with a depth of 370 nm by anisotropic dry etch. A layer of SiO2 for isolation was deposited by PECVD and was annealed at 900°C. 38 nm thick Si3N4 was deposited by LPCVD as shown in Fig. 1 (a) for achieving better etch profile of the SiO2 layer. Afterwards, the PR layer was coated and baked as shown in Fig. 1(b) and Fig.2 (a). In this technology, the PR layer is used to expose the oxide surface which has to be etched for planarization. To get an appropriate exposure of the surface of fin bodies, thickness and etch margin of the PR were considered at the same time. Since nonuniformity of PR ashing process increases with the process time, we should decrease PR thickness to get a short ashing process time and uniform ashing profile. We got a 400 nm thick PR with a planar surface by using 1:1 diluted AZ1512 PR with PR thinner, and PR coating conditions with 4000RPM and 30 sec. Another aspect of PR thickness to be considered is thickness margin. The margin is defined as the difference between the PR thickness on the surface of the fin body and the one on the etched Si region, and is determined by the viscosity of PR and RPM of the coating process as shown in Fig. 2(a). We got a margin of about 225 nm which is enough to do following processes. After the PR ashing to a thickness, Si3N4 surface on the fin body was exposed as shown in Fig. 1 (c). Fig. 2 (b) shows a SEM image of a test sample which has no Si3N4 layer but it has the same profile as that of main samples. Exposed Si3N4 layer was etched by anisotropic dry etch process. Because the selectivity of the Si3N4 with the PR layer was not good, thickness of the Si3N4 layer was thin (40 nm) as possible. As shown in Fig. 1(d), the upper side SiO2 surface was exposed after Si3N4 etch, but the SiO2 in the isolation region was protected by the Si3N4 layer during wet etch. There is no damage or dishing on the SiO2 layer under the Si3N4 layer during wet etching, which is one of key benefits of this process compared to conventional CMP process. After PR strip, SiO2 layer was etched in 7:1 BHF solution as shown in Fig.1 (e). Fig 3 (a) shows uncontrolled oxide profile after the wet etch. In this sample, there is no Si3N4 layer and only the PR layer acts as a mask during the wet etch. By adopting the Si3N4 layer we could obtain reasonable etch profile as shown in Fig. 3 (b). We can form a channel on part of side surface exposed by the wet etch. Fig. 4 shows microscope image of active (and fin body) and isolation regions after the nitride strip. There is no dishing effect for the area more than ~50µm×50µm, but oxide layer on large active patterns which will be removed easily by using one additional mask. In the fabrication of body-tied triple-gate MOSFET (bulk FinFET) using CMP [4], Si3N4 spacer was applied to obtain reasonable side surface of the fin body in which the side-channel is formed. We achieved nearly the same profile without adopting CMP process as shown in Fig. 5. We have developed an isolation method which is suitable for bulk FinFET technology without using CMP. Important parameters are PR dilution, coating, ashing, and wet etching of isolation oxide. We found no dishing in large isolation area and obtained reasonable exposure of side surface of the
Student paper
fin body and isolation region. Acknowledgements This work was supported by SystemIC 2010 Project in 2004 References [1] Y.J. Seo. et al., CMP-MIC-2001. p.527, 2001.[2] S.Y.Kim. et al., IUMRS-ICEM-98, p.106, 1998. [3] Y.J. Seo.et al., JKIEEME., Vol.14,No. 1, p.1, 2001.[4] T. Park. et al., VLSI Symp. Tech. Dig.,, p.135, 2003. Uncontrolled oxide profile. (b) Controlled oxide profile in the isolation region. The part of the side surface is exposed by intentionally controlling the etch time
Fig. 1 Fabrication process steps of a bulk FinFET isolation (a) SiO2 and Si3N4 layer deposition after Si trench etching. (b) PR coating and baking (c) PR ashing (d) Si3N4 layer etch (e) PR strip and SiO2 wet etching (f) Si3N4 wet etching
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Fig. 2. Cross sectional SEM images showing PR ashing process for selective wet etching. (a) PR coating and baking. (b) Top side oxide surface exposed after PR ashing.
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Fig. 3. SEM images of oxide etch profile. (a)
Fig. 4. Microscope image of active region formed by our isolation method. There is no SiO2 dishing in wide area trench. But there is SiO2 layer on the large area active patterns.
Fig. 5. SEM image after SiO2 etching. Top and part of side surface of the 50 nm width fin body fin body are exposed by controlling etch time. The channel is formed on the exposed top and side surfaces of the fin body. process.
