John H. Lau, Lim Ying Ying, Lim Teck Guan, Tang Gong Yue, Khong

John H. Lau, Lim Ying Ying, Lim Teck Guan, Tang Gong Yue, Khong Chee Houe, Xiaowu Zhang, Pamidighantam V Ramana, Zhang Jing, Tan Chee Wei, Jayakrishnan Chandrappan, Joey Chai, Li Jing, Geri Tangdiongga, and Kwong Dim Lee, “Design and Analysis of 3D Stacked Optoelectronics on Optical Printed Circuit Boards ,” Photonics Packaging, Integration, and Interconnects VIII, edited by Alexei L. Glebov, Ray T. Chen Proc. of SPIE Vol. 6899, 689907, (2008) Copyright 2009 Society of Photo-Optical Instrumentation Engineers. One print or electronic copy may be made for personal use only. Systematic electronic or print reproduction and distribution, duplication of any material in this paper for a fee or for commercial purposes, or modification of the content of the paper are prohibited. http://dx.doi.org/10.1117/12.764032

Invited Paper

Design and Analysis of 3D Stacked Optoelectronics on Optical Printed Circuit Boards John H. Lau, Lim Ying Ying, Lim Teck Guan, Tang Gong Yue, Khong Chee Houe, Xiaowu Zhang, Pamidighantam V Ramana, Zhang Jing, Tan Chee Wei, Jayakrishnan Chandrappan, Joey Chai, Li Jing, Geri Tangdiongga, and Kwong Dim Lee Microsystems, Modules & Components Laboratory Institute of Microelectronics 11 Science Park Road Singapore Science Park II Singapore 117685 [email protected]

ABSTRACT In this study, a low-cost (with bare chips) and high (optical, electrical, and thermal) performance optoelectronic system with a data rate of 10Gbps is designed and analyzed. This system consists of a rigid printed circuit board (PCB) made of FR4 material with an optical polymer waveguide, a vertical cavity surface emitted laser (VCSEL), a driver chip, a 16:1 serializer, a photo-diode detector, a Trans-Impedance Amplifier (TIA), a 1:16 deserializer, and heat spreaders. The bare VCSEL, driver chip, and serializer chip are stacked with wire bonds and then solder jointed on one end of the optical polymer waveguide on the PCB via Cu posts. Similarly, the bare photo-diode detector, TIA chip, and deserializer chip are stacked with wire bonds and then solder jointed on the other end of the waveguide on the PCB via Cu posts. Because the devices in the 3D stacking system are made with different materials, the stresses due to the thermal expansion mismatch among various parts of the system are determined.

Keywords: 3D bare chips stacking, VCSEL, PIN, serializer, deserializer optical PCB, Cu post, and leadfree solder joint. (1) INTRODUCTION The major trend in the optoelectronic industry today is to make products more personal by making them smarter, lighter, smaller, thinner, shorter, and faster, while at the same time making them more friendly, functional, powerful, reliable, robust, innovative, creative, and less expensive. As the trend towards miniature and compact products continues, the introduction of cool products that are more user-friendly and contain a wider variety of functions will provide growth in the market. One of the key technologies that is helping to make these cool product design goals possible is 3D bare chips stacking on optical PCB. As integrated circuit (IC) technology advances, the speed and complexity of interconnects increase tremendously. As the number of devices per chip, the number of chips per board, the modulation speed, and the degrees of integration continue to increase, electrical interconnects are facing their fundamental bottlenecks, e.g., speed, date rate, and power dissipation. Optical interconnect is an attractive solution to the bandwidth limitation of the electrical transmission line for board level interconnections. However, the implementation of optical waveguide in a commercial PCB imposes severe restrictions on the materials and processes like low propagation loss, high thermal stability, cost effective fabrication, and etc. Currently, polymer based waveguide is the most popular choice for optical interconnect due to its low cost, suitability for mass production, high thermal stability and low optical loss [1-13].

Photonics Packaging, Integration, and Interconnects VIII, edited by Alexei L. Glebov, Ray T. Chen Proc. of SPIE Vol. 6899, 689907, (2008) · 0277-786X/08/$18 · doi: 10.1117/12.764032

Proc. of SPIE Vol. 6899 689907-1

A vertical-cavity surface-emitting laser, or VCSEL, is a specialized laser diode that is gaining popularity as a transceiver component in fiber optic communications. Unlike older edge emitting diodes that emit IR radiation in the plane of the semiconductor, the VCSEL produces a nearly circular beam of symmetrical laser light with small output beam divergence angle that is perpendicular to the plane of the semiconductor. These devices may be constructed on the surface of a fabricated wafer and tested for their optical and electrical properties on the wafer, and have the advantage of combining large 2D emitter arrays and active devices such as CMOS drivers with conventional technology. In addition, VCSELs offer ease of fiber coupling and of physical conformity with vertical laser cavity assemblies, see for example, Figure 10.47 of [14] and [15]. When the VCSEL is integrated with the optical PCB, however, it requires an out-of-plane 45º reflector to couple the optical signal to the polymer waveguide due to its surface emitting characteristic. This problem is also encountered by the surface illuminated photo detector. The optical polymer waveguide is usually designed in multimode and has a larger aperture, for reasons of low cost and compatibility with PCB process. An optical polymer waveguide is designed and analyzed for the present optoelectronic system. The speed, date rate, power, and size of optoelectronic devices generally scale with the wavelength of light used. The complexity of the present-day 2D photonic modules is limited by their substrate sizes and the difficulty in connecting large numbers of electrical connections. By progressing to multi-layer interconnects, the IC density can be increased greatly. Since fewer connections are required between bare chips, a higher performance will result. Some devices can actually be made smaller when integrated vertically rather than laterally. Vertical stacking also allows more chips per wafer. Complete optoelectronic integration of devices of different materials onto a single substrate (like the optical PCB) will achieve a dramatic cost and labor reduction as well. Novel combinations of materials/geometries may allow for devices far superior than their in-plane counterparts. Additional flexibility can be afforded in package design, interconnect routing, and package placement through 3D architectures. These factors have the potential to revolutionize the way 3D hybrid modules are produced and used. A low-cost 3D hybrid optoelectronic system with electrical and photonics ICs for board level applications, as shown in Figures 1 through 3, is designed and analyzed. The entire system consists of a rigid PCB made of FR4 material with an optical polymer waveguide, a VCSEL, a LD, a 16:1 serializer, a photo-diode detector, a TIA, a 1:16 deserializer, and heat spreaders. The bare VCSEL, LD, and serializer chips are stacked with wire bonds and then solder jointed on the optical PCB via copper posts. Similarly, the bare photo-diode detector, TIA, and deserializer chips are stacked with wire bonds and then solder jointed on the optical PCB via copper posts. The optical, electrical, thermal, and mechanical design philosophy and their metrics of the proposed 3D optoelectronic system will be given and the analysis results will be discussed.

(2) OPTICAL DESIGN AND ANALYSIS (2A) Optical Design Philosophy Beside the heat spreader, it can be seen from Figure 1 that the top most layer of the 3D system contains a parallel to serial electrical converter called serializer. The serializer converts the 16-bit 622 Mbps parallel signals into a 10 Gbps serial signal which is fed to the next layer (the VCSEL laser driver) in the 3D system. The signal inputs to the serializer and VCSEL laser driver (LD) are re-routed using wafer level Re-Distribution Layer (RDL) deposition techniques. The VCSEL itself is wirebonded on the LD, which converts the incoming signal into an electrical driving signal for the VCSEL. Again, from Figure 1, it can be seen that the receiver schematic is similar to that of the transmitter except that the internal ICs are the receiving elements. The 3D stacked transmitter and receiver can be used for board level optical interconnects as shown in Figure 1 with the transmitter output coupling to one end of the polymer waveguide, and the output on the other end of the polymer waveguide coupling to the receiver element. Direct coupling (without lens) is used for optical coupling design in this study. The optical signal is coupled from the VCSEL directly into the waveguide through its mirror on one end, and from the waveguide directly to the photodiode through the mirror on its other end. For direct coupling, due to the divergence nature of the optical signal, it is critical to maintain the optical propagating distance as short as possible in order to achieve the desire coupling efficiency.


TRANSMITTER

RECEIVER

Heat Spreader

Heat Spreader

Serializer Laser Driver

DeSerializer TIA

VCSEL

PIN Photo

Polymer Waveguide

PCB Not to scale

10 cm (Polymer Waveguide) TRANSMITTER

RECEIVER _10 Gbps PIN Photodiode (0.31x0.4x0.2mm) _10.7 Gbps Transimpedance Amplifier or TIA (2x2x0.3mm) _10 Gbps 1:16 DeSerializer or DeMultiplexer (4.5x4.5.0.8mm, 3.3V, 2.5W, 2.5-6.7W/cm2)

_10 Gbps VCSEL (0.31x0.4x0.2mm, 2.2V, 33mW, 16W/cm2) _10.7 Gbps VCSEL Driver (2x2x0.3mm, 3.3V, 0.35W, 6-35W/cm2) _10 Gbps 16:1 Serializer or Multiplexer (4.5x4.5.0.8mm, 3.3V, 2.5W, 2.5-6.7 W/cm2)

Fig. 1 3D Stacking of Optoelectronics on Optical Printed Circuit Board

Based on a given structure, this minimum distance is determined by the assembly design of the optoelectronic components. For wire bonding component, the minimum distance or height is determined by the bonding wire loop, which is typically approximately 200µm. On the other hand, for flip chip back illuminated optoelectronics components, the minimum height can be as closed as possible (~50µm for conventional solder bumps and ~25µm for microbumps) without damaging the active area of the optoelectronic components. (2B) Optical Simulation The design of the optical waveguide is as shown in Figure 1. The waveguide is embedded on the top surface of the FR4 PCB to give a complete planar design. The cross sectional design of the waveguide is as shown in Figure 2 and the refractive indices for the core and cladding are, respectively 1.5622 and 1.5544. At both end of the waveguide there is the out-of-plane reflector or mirror, which reflects the optical signal at 90 degrees.

4.5 mm 0.8mm

Multiplexer

2 mm

0.3 mm

Driver

0.7 mm

VCSEL

UU

Cu Post Polymer Waveguide

Solder

PCB

Not to scale

Core 50x70 µm²

z

x

Cladding 85x90 µm²

10 µm 25 µm

Polymer Waveguide: The refractive indices for the core and cladding are 1.5622 and 1.5544, respectively

Fig. 2 VCSEL, Laser Driver, Serializer (Mux), and Polymer Waveguide


Multiplexer (Mux)

Cu Post

Multiplexer (Mux) LD VCSEL Solder Joint

Solder

Fig. 3 VCSEL, Laser Driver (LD), Serializer (Mux), and Cu Post with Solder (2C) Results The optical simulation is done using the commercial software, ASAP, and Figure 4 shows the layout used in the simulation. The VCSEL used in the simulation has a beam divergence of 30º, and the photodiode has an active area of 40µm. The mirror on both sides of the waveguide is simulated with a loss of 0.6dB, and the waveguide loss is not simulated. Using the above parameters, the coupling losses are 8.5dB and 5dB, respectively for 250µm and 50µm heights (distances of the VCSEL and photodiode from the waveguide). Figure 5 shows the coupling losses for other heights. As expected, the greater the height, the larger the coupling loss.

VCSEL 30 C o

45oC

Optoelectronic height from waveguide

Photodiode

Waveguide

Simulation Conditions: VCSEL: half-divergence angle = 15o PD: active area = 40µm Assume no waveguide loss Assume mirror loss = 0.6dB Simulation Results:

• •

For VCSEL and PD height = 250µm (wire bonding components) Direct Coupling Loss = 8.5dB

Polymer Waveguide: The refractive indices for the core and cladding are, respectively, 1.5622 and 1.5544.

For VCSEL and PD height = 50µm (flip chip components) Direct Coupling Loss = 5.0dB

Fig. 4 Simulated Model Showing the Direct Coupling of the Optical Signal


9 8.5

Loss (dB)

8 7.5 7 6.5 6 5.5 5 4.5 4 0

50

100

150

200

250

300

Height (um) Fig. 5 Coupling Loss vs. the Height of optoelectronic Components (2D) Analysis and Summary The typical optical power from the VCSEL is 3dBm and the responsitivity for the GaAs photodiode at 850µm is 0.6A/W. Assuming the waveguide loss is 0.1dB/cm, hence the optical loss of a 10cm long waveguide will be 1dB. Also assuming that the minimum input optical power required for a 10Gbps receiver is -13dBm, and then the maximum optical acceptable coupling loss is approximately 15dB. Therefore, the direct coupling schemes are feasible for the 10Gbps OECB design.

(3) ELECTRICAL DESIGNS AND ANALYSES (3A) Design Philosophy and Metrics The electrical loss is a function of the electrical length of the circuit. In high frequency applications, electrical loss is one of the critical issues affecting system performance. One of the most effective solutions is to minimize all the high-frequency electrical interconnections. In addition, minimizing the electrical length helps to reduce the cross talk or interference [16]. For digital circuits, the bandwidth required is a function of the pulse rise time, and the typical rise time is about 28ps for 10Gbps. This corresponds to (a conservative of a 3dB bandwidth of) about 15GHz. Hence, the required 3dB bandwidths for the insertion loss and the 10dB bandwidth for the return loss designed here are set to 15GHz. For high-frequency VCSEL and photodiode, their impedances are usually 50Ω. Similarly, the Laser Driver (LD) IC and the Transimpedance Amplifier (TIA) IC for the respective optoelectronics are also 50Ω. In addition, the typical heights for both ICs are usually about 300µm. Therefore, their electrical interconnections are similar. Hence, only the electrical interconnections between the VCSEL and its driver IC are simulated and analyzed here. In addition, the electrical characteristics between the LD and its Serializer and the TIA and its De-serializer are similar, and having a standard input and output impedances of 50Ω. As a result, only the electrical interconnections between the LD IC and its Serializer are simulated and analyzed here as well. In order to maximize the electrical performance, the 10Gbps electrical interconnection lengths are minimized as well. Therefore, both the optoelectronic components are designed in such a way that they are attached directly above the I/Os of their respective ICs. (This leads to the offsetting of the optoelectronic from the center of their ICs). Similarly, for the redistribution layer of the Serializer and the De-Serializer, their 10Gps electrical interconnections will be designed in such a way that the I/Os of their respective ICs are directly above them. Consequently, it is assumed that there is no electrical transmission line required and very short vias are required to bring the I/Os to the top layer for wire bonding to


their respective IC. It is expected that length of the vias will be electrically very much smaller than the signal wavelength; therefore, the vias are not simulated here. For the 16 inputs of the Serializer and the 16 output to the De-Serializer, their bit rate is one of 16 times of the 10Gbps. Their typical rise time is about 100ps, which correspond to a require bandwidth of about 3.5GHz. Hence, the copper posts, which are used for their electrical interconnection and the transmission line in the FR4 PCB are designed to meet this bandwidth. The crosstalk between 2 pairs of differential copper posts are also investigated and the target crosstalk is 3.5GHz and the targeted crosstalk < -40dB at 3.5GHz. From Fig. 11, a differential mode insertion loss of 0.15 dB is obtained at 3.5GHz with a corresponding differential return loss < 25dB. In addition, the differential microstrips achieved more than 3.5GHz bandwidth over 10 mm. From Fig. 11, the crosstalk < -70dB across 3.5GHz, which provides for good suppression of undesired noise signals. ASIC! Mioroprooeor

Simulation Parameters: FR-4 -Dielectric constant: 4.4 -Loss Tangent: 0.02

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0

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(8p) aaoi

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Differential inaertionbaa (dB)

w=s=400µm Zdiff=100Ω

0

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2

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4

5

Frequency (GHz)

Fig. 11 Losses and crosstalk performance in differential line structure (3C) Summary The above simulated results show that the electrical parameters meet the requirement of the 3dB insertion loss bandwidth and the 10dB return loss bandwidth to operate at 10Gbps. To improve the performance of the electrical interconnections or increase the operating bit rate, the resistances of the bonding wires would need to be reduced further.

(4) THERMAL DESIGNS AND ANALYSES (4A) Design Philosophy and Metrics The choice of a photonic package configuration requires recognition not only of critical cost issues and optical and electrical performances but also those of thermal performance and mechanical reliability. Since low-cost bare (VCSEL, PIN, laser driver, TIA, Serializer, and Deserializer) chips are used to stack up the optoelectronic structure as shown in Figure 1, thermal management is a critical issue. This is compounded with the high power dissipation of the 10 Gbps laser (2.2V, 33mW, and 16W/cm2), the 10.7 Gbps laser driver and TIA chips (3.3V, 0.35W, and 6-35W/cm2), and the 10Gbps 1:16 sweializer and the 10 Gpbs 16:1 deserializer (3.3V, 2.5W, and 2.5-6.7 W/cm2), thus how to take the heat out from these chips before they burn themselves is a challenge problem. In particular, a stable thermal environment is required for the VCSEL. Excursions from the desired operating temperature may alter the wavelength of the emitted light, consequently degrading the VCSEL’s performance. In this study, the target temperature at the laser of the 10Gpbs VCSEL is 85oC. (4B) Heat-Spreader Design and Analysis The full 3D optoelectronic structure shown in Figure 1 is modeled and analyzed by FLOTHERM, which is a computational Fluid Dynamic (CFD) thermal modeling analysis tool to simulate the air flow and heat transfer in optoelectronic systems.


Four different heat-spreader sizes are considered, 0x0x0mm (no heat spreader), 15x15x0.8mm, 30x30x0.8mm, and 50x50x0.8mm. (4B-1) Boundary Conditions and Material Properties The 3D package size is about: X = 175mm, Y = 125mm, and Z = 3.15mm. The gravity direction is set in the negative Z direction. The overall dimensions of the volume or enclosure (domain for computation) are: X = 200mm, Y = 150mm, and Z = 60mm. Since the gravity is set in the negative Z direction, the air flow is mainly in the Z direction, and hence more space for free convection is given in the upper and lower parts of the package. The boundary conditions of all exposed surfaces are free convection with the ambient, i.e. there is not fan to help to cool the system. The boundary conditions of inner boundaries between the components are by conduction. The ambient dry air temperature is set to 25oC, the pressure is set to 1atm, and the properties of the air at the specified condition (i.e. 25oC and 1atm) are set as following: density = 1.185 kg/m3, viscosity = 18.35x10-6 kg/(m.s), specific heat = 1.005 kJ/(kg.C), and thermal conductivity = 0.0263 W/(m.C). All other material properties, power, and dimensions are shown in Table 2 [17, 18]. Component

PCB

HS

MUX

LD

VCSEL

DeMUX

TIA & LA

PD

Material

FR4

Copper

Si

Si

GaAs

Si

Si

GaAs

Thermal Conductivity (W/m/C)

// 0.8 ⊥ 0.3

390

150

150

68

150

150

68

Dimension 175x125 4.5x4.5 2.0x2 .31x.4 4.5x4.5 2.0x2. .31x.4 Variable detail (mm) x1.6 x0.8 x.3 x.2 x.8 x.3 x.2 Power (W)

N.A.

N.A.

2.5

0.35

0.033

2.5

0.35

0.033

Table 2 Material Properties, Power, and Dimension for Thermal Modelling (4B-2) Results and Analyses Figure 12 shows the calculated heat transfer coefficient at the faces of all the key components (e.g., PCB, laser of the VCSEL, serializer, driver, etc.) of the 3D system without heat spreader. It can be seen and expected that the maximum heat transfer coefficient occurs at the laser of the VCSEL. Figures 13 through 15 show the calculated heat transfer coefficient at the faces of all the key components of the 3D stacked optoelectronic components with 15x15x0.8mm, 30x30x0.8mm, and 50x50x0.8mm heat spreaders, respectively. It can be seen that for all the cases, the maximum heat transfer coefficient occurs at the laser of the VCSEL and it is decreasing with the increasing of the heat spreader sizes as shown in Figure 16. This means that the heat spreader helps to dissipate the heat from the system and the larger the heat spreaders the less heat coming out from the laser of the VCSEL.

Proc. of SPIE Vol. 6899 689907-10

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Fig. 13 Heat Transfer Coefficient

Proc. of SPIE Vol. 6899 689907-11

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Proc. of SPIE Vol. 6899 689907-12

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Heat transfer coefficient (W/m2/oC)

100 90

VCSEL Surface with Laser

80 70 60 50 40 30 20 10 0 No HS

15x15x0.8

30x30x0.8

50x50x0.8

Heat Spreader Size (mm) FACE:

Z (-)

X (+)

X (-)

Y (+)

Y (-)

Fig. 16 Heat Transfer Coefficient at the VCSEL

Figure 17 shows the temperature distributions in the 3D system with a 50x50x0.8mm heat spreader. It can be seen and expect that the maximum temperature occurs at the laser of the VCSEL and is equal to 84.7oC which meets the target (85oC). Figure 18 shows the effects of heat-spreader size on the maximum temperature of the 3D system. It can be seen and expected that the larger the heat spreaders the less the maximum temperature at the laser of the VCSEL.

Cross-Section View

3D View Heat Spreader Mux

LD VCSEL

Fig. 17 Temperature Distribution of the 3D Stacked Optoelectronics

Proc. of SPIE Vol. 6899 689907-13

Temperature (oC)

30

285

25 192

20 15

123

10 85

5 0 No

15x15x0.

30x30x0.

50x50x0.

Heat Spreader Size Fig. 18 Effects of Heat-Spreader Size on the Max. Temperature at VCSEL (4C) Summary Based on the design and analysis of a few heat spreaders for the 3D optoelectronic system, it is found that the 50x50x0.8mm heat spreader (without fan) can help to lower the maximum temperature at the laser of the VCSEL to 85oC.

(5) MECHANCIAL DESIGNS AND ANALYSES (5A) Design Philosophy and Metric As mentioned earlier, the choice of a photonic package configuration requires recognition not only of critical cost issues and optical, electrical, and thermal performances but also those of mechanical reliability. Since low-cost bare chips with different material properties (e.g., thermal expansion of coefficient) are used to stack up the optoelectronic structure as shown in Figure 1, the mechanical stresses and strains (i.e., creep strain energy density per temperature cycle) in the solder joints and the mechanical stresses at the laser of the VCSEL due to the global and local thermal expansion mismatches under the most common environmental stress condition (i.e., temperature cycling with -40 to +125oC, one hour per cycle) are critical issues. One of the functions of Cu post is to increase the stand-off height of the 3D stacked system and thus to relax the stress and strain acting at the solder joints. However, based on the optical performance of the laser of the VCSEL without lens, the stand-off height should be as small as possible. Thus, it is necessary to design a height of the Cu post + solder joint such that the structure has enough compliance (for the solder-joint reliability) and still within the optical performance target. In this study, the target for the creep strain energy density per temperature cycle is 0.3MPa and the stress at the laser is 30MPa. (5B) Design and Analysis The Cu post and the solder joint shown in Figures 1 through 3 are designed with the dimensions: 0.5mmx0.2mmΦ and 0.2mmΦ, respectively. Figure 19 shows the 3-D finite element model that captures the construction along a diagonal strip from the 72-pin serializer lead-free assembly’s geometric center to a corner. Because of the mid-plane symmetry, the mesh actually models a one-half strip (with one-half of a solder joint) using the appropriate in-plane constraints placed on one symmetry plane. Coupled in-plane translations are applied to the other symmetry plane to produce a state of generalized plane strain. Using exclusively hexahedral solid elements, the model can capture the precise shape of the packages’ solder joints and potential DNP (distant to neutral point) effects while retaining significant computational efficiency over full octant models. ANSYS is the code selected for the modeling and analyses.

Proc. of SPIE Vol. 6899 689907-14

Serializer or DeSerializer

LD or PIA Cu Post VCSEL or PIN

Solder Joint Optical PCB

Temperature (oC)

140 120 100 80 60 40 20 0 -20

2000

-40 -60

4000 6000 8000 10000 1200014000 16000 18000 20000

Time (sec)

Fig. 19 Mechanical Analysis of the 3D Stacked Optoelectronics on PCB

(5B-1) Material Properties Materials VCSEL Serializer Laser Driver FR-4 PCB Cu RDL Die Attach Film

CTE (ppm/°C) 5.6 2.7 2.7 15 17 17 40

E (GPa)

Poisson Ratio

85 131 131 21 110 110 0.69

0.30 0.28 0.28 0.18 0.34 0.34 0.3

Table 3 Material Properties for Environmental Stress Modelling The material properties of the 3D assembly are shown in Table 3. All of the material properties are assumed to be constant except for those of the solders. Useful creep constitutive equations for various SnAgCu alloys have been given by Schubert, Dudek, Auerswald, Gollhardt, Michel, and Reichl [19, 20], which are based on 108 creep data points from the literature and IZM’s own measurements. At the same time, based on 32 creep data points measured by Sandia, Vianco, Rajent, Kilgo, Lau, and Dauksher presented another creep constitutive equation [21, 22, 23]. By averaging the data of [20, 21, 22], Lau and

Proc. of SPIE Vol. 6899 689907-15

Dauksher obtained a new creep constitutive equation [24], for a range of SnAgCu lead-free solder alloys. The Young’s modulus, coefficient of thermal expansion (CTE), and normal creep strain rate given in [24] are: E = −0.07T (o C ) + 49

[

]

CTE = 0.017T ( o C ) + 21.3 x10 −6 / o C

dε = 5 x105 exp − 48.28(kJ / mol ) / RT (o K ) sinh 5 (0.01σ ) dt

[

]

In these equations, E is the Young’s modulus (GPa), R is the gas constant, ε is the normal creep strain, and σ is the normal stress (MPa). The last equation can be rewritten suitable for the input of ANSYS and is shown below:

⎛ −C ⎞ dε C = C1 [sinh(C 2σ )] 3 exp⎜⎜ o 4 ⎟⎟ dt ⎝T( K) ⎠ where the constants are [24] C1 = 500000 1/sec, C2 = 0.01 1/MPa, C3 = 5, and C4 = 5802 oK. (5B-2) Temperature Boundary Conditions The temperature loading imposed to the lead-free 3D assembly is shown in Figure 19. It can be seen that the temperature ranges are -40oC to 125oC and the ramp-up, ramp-down, dwell-at-hot, and dwell-at-cold are each 15 minutes. (5B-3) Maximum Stress/Strain Location Figure 20 shows a typical von Mises stress and equivalent creep strain contour of the most likely to fail (corner) lead-free solder joint in the 3D assembly at the end of the 5th cycle. It can be seen that the location for the maximum Mises stress and equivalent creep strain is near the corner interface between the solder and the pad of the PCB of the lead-free solder joint.

AN

AN

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Maximum von Mises Stress = 0.994x107Pa

Maximum Equivalent Creep Strain = 0.0121

Fig. 20 Max. Miss Stress and Equivalent Creep Strain at the Corner Solder Joint after the 5th temperature cycle

Proc. of SPIE Vol. 6899 689907-16

(5B-4) Creep Hysteresis Loops It is important to study the creep responses for multiple cycles by observing when the hysteresis loops become stabilized. Figure 21 shows a typical shear stress and creep shear strain hysteresis loops for multiple cycles at the corner of the most likely to fail solder joint in the lead-free 3D assembly subject to the -40oC to 125oC environmental temperature cycles. It can be seen that the creep shear strain vs. shear stress loop is quite stabilized after the fourth cycle. 10

Shear Stress (MPa)

5 0 -5 -10 -15 -20 -0.004

-0.002

0.000

0.002

0.004

0.006

0.008

Creep Shear

Creep strain energy density (MPa)

Fig. 21 Max. Hysteresis Loops at the Corner Solder Joint 0.6 0.5

∆W = 0.123MPa

0.4 0.3 0.2 0.1 0 0

3600

7200

10800

14400

18000

Time (sec) Fig. 22 Max. Creep Strain Energy Density History at the Corner Solder

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(5B-5) Maximum Creep Strain Energy Density Time-History Figure 22 shows the von Mises creep strain energy density time-history (for 5 complete cycles) at the corner solder joint of the 3D assembly. The creep strain energy density per temperature cycle (∆W) can be determined from either the 4th or the 5th cycle and is equals to 0.123MPa, which is less than the target (0.3MPa). (5B-6) Maximum Stress in VCSEL The maximum stress (Figure 23) in the VCSEL due to the environmental stress condition (-40oC to 125oC) occurs at the laser in the bottom surface of the VCSEL and is equal to 28.6MPa. This value is less than the maximum allowable stress (30MPa) of the target.

Max. Stress Location The Max. Stress (28.6MP) occurs at the bottom-center (laser) of the VCSEL Fig. 23 Max. Mises Stress in the VCSEL

Max. Mises Stress = 28.6MP at the end of the 5th temperature cycle

(5C) Summary Based on time and temperature dependent analyses, it has been shown that the present design of the solder joint and Cu post in the 3D optoelectronic system can withstand the most common environmental stress condition.

(6) CONCLUSIONS A low-cost (with bare chips) and high (optical, electrical, and thermal) performance optoelectronic 3D system with a data rate of 10Gbps has been designed and analyzed. This system consists of a rigid PCB with an optical polymer waveguide, a bare VCSEL, a bare LD, a bare serializer, a bare PIN, a bare TIA, a bare deserializer, and heat spreaders. Mechanical stresses due to the thermal expansion mismatch among various parts of the system have also been determined. Some important results are summarized in the following. (1) Optical analyses showed that the present design of the cross-section of the polymer waveguide meets the optical acceptable coupling loss (15dB). Therefore, the direct coupling schemes (without lens) are feasible for the 10Gbps optical board level interconnect. (2) Electrical analyses showed that: (a) a 25.4µm-diameter bonding wire connecting the LD to the VCSEL is adequate for high frequency (15GHz) applications; (b) 4 parallel 25.4µm-diameter bonding wires are needed to connect the LD and the serializer; (c) the effect of the differential copper post on the overall loss from the serializer to the PCB is less than the target (0.5dB at 3.5GHZ); (d) the effect of crosstalk between 2 pairs of differential copper post on the overall loss from the serializer to the PCB is less than the target (40dB at 3.5GHz); and (e) the loss of a pair of 100Ω differential lines over 10mm is less than the acceptable loss (70dB at 3.5GHz).

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(3) Thermal analyses showed that the 50x50x0.8mm heat spreader (without fans) can lower the maximum temperature at the laser of the VCSEL to below 85oC. (4) Mechanical stress analyses showed that: (a) the maximum creep strain energy density per temperature cycle in the corner lead-free solder joint is less than that of the allowable one (0.3MPa), and (b) the maximum Mises stress at the laser of the VCSEL is less than the target (30MPa).

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(18) Lau, J. H., and Pao, Y. H., Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies, McGraw-Hill, New York, NY, 1997. (19) Lau, J. H., C. P. Wong, N. C. Lee, and R. Lee, Electronics Manufacturing with Lead-Free, Halogen-Free & Conductive-Adhesive Materials, McGraw-Hill, New York, NY, 2003. (20) Schubert, A., R. Dudek, E. Auerswald, A. Gollhardt, B. Michel, and H. Reichl, “Fatigue Life Models for SnAgCu and SnPb Solder Joints Evaluated by Experiments and Simulation,” IEEE Electronic Components and Technology Conference Proceedings, New Orleans, Louisiana, June 2003, pp. 603-610. (21) Lau, J., W. Dauksher, and P. Vianco, “Acceleration Models, Constitutive Equations and Reliability of Lead-Free Solders and Joints,” IEEE Electronic Components and Technology Conference Proceedings, New Orleans, Louisiana, June 2003, pp. 229-236. (22) Vianco, P., J. Rejent, and A. Kilgo, “Creep Behavior of the Ternary 95.5Sn-3.9Ag-0.6Cu Solder: Part I – As-Cast Condition”, Journal of Electronics Material, Vol. 33, 2004, pp. 1389 - 1400. (23) Vianco, P., J. Rejent, and A. Kilgo, “Creep Behavior of the Ternary 95.5Sn-3.9Ag-0.6Cu Solder: Part II – Aged Condition,” Journal of Electronic Materials, Vol. 33, 2004, pp. 1473 - 1484. (24) Lau, J. H., and W. Dauksher, “Creep of Sn-(3.5-3.9)wt%Ag-(0.5-0.8)wt%Cu Lead-Free Solder”, in Micromaterials and Nanomaterials, Edited by B. Michel, Fraunhofer Institute, IZM, Berlin, 2004, pp. 54-62.

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