PERFORMANCE COMPARISON OF PHASE LOOKED LOOP ALGORITHMS APPLIED TO MICRO-INVERTERS FOR DISTRIBUTED PHOTOVOLTAIC GENERATION G. Scelba*, M. Cacciato*, G. Scarcella*, N. Bartoli*, R. Attanasio†, G. Scuderi† *
UNIVERSITY OF CATANIA Viale Andrea Doria n°6, 95125 Catania, Italy
[email protected]
†
ST MICROELECTRONICS Statale Primosole n°50, 95100 Catania, Italy
[email protected]
Keywords Renewable energy systems, Photovoltaic, Micro-inverter, Fault ride-through.
Abstract The paper deals with the experimental comparison of different phase locked loop (PLL) algorithms for single phase, grid tied, photovoltaic generation systems; in particular, this work analyzes the effects of abnormal grid conditions on the output current and power control loops of a 250W micro-inverter unit, highlighting pros and cons of each PLL algorithm. The effectiveness of such algorithms has been evaluated by means of experimental tests analyzing the micro inverter operations when the grid voltage is affected by sags, dips, frequency variations and harmonic distortion. Harmonics rejection and dynamic response of the control algorithm in these operating conditions has been highlighted. In addition the computational burden required by each algorithm has been evaluated.
Introduction Even though conventional Photovoltaic (PV) systems are widely adopted, they present some drawbacks related to partial shadowing, mismatching and failure modes which may limit the annual energy production of the plant. The new trend is to overcome these problems with new conversion solutions based on the so called distributed approach. The distributed approach is the result of the understanding of how important is to realize panel dedicated Maximum Power Point Tracking (MPPT) and can be implemented by means of Microinverters (MICs) which, from a market trend point of view, seems a well accepted solution in several countries. Generally speaking, MICs are single phase grid connected DC/AC converters, whose basic requirements are the extraction of maximum energy available from the PV panel and the synchronization to utility network even when the grid voltage is distorted. Ideally, the control system should provide fast and accurate synchronization capability while ensuring a high immunity to voltage disturbances such as harmonics, sags, dips and any other types of distortions. One of the most important parts of a grid synchronization algorithm is the Phase Looked Loop (PLL). The main tasks of a PLL are the precise estimation of the grid voltage amplitude, phase and frequency. Differently than three phase PV generation systems, in single phase implementations, the majority of the PLL algorithms require the generation of a 90 degrees phase shifted voltage signal [1-12]. Several PLL implementations have been proposed in the past to generate the 90 degrees phase shifted signal and ensure closed loop stability and good dynamic response during normal operation. Another important part of the grid synchronization algorithm is the current control loop. New regulations recently approved in many countries worldwide require both the control of active and reactive power. Therefore, the current control scheme requires the generation of a 90 degrees phase shifted signal (iα) with respect to the measured current (iβ) which is used to perform a reference frame transformation and the calculation of two decoupled current components, id and iq, respectively proportional to active and reactive power. In this case, the signal iα can be obtained by applying the same algorithms used in
PLLs to estimate the phase, amplitude and frequency of the grid voltage signal. Depending on the adopted PLL algorithm, the control provides a different dynamic behavior. The analysis presented in this work gives particular relevance to the entire generation system, not only to the grid synchronization unit, as the performance of a PLL has an important impact on the stability and behavior of both MPPT and power control algorithms. In addition, from a computational point of view, the implementation of a very sophisticated PLL algorithm can be of difficult practice in real applications, where microcontroller resources are limited. As a consequence, the required microcontroller resources and performance must be accurately evaluated for each PLL algorithm in order to allocate them in a suitable complexity level scale. The MIC configuration and the control structure used in this analysis are shown in Fig.1. Basically, the generation unit consists of two power conversion stages: a DC/DC converter performing the MPPT algorithm, and a second power conversion stage used to connect the MIC to the utility grid. Fig. 1 also displays the control block diagram adopted for this application. The decoupled active and reactive power controls are achieved by performing a suitable reference frame transformation of the grid voltage and inverter current, from a stationary reference frame to an orthogonal, rotating reference frame (q,d). The MPPT is implemented by measuring the output power of the PV module and applying a perturb&observe control strategy [3].
Fig. 1: Block Diagram Control Solution. As mentioned above, the more susceptible part of the control system is identified by the two red highlighted blocks of Fig.1. The analysis and comparison of the control system performance obtained under abnormal grid conditions using three different PLL solutions is of main concern in this paper. The performance assessment is carried out by evaluating for each of the three PLLs: 1) the effects of voltage distortions on current THD%; 2) the dynamic response during transients; 3) the stability of each PLL and the computational effort required for its implementation.
Phase locked loop algorithms A phase locked loop is an algorithm successfully used to detect the phase of an input signal. Depending on the signal characteristics, the structure of a PLL can be more or less sophisticated in terms of computational burden, but essentially it is characterized by three elements: a phase detector, a loop filter and a Voltage Controlled Oscillator (VCO). The loop filter is generally a standard proportional-integral regulator, while the VCO stage minimizes the output error of the phase detector. Three different PLL algorithms have been evaluated in this analysis: the Transport Delay Time (TDT) [1], the Inverse Park Transformation (IPT) [1] and the Second Order Generalized Integrator (SOGI)
[2]. The block diagrams of these three PLL structures are shown in Fig. 3. The main difference among them is strictly related to the generation of the voltage signal Vα, that has to be 90 degrees phase shifted with respect to the measured grid voltage Vβ. All the analyzed PLLs perform the grid voltage phase detection θe by applying a reference frame transformation (αβ/qd) synchronous to the grid angle θe to the estimated Vα and the measured Vβ; this mathematical operation provides two new constant voltage components Vd and Vq, with the latter forced steadily to zero. In the TDT PLL, the signal Vα is obtained by shifting the measured Vβ samples of a constant quantity (Fig. 3a).
Fig. 2: Transport delay time procedure. The IPT PLL generates the signal Vα by means of an additional closed loop, consisting of a low pass filter applied to the qd voltage components, followed by an inverse reference frame transformation (Fig. 3b). The signal Vα, achieved by the latter analytical operation, is sent together with Vβ to the reference frame transformation (αβ/qd). ωff Kp
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Fig. 3: PLL structures analyzed in this study.
offset rejection implementation.
Differently from the previous algorithms, a second order generalized integrator is used in the algorithm of Fig. 3c [2], where parameter k is the gain affecting the bandwidth of the PLL while ω is the resonance frequency of the SOGI. The input signal is filtered obtaining two orthogonal signals Vβ and Vα. An improved implementation can be achieved allowing the rejection of the DC component in both voltage components.
Experimental comparison of grid synchronization methods Experimental tests have been performed on a 250W MIC fed by a PV panel whose maximum power point voltage is in the 20V-40V range. The DC-DC stage of the proposed MIC, designed to boost the PV panel voltage to about 400V, is an isolated interleaved boost, as shown in Fig. 4.
Fig. 4b
Fig. 4: Conversion topology and prototype of the MIC. The DC/AC converter is a Full Bridge with one leg switching with HF sinusoidal PWM and the other leg modulated at grid frequency. Such a modulating strategy optimizes the efficiency of the MIC at low loads since a sensible reduction in switching losses is achieved. MOS3 and MOS4 are connected in one leg and switch at 17.4 kHz. Two Schottky diodes are connected to the drain of these two MosFETS in order to inhibit the internal body diode. Silicon Carbide (SiC) diodes are therefore connected in anti-parallel for current freewheeling, avoiding problems due to reverse recovery at MosFET turn on. An LCL filter is connected to the mid-points of inverter legs and is used to interface the system to the grid. On the DC side a bank of four electrolytic capacitors is used to store and deliver energy during normal operation. The experimental setup shown in Fig. 5 has been used to evaluate the performance of the control algorithm with each of the three above mentioned PLL algorithms with distorted input voltage signal. The PV module has been emulated by including the V-I characteristic of the panel in a DC power supply, while the AC grid has been emulated by applying a controllable AC power source; such an instrument has allowed the implementation of the distorted AC voltage conditions mentioned above.
A high precision power analyzer has been used to measure the total harmonic distortion of the current flowing between the MIC and the AC source; the same instrument has also been used to measure the current and voltage harmonics amplitude. Experimental tests have been performed assuming a grid voltage of 230Vrms and a grid frequency equal to 50Hz in normal operating conditions. As the goal of this study is to highlight the influence of the PLL structure in steady state and during transient operations of the generation unit, multiple tests were needed with the system implementing the MPPT algorithm at rated conditions (250W). In particular, Fig. 6 shows the inverter current iμ, the voltage applied to the filter terminals vμ, the estimated angle θe and the estimated voltage vα, measured at rated conditions, when one of the above mentioned PLL structures was used. The increment of Total Harmonic Distortion of the current (THDI) due to the reduction of current amplitude is displayed in the same figure.
Scope
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Fig. 5: Experimental setup.
Fig. 6: Electrical quantities waveforms and iμ THD under normal operating condition (230Vrms, 50Hz).
Such a parameter has been calculated as the ratio between the THD measured at a certain delivered power and that measured at rated conditions. In the latter situation, the improvement in terms of harmonic content achievable by using IPT and SOGI with respect to TDT is very significant, while all the algorithms present a high THDI when the MIC is operating at lower power levels. The dynamic behavior of the generation unit is shown in Fig. 7, where frequency and voltage amplitude steps are applied to the grid voltage. The figure depicts the same quantities analyzed in the previous test, with the red trace indicating the time instant of the frequency variation. The perturbations have been applied at the same instant time corresponding to the maximum value of the grid voltage amplitude. By looking at the results, it can be noted that TDT shows a higher susceptibility to deviations from the normal operating conditions, producing more severe transients. Such a behavior can be explained by considering that both the IPT and SOGI PLLs include filtering processes in their structures to help mitigating sudden voltage and/or frequency variations. Fig.8 shows the current, voltage and estimated phase grid voltage θe waveforms in steady state, when an additional third harmonic with amplitude equal to 5% of the fundamental one is superimposed to the grid voltage. The generation unit is operating at 250W. It is worth to notice the presence of a considerable distortion in the delivered current iμ, which is mitigated by the PLL configuration. In fact, as indicated in the same figure, this voltage disturbance produces a considerable increment of the current THD in TDT, while the other two PLL implementations considerably reduce this THD variation because of the filtering processes included in both PLL structures, which mitigates the presence of signals whose frequency is higher than the nominal grid frequency. i
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Fig. 7: Electrical quantities waveforms under a frequency step and voltage amplitude step (230Vrms, 50Hz).
Fig. 8: Electrical quantities waveforms and iμ harmonic spectrum at steady state, under the presence of a third harmonic in the grid voltage.
Fig. 9: Electrical quantities waveforms and iμ harmonic spectrum at steady state, in presence of a third harmonic in the grid voltage.
Offset rejection is the key issue that highlights the main difference among the considered PLL algorithms; in particular, Fig. 9 shows the experimental results obtained by injecting a DC component equal to 1% of the measured grid voltage. This disturbance considerably affects the power production from the MIC, yielding to a considerable distortion of the inverter current in both TDT and IPT, as such algorithms are not designed to mitigate this drawback. In this operating condition, the SOGI PLL with offset rejection provides the best results as shown in Fig. 9. Finally, Fig. 10 highlights the effects of grid voltage dips. In particular, it is possible to notice severe current pulses occurring during the voltage dips which could compromise the functionality of the MIC. All PLLs show the same behavior in such an abnormal operating condition. Another important issue to be taken into consideration in the choice of a PLL structure is the computational burden, playing an essential role in applications where computational resources of the microcontroller unit can be limited. Tab. I shows the time required for the execution of each of the three PLL solutions; it is interesting to notice that the more time consuming solution is the SOGI, whose execution is 10% longer compared to the IPT. From a computational burden point of view, the most suitable PLL structure is certainly the TDT.
Fig. 10: MIC operating with voltage dips.
Tab. I: Execution time of major routines. PLL MPPT and Power Control Main Routine
TDT
IPT
SOGI with offset rejection
7.5 μs 25 μs 56.8μs
10.5 μs 29.5 μs 56.8μs
11.5 μs 30.5 μs 56.8μs
Conclusions and future works The main contribution of this paper is the implementation and experimental evaluation of different PLL algorithms used in micro-inverter applications for distributed photovoltaic generation. The analysis shows the improvement achievable in the power control loop by adopting a more sophisticated PLL structure. In fact, the tests have pointed out that TDT is the worst solution among the ones taken into consideration as the inherent delays, used to calculate the ninety degrees phase shifted grid voltage, negatively affects the dynamic response of the control system. More complex implementations as SOGI and IPT make the system more robust when the grid voltage is highly disturbed. Their behavior is very similar in most of the cases; the only advantage of using a SOGI PLL with respect to the IPT is given by the offset rejection. Future activities will be focused on the analysis of the algorithms exploited to generate the ninety degrees phase shifted current signal with respect to the measured current. Experimental tests will support the analysis.
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