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EECE 321: Computer Organization Mohammad M. Mansour Dept. of Electrical and Compute Engineering American University of Beirut Lecture 1: Introduction

Administrative 

Instructor – – – –

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Dr. Mohammad M. Mansour, Associate Professor of ECE Office: 501 Bechtel Extension: 3597 Email: [email protected]

Send emails with Subject: EECE321 – Will try to reply back during office hours

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Course Webpage: – http://webfea.fea.aub.edu.lb/mmansour/eece321/index.htm

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Teaching Assistant (TA): – Nadida Raad ([email protected])

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Office hours to be announced Lecture hours: – MWF: 10:00 – 11:00 am in room 541 Bechtel

Prof. M. Mansour

EECE 321: Computer Organization

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Course Policy 

Grading (tentative) – – – – –

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Homework 2 Midterms Project Final Exam Participation/attendance

(10%) (40%) --- [Include Homework questions] (15%) (30%) --- [Includes Homework questions] (5% up to instructor)

Final course grade will not be assigned based on a curve Attendance taken randomly during the semester at the start of the lecture – Late arrivals are considered as absences (no excuses allowed)

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Assignments: – – – – –

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Reading assignments: Assigned every lecture. ~20% course questions on exams. Weekly homework: Direct HW questions will be part of the midterms and final exam Deadlines are sharp, late submissions will not be accepted. Cheating: All parties involved will automatically get a grade of zero on the 10% homework grade. Final homework grade = (Grade on HW assignments) x (HW grade on exams / 100)

Projects: Groups of three students – – – – –

Must assemble teams early Project will be done in several phases Direct project questions will be part of the midterms and final exam Cheating: All parties involved will automatically get a grade of zero on the 15% project grade. Final project grade = (Grade on course project) x (project grade on exams / 100)

Prof. M. Mansour


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Course Policy 

Lecture slides will be posted on line – Must come to class prepared to take notes, so bring pens & notebooks – Lectures begin on the hour. Students arriving late may be refused entry to the classroom.

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Exams are closed book and comprehensive. Students are responsible for all material covered in class, as well as other material posted on the web. – No makeup exams will be given for missing any midterm (70% of your grade will be based on whatever exams were taken) – If you miss the final exam, your course grade will be Incomplete (I) • Do not make any travel arrangements during the final exams week of the semester • Must sit for final exam on campus

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Reviewing your final course grade at the end of the semester must be accompanied with a signed letter from the Associate Dean – Any student who sends emails objecting for his/her course grade or asking for more grades will be automatically reported to the FEA Student Affairs Committee, which may result in a Dean’s Warning in addition to failing the course.

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Don’t even think about cheating !!! – Zero tolerance policy; Reported to Student Affairs Committee for appropriate action.

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This course policy must be read and understood clearly by all students before registering in the course

Prof. M. Mansour


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Course Syllabus 

Main Textbook (P&H) – David Patterson and John Hennessy, “Computer Organization & Design: The Hardware/Software Interface,” 4th edition, Morgan Kaufmann Pub., Inc., 2009.

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Prerequisites – EECE 230: C/C++ Programming – EECE 320: Digital Logic Design – Assumption is that you know • • • • • • •

C/C++ programming: loops, functions, etc. 2’s complement and unsigned numbers Basic digital logic gates, truth tables Basic combination gates: Adders, shifters, multipliers Basic sequential gates: Flip flops, registers Finite state machines VHDL

– You are responsible for reviewing all the above material

Prof. M. Mansour

EECE 421: Computer Architecture

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Outline 

Topics         

Computer Abstractions Machine Instructions, Assembly Language and Programs MIPS/x86 Instruction Set Architectures: RISC vs. CISC Microprocessor Datapath Design Basics Instruction Sequencing and Datapath Control Pipelining Memory Systems Input/Output Organization Introduction to multi-cores/multi-processors

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Detailed outline found in course syllabus.

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Material is mainly based on Patterson and Hennessy (P&H), 4th edition

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Project: You will apply these ideas to design and implement a substantial course project.

Prof. M. Mansour


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Course Objectives  Introduce the main components of a computer system.   

Datapath & Control (=processor) Memory System Input and Output (I/O) system

 Present an overview of the state-of-the-art microprocessors, memory systems, and I/O techniques.  Use commercial microprocessors to demonstrate these concepts.  Understand the full internal workings of a typical RISC microprocessor including the utilization of the various hardware resources during the execution of instructions.  Introduce assembly language programming, and use a software simulator to simulate the execution of machine code on a MIPS microprocessor.  Introduce the design and implementation of a microprocessor’s datapath and control using a hardware description language (HDL).  Introduce modern memory technologies, and modern memory systems.  Introduce the design of microprocessor interfacing, basic I/O hardware, and I/O techniques and protocols: polling, interrupts, DMA.  Introduce new trends in multi-core/multi-processor systems In this course we will use the MIPS 32-bit RISC microprocessor Prof. M. Mansour


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Basic Structures of Computers

Prof. M. Mansour


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Basic Structure of Computers: Five Main Components 

Since 1946, all computers have had five main components  Datapath, Control, Memory, Input, Output

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Processor = Control + Datapath Computer

Processor

Control (“brain”) Datapath (“brawn”)

Memory

(where programs, data live when running)

IO System

Input

Output

Keyboard, Mouse Disk (where programs, data live when not running) Display, Printer

Prof. M. Mansour


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Inside a “Modern” Processor 

AMD Barcelona processor: 4 cores

Prof. M. Mansour


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The Big Picture 

Coordination of many layers of abstraction

Application (ex: Matlab) Compiler Software Hardware

Assembler Processor

Operating System (WinXP)

Memory

I/O system

EECE 321 Instruction Set Architecture

Datapath & Control Digital Design Circuit Design Transistors Devices

Prof. M. Mansour


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Instruction Set Architecture (ISA)  

ISA is the interface between hardware and the lowest-level software. It is an abstraction layer through which hardware designers and software designers communicate. – It includes anything programmers need to know to make a binary machine language program work properly. – It defines the specs that hardware designers need to implement.

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There are many implementations of an ISA (called microarchitectures) – Varying cost and performance, but run identical software – Example: Intel and AMD implement different processors of the Intel 80x86 ISA • Pentium Processors by Intel • Athlon Processors by AMD

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An ISA comprises: – – – – – –

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Organization of memory Data types and data structures: Encodings and representations Instruction set Instruction formats Modes of addressing and accessing data items and instructions Exceptional conditions

Modern instruction set architectures: – 80x86/Pentium/K6, PowerPC, MIPS, SPARC, HP

Prof. M. Mansour


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Levels of Representation in EECE 321 temp = v[k]; v[k] = v[k+1]; v[k+1] = temp;

High-level Language Program (e.g., C)

Compiler

lw lw sw sw

Assembly Language Program (e.g., MIPS)

Assembler Machine Language Program (MIPS)

Architecture Interpretation Hardware Architecture Description (e.g., VHDL)

Architecture Implementation Logic Circuit Description (VHDL) Prof. M. Mansour

0000 1010 1100 0101

1001 1111 0110 1000

$t0, $t1, $t1, $t0, 1100 0101 1010 0000

0($2) 4($2) 0($2) 4($2)

0110 1000 1111 1001

1010 0000 0101 1100

1111 1001 1000 0110

0101 1100 0000 1010

1000 0110 1001 1111

signal dataBus: std_logic_vector(31 downto 0); Component regFile port (dataBus :in std_logic_vector(31 downto 0); A,B:out std_logic_vector(31 downto 0) ); end component; Component ALU port (A,B:in std_logic_vector(31 downto 0); dataBus: out std_logic_vector(31 downto 0) ); end component; signal x, y: std_logic; y